src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "panfrost-quirks.h"
  56
  57 static const struct debug_named_value debug_options[] = {
  58         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  59         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  60         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  61         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  62         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  63         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  64         {"gles3",     PAN_DBG_GLES3,    "Enable experimental GLES3 implementation"},
  65         DEBUG_NAMED_VALUE_END
  66 };
  67
  68 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  69
  70 int pan_debug = 0;
  71
  72 static const char *
  73 panfrost_get_name(struct pipe_screen *screen)
  74 {
  75         return panfrost_model_name(pan_screen(screen)->gpu_id);
  76 }
  77
  78 static const char *
  79 panfrost_get_vendor(struct pipe_screen *screen)
  80 {
  81         return "Panfrost";
  82 }
  83
  84 static const char *
  85 panfrost_get_device_vendor(struct pipe_screen *screen)
  86 {
  87         return "Arm";
  88 }
  89
  90 static int
  91 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  92 {
  93         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  94         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  95
  96         /* Our GLES3 implementation is WIP */
  97         bool is_gles3 = pan_debug & PAN_DBG_GLES3;
  98         is_gles3 |= is_deqp;
  99
 100         switch (param) {
 101         case PIPE_CAP_NPOT_TEXTURES:
 102         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 103         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 104         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 105         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 106         case PIPE_CAP_POINT_SPRITE:
 107                 return 1;
 108
 109         case PIPE_CAP_MAX_RENDER_TARGETS:
 110                 return is_gles3 ? 4 : 1;
 111
 112         /* Throttling frames breaks pipelining */
 113         case PIPE_CAP_THROTTLE:
 114                 return 0;
 115
 116         case PIPE_CAP_OCCLUSION_QUERY:
 117                 return 1;
 118         case PIPE_CAP_QUERY_TIME_ELAPSED:
 119         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 120         case PIPE_CAP_QUERY_TIMESTAMP:
 121         case PIPE_CAP_QUERY_SO_OVERFLOW:
 122                 return 0;
 123
 124         case PIPE_CAP_TEXTURE_SWIZZLE:
 125                 return 1;
 126
 127         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 128         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 129                 return 1;
 130
 131         case PIPE_CAP_TGSI_INSTANCEID:
 132         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 133         case PIPE_CAP_PRIMITIVE_RESTART:
 134                 return 1;
 135
 136         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 137                 return is_gles3 ? 4 : 0;
 138         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 139         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 140                 return is_gles3 ? 64 : 0;
 141         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 142                 return 1;
 143
 144         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 145                 return 256;
 146
 147         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 148         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 149                 return is_gles3 ? 140 : 120;
 150         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 151                 return is_gles3 ? 300 : 120;
 152
 153         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 154                 return 16;
 155
 156                 return is_deqp;
 157
 158         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 159                 return is_gles3;
 160
 161         /* For faking GLES 3.1 for dEQP-GLES31 */
 162         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 163         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 164         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 165         case PIPE_CAP_CUBE_MAP_ARRAY:
 166                 return is_deqp;
 167
 168         /* For faking compute shaders */
 169         case PIPE_CAP_COMPUTE:
 170                 return is_deqp;
 171
 172         /* TODO: Where does this req come from in practice? */
 173         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 174                 return 1;
 175
 176         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 177                 return 4096;
 178         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 179         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 180                 return 13;
 181
 182         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 183         case PIPE_CAP_INDEP_BLEND_ENABLE:
 184         case PIPE_CAP_INDEP_BLEND_FUNC:
 185                 return 1;
 186
 187         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 188                 /* Hardware is natively upper left */
 189                 return 0;
 190
 191         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 192         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 193         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 194         case PIPE_CAP_GENERATE_MIPMAP:
 195                 return 1;
 196
 197         /* We would prefer varyings */
 198         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 199         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 200                 return 0;
 201
 202         /* I really don't want to set this CAP but let's not swim against the
 203          * tide.. */
 204         case PIPE_CAP_TGSI_TEXCOORD:
 205                 return 1;
 206
 207         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 208         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 209                 return 1;
 210
 211         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 212                 return 0xffff;
 213
 214         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 215                 return 1;
 216
 217         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 218                 return 65536;
 219
 220         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 221                 return 0;
 222
 223         case PIPE_CAP_ENDIANNESS:
 224                 return PIPE_ENDIAN_NATIVE;
 225
 226         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 227                 return 1;
 228
 229         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 230                 return -8;
 231
 232         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 233                 return 7;
 234
 235         case PIPE_CAP_VENDOR_ID:
 236         case PIPE_CAP_DEVICE_ID:
 237                 return 0xFFFFFFFF;
 238
 239         case PIPE_CAP_ACCELERATED:
 240         case PIPE_CAP_UMA:
 241         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 242         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 243         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 244         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 245                 return 1;
 246
 247         case PIPE_CAP_VIDEO_MEMORY: {
 248                 uint64_t system_memory;
 249
 250                 if (!os_get_total_physical_memory(&system_memory))
 251                         return 0;
 252
 253                 return (int)(system_memory >> 20);
 254         }
 255
 256         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 257                 return 1;
 258
 259         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 260                 return 4;
 261
 262         case PIPE_CAP_MAX_VARYINGS:
 263                 return 16;
 264
 265         case PIPE_CAP_ALPHA_TEST:
 266         case PIPE_CAP_FLATSHADE:
 267         case PIPE_CAP_TWO_SIDED_COLOR:
 268         case PIPE_CAP_CLIP_PLANES:
 269                 return 0;
 270
 271         case PIPE_CAP_PACKED_STREAM_OUTPUT:
 272                 return 0;
 273
 274         case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
 275         case PIPE_CAP_PSIZ_CLAMPED:
 276                 return 1;
 277
 278         default:
 279                 return u_pipe_screen_get_param_defaults(screen, param);
 280         }
 281 }
 282
 283 static int
 284 panfrost_get_shader_param(struct pipe_screen *screen,
 285                           enum pipe_shader_type shader,
 286                           enum pipe_shader_cap param)
 287 {
 288         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 289
 290         if (shader != PIPE_SHADER_VERTEX &&
 291             shader != PIPE_SHADER_FRAGMENT &&
 292             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 293                 return 0;
 294
 295         /* this is probably not totally correct.. but it's a start: */
 296         switch (param) {
 297         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 298         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 299         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 300         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 301                 return 16384;
 302
 303         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 304                 return 1024;
 305
 306         case PIPE_SHADER_CAP_MAX_INPUTS:
 307                 return 16;
 308
 309         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 310                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
 311
 312         case PIPE_SHADER_CAP_MAX_TEMPS:
 313                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 314
 315         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 316                 return 16 * 1024 * sizeof(float);
 317
 318         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 319                 return PAN_MAX_CONST_BUFFERS;
 320
 321         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 322                 return 0;
 323
 324         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 325                 return 1;
 326         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 327                 return 0;
 328
 329         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 330                 return 0;
 331
 332         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 333                 return 1;
 334
 335         case PIPE_SHADER_CAP_SUBROUTINES:
 336                 return 0;
 337
 338         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 339                 return 0;
 340
 341         case PIPE_SHADER_CAP_INTEGERS:
 342                 return 1;
 343
 344         case PIPE_SHADER_CAP_INT64_ATOMICS:
 345         case PIPE_SHADER_CAP_FP16:
 346         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 347         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 348         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 349         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 350         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 351                 return 0;
 352
 353         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 354         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 355                 return 16; /* XXX: How many? */
 356
 357         case PIPE_SHADER_CAP_PREFERRED_IR:
 358                 return PIPE_SHADER_IR_NIR;
 359
 360         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 361                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 362
 363         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 364                 return 32;
 365
 366         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 367         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 368                 return is_deqp ? 8 : 0;
 369         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 370         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 371                 return 0;
 372
 373         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 374         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 375                 return 0;
 376
 377         default:
 378                 DBG("unknown shader param %d\n", param);
 379                 return 0;
 380         }
 381
 382         return 0;
 383 }
 384
 385 static float
 386 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 387 {
 388         switch (param) {
 389         case PIPE_CAPF_MAX_LINE_WIDTH:
 390
 391         /* fall-through */
 392         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 393                 return 255.0; /* arbitrary */
 394
 395         case PIPE_CAPF_MAX_POINT_WIDTH:
 396
 397         /* fall-through */
 398         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 399                 return 1024.0;
 400
 401         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 402                 return 16.0;
 403
 404         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 405                 return 16.0; /* arbitrary */
 406
 407         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 408         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 409         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 410                 return 0.0f;
 411
 412         default:
 413                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 414                 return 0.0;
 415         }
 416 }
 417
 418 /**
 419  * Query format support for creating a texture, drawing surface, etc.
 420  * \param format  the format to test
 421  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 422  */
 423 static bool
 424 panfrost_is_format_supported( struct pipe_screen *screen,
 425                               enum pipe_format format,
 426                               enum pipe_texture_target target,
 427                               unsigned sample_count,
 428                               unsigned storage_sample_count,
 429                               unsigned bind)
 430 {
 431         const struct util_format_description *format_desc;
 432
 433         assert(target == PIPE_BUFFER ||
 434                target == PIPE_TEXTURE_1D ||
 435                target == PIPE_TEXTURE_1D_ARRAY ||
 436                target == PIPE_TEXTURE_2D ||
 437                target == PIPE_TEXTURE_2D_ARRAY ||
 438                target == PIPE_TEXTURE_RECT ||
 439                target == PIPE_TEXTURE_3D ||
 440                target == PIPE_TEXTURE_CUBE ||
 441                target == PIPE_TEXTURE_CUBE_ARRAY);
 442
 443         format_desc = util_format_description(format);
 444
 445         if (!format_desc)
 446                 return false;
 447
 448         /* MSAA 4x supported, but no more. Technically some revisions of the
 449          * hardware can go up to 16x but we don't support higher modes yet. */
 450
 451         if (sample_count > 1 && !(pan_debug & PAN_DBG_DEQP))
 452                 return false;
 453
 454         if (sample_count > 4)
 455                 return false;
 456
 457         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 458                 return false;
 459
 460         /* Format wishlist */
 461         if (format == PIPE_FORMAT_X8Z24_UNORM)
 462                 return false;
 463
 464         if (format == PIPE_FORMAT_A1B5G5R5_UNORM || format == PIPE_FORMAT_X1B5G5R5_UNORM)
 465                 return false;
 466
 467         /* TODO */
 468         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 469                 return FALSE;
 470
 471         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 472          * more alpha than they ask for */
 473
 474         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 475         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 476
 477         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 478                 return false;
 479
 480         switch (format_desc->layout) {
 481                 case UTIL_FORMAT_LAYOUT_PLAIN:
 482                 case UTIL_FORMAT_LAYOUT_OTHER:
 483                         break;
 484                 case UTIL_FORMAT_LAYOUT_ETC:
 485                 case UTIL_FORMAT_LAYOUT_ASTC:
 486                         return true;
 487                 default:
 488                         return false;
 489         }
 490
 491         /* Internally, formats that are depth/stencil renderable are limited.
 492          *
 493          * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
 494          * rendering perspective. That is, we render to Z24S8 (which we can
 495          * AFBC compress), ignore the different when texturing (who cares?),
 496          * and then in the off-chance there's a CPU read we blit back to
 497          * staging.
 498          *
 499          * ...alternatively, we can make the state tracker deal with that. */
 500
 501         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 502                 switch (format) {
 503                         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 504                         case PIPE_FORMAT_Z24X8_UNORM:
 505                         case PIPE_FORMAT_Z32_UNORM:
 506                         case PIPE_FORMAT_Z32_FLOAT:
 507                         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 508                                 return true;
 509
 510                         default:
 511                                 return false;
 512                 }
 513         }
 514
 515         return true;
 516 }
 517
 518 static int
 519 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 520                 enum pipe_compute_cap param, void *ret)
 521 {
 522         const char * const ir = "panfrost";
 523
 524         if (!(pan_debug & PAN_DBG_DEQP))
 525                 return 0;
 526
 527 #define RET(x) do {                  \
 528    if (ret)                          \
 529       memcpy(ret, x, sizeof(x));     \
 530    return sizeof(x);                 \
 531 } while (0)
 532
 533         switch (param) {
 534         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 535                 RET((uint32_t []){ 64 });
 536
 537         case PIPE_COMPUTE_CAP_IR_TARGET:
 538                 if (ret)
 539                         sprintf(ret, "%s", ir);
 540                 return strlen(ir) * sizeof(char);
 541
 542         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 543                 RET((uint64_t []) { 3 });
 544
 545         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 546                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 547
 548         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 549                 RET(((uint64_t []) { 1024, 1024, 64 }));
 550
 551         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 552                 RET((uint64_t []) { 1024 });
 553
 554         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 555                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 556
 557         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 558                 RET((uint64_t []) { 32768 });
 559
 560         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 561         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 562                 RET((uint64_t []) { 4096 });
 563
 564         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 565                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 566
 567         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 568                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 569
 570         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 571                 RET((uint32_t []) { 9999 });  // TODO
 572
 573         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 574                 RET((uint32_t []) { 1 }); // TODO
 575
 576         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 577                 RET((uint32_t []) { 32 });  // TODO
 578
 579         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 580                 RET((uint64_t []) { 1024 }); // TODO
 581         }
 582
 583         return 0;
 584 }
 585
 586 static void
 587 panfrost_destroy_screen(struct pipe_screen *pscreen)
 588 {
 589         struct panfrost_screen *screen = pan_screen(pscreen);
 590         panfrost_bo_cache_evict_all(screen);
 591         pthread_mutex_destroy(&screen->bo_cache.lock);
 592         pthread_mutex_destroy(&screen->active_bos_lock);
 593         drmFreeVersion(screen->kernel_version);
 594         ralloc_free(screen);
 595 }
 596
 597 static uint64_t
 598 panfrost_get_timestamp(struct pipe_screen *_screen)
 599 {
 600         return os_time_get_nano();
 601 }
 602
 603 static void
 604 panfrost_fence_reference(struct pipe_screen *pscreen,
 605                          struct pipe_fence_handle **ptr,
 606                          struct pipe_fence_handle *fence)
 607 {
 608         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 609         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 610         struct panfrost_fence *old = *p;
 611
 612         if (pipe_reference(&(*p)->reference, &f->reference)) {
 613                 util_dynarray_foreach(&old->syncfds, int, fd)
 614                         close(*fd);
 615                 util_dynarray_fini(&old->syncfds);
 616                 free(old);
 617         }
 618         *p = f;
 619 }
 620
 621 static bool
 622 panfrost_fence_finish(struct pipe_screen *pscreen,
 623                       struct pipe_context *ctx,
 624                       struct pipe_fence_handle *fence,
 625                       uint64_t timeout)
 626 {
 627         struct panfrost_screen *screen = pan_screen(pscreen);
 628         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 629         struct util_dynarray syncobjs;
 630         int ret;
 631
 632         /* All fences were already signaled */
 633         if (!util_dynarray_num_elements(&f->syncfds, int))
 634                 return true;
 635
 636         util_dynarray_init(&syncobjs, NULL);
 637         util_dynarray_foreach(&f->syncfds, int, fd) {
 638                 uint32_t syncobj;
 639
 640                 ret = drmSyncobjCreate(screen->fd, 0, &syncobj);
 641                 assert(!ret);
 642
 643                 ret = drmSyncobjImportSyncFile(screen->fd, syncobj, *fd);
 644                 assert(!ret);
 645                 util_dynarray_append(&syncobjs, uint32_t, syncobj);
 646         }
 647
 648         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 649         if (abs_timeout == OS_TIMEOUT_INFINITE)
 650                 abs_timeout = INT64_MAX;
 651
 652         ret = drmSyncobjWait(screen->fd, util_dynarray_begin(&syncobjs),
 653                              util_dynarray_num_elements(&syncobjs, uint32_t),
 654                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 655                              NULL);
 656
 657         util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
 658                 drmSyncobjDestroy(screen->fd, *syncobj);
 659
 660         return ret >= 0;
 661 }
 662
 663 struct panfrost_fence *
 664 panfrost_fence_create(struct panfrost_context *ctx,
 665                       struct util_dynarray *fences)
 666 {
 667         struct panfrost_screen *screen = pan_screen(ctx->base.screen);
 668         struct panfrost_fence *f = calloc(1, sizeof(*f));
 669         if (!f)
 670                 return NULL;
 671
 672         util_dynarray_init(&f->syncfds, NULL);
 673
 674         /* Export fences from all pending batches. */
 675         util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
 676                 int fd = -1;
 677
 678                 /* The fence is already signaled, no need to export it. */
 679                 if ((*fence)->signaled)
 680                         continue;
 681
 682                 drmSyncobjExportSyncFile(screen->fd, (*fence)->syncobj, &fd);
 683                 if (fd == -1)
 684                         fprintf(stderr, "export failed: %m\n");
 685
 686                 assert(fd != -1);
 687                 util_dynarray_append(&f->syncfds, int, fd);
 688         }
 689
 690         pipe_reference_init(&f->reference, 1);
 691
 692         return f;
 693 }
 694
 695 static const void *
 696 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 697                                      enum pipe_shader_ir ir,
 698                                      enum pipe_shader_type shader)
 699 {
 700         return &midgard_nir_options;
 701 }
 702
 703 static uint32_t
 704 panfrost_active_bos_hash(const void *key)
 705 {
 706         const struct panfrost_bo *bo = key;
 707
 708         return _mesa_hash_data(&bo->gem_handle, sizeof(bo->gem_handle));
 709 }
 710
 711 static bool
 712 panfrost_active_bos_cmp(const void *keya, const void *keyb)
 713 {
 714         const struct panfrost_bo *a = keya, *b = keyb;
 715
 716         return a->gem_handle == b->gem_handle;
 717 }
 718
 719 struct pipe_screen *
 720 panfrost_create_screen(int fd, struct renderonly *ro)
 721 {
 722         pan_debug = debug_get_option_pan_debug();
 723
 724         /* Blacklist apps known to be buggy under Panfrost */
 725         const char *proc = util_get_process_name();
 726         const char *blacklist[] = {
 727                 "chromium",
 728                 "chrome",
 729         };
 730
 731         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 732                 if ((strcmp(blacklist[i], proc) == 0))
 733                         return NULL;
 734         }
 735
 736         /* Create the screen */
 737         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 738
 739         if (!screen)
 740                 return NULL;
 741
 742         if (ro) {
 743                 screen->ro = renderonly_dup(ro);
 744                 if (!screen->ro) {
 745                         DBG("Failed to dup renderonly object\n");
 746                         free(screen);
 747                         return NULL;
 748                 }
 749         }
 750
 751         screen->fd = fd;
 752
 753         screen->gpu_id = panfrost_query_gpu_version(screen->fd);
 754         screen->core_count = panfrost_query_core_count(screen->fd);
 755         screen->thread_tls_alloc = panfrost_query_thread_tls_alloc(screen->fd);
 756         screen->quirks = panfrost_get_quirks(screen->gpu_id);
 757         screen->kernel_version = drmGetVersion(fd);
 758
 759         /* Check if we're loading against a supported GPU model. */
 760
 761         switch (screen->gpu_id) {
 762         case 0x720: /* T720 */
 763         case 0x750: /* T760 */
 764         case 0x820: /* T820 */
 765         case 0x860: /* T860 */
 766                 break;
 767         default:
 768                 /* Fail to load against untested models */
 769                 debug_printf("panfrost: Unsupported model %X", screen->gpu_id);
 770                 return NULL;
 771         }
 772
 773         pthread_mutex_init(&screen->active_bos_lock, NULL);
 774         screen->active_bos = _mesa_set_create(screen, panfrost_active_bos_hash,
 775                                               panfrost_active_bos_cmp);
 776
 777         pthread_mutex_init(&screen->bo_cache.lock, NULL);
 778         list_inithead(&screen->bo_cache.lru);
 779         for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache.buckets); ++i)
 780                 list_inithead(&screen->bo_cache.buckets[i]);
 781
 782         if (pan_debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 783                 pandecode_initialize(!(pan_debug & PAN_DBG_TRACE));
 784
 785         screen->base.destroy = panfrost_destroy_screen;
 786
 787         screen->base.get_name = panfrost_get_name;
 788         screen->base.get_vendor = panfrost_get_vendor;
 789         screen->base.get_device_vendor = panfrost_get_device_vendor;
 790         screen->base.get_param = panfrost_get_param;
 791         screen->base.get_shader_param = panfrost_get_shader_param;
 792         screen->base.get_compute_param = panfrost_get_compute_param;
 793         screen->base.get_paramf = panfrost_get_paramf;
 794         screen->base.get_timestamp = panfrost_get_timestamp;
 795         screen->base.is_format_supported = panfrost_is_format_supported;
 796         screen->base.context_create = panfrost_create_context;
 797         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 798         screen->base.fence_reference = panfrost_fence_reference;
 799         screen->base.fence_finish = panfrost_fence_finish;
 800         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 801
 802         panfrost_resource_screen_init(screen);
 803
 804         return &screen->base;
 805 }