src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "bifrost/bifrost_compile.h"
  56 #include "panfrost-quirks.h"
  57
  58 static const struct debug_named_value debug_options[] = {
  59         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  60         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  61         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  62         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  63         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  64         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  65         {"nofp16",     PAN_DBG_NOFP16,     "Disable 16-bit support"},
  66         {"bifrost",   PAN_DBG_BIFROST, "Enable experimental Mali G31 and G52 support"},
  67         {"gl3",       PAN_DBG_GL3,      "Enable experimental GL 3.x implementation, up to 3.3"},
  68         DEBUG_NAMED_VALUE_END
  69 };
  70
  71 static const char *
  72 panfrost_get_name(struct pipe_screen *screen)
  73 {
  74         return panfrost_model_name(pan_device(screen)->gpu_id);
  75 }
  76
  77 static const char *
  78 panfrost_get_vendor(struct pipe_screen *screen)
  79 {
  80         return "Panfrost";
  81 }
  82
  83 static const char *
  84 panfrost_get_device_vendor(struct pipe_screen *screen)
  85 {
  86         return "Arm";
  87 }
  88
  89 static int
  90 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  91 {
  92         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  93         struct panfrost_device *dev = pan_device(screen);
  94         bool is_deqp = dev->debug & PAN_DBG_DEQP;
  95
  96         /* Our GL 3.x implementation is WIP */
  97         bool is_gl3 = dev->debug & PAN_DBG_GL3;
  98         is_gl3 |= is_deqp;
  99
 100         /* Don't expose MRT related CAPs on GPUs that don't implement them */
 101         bool has_mrt = !(dev->quirks & MIDGARD_SFBD);
 102
 103         /* Bifrost is WIP. No MRT support yet. */
 104         bool is_bifrost = (dev->quirks & IS_BIFROST);
 105         has_mrt &= !is_bifrost;
 106
 107         switch (param) {
 108         case PIPE_CAP_NPOT_TEXTURES:
 109         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 110         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 111         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 112         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 113         case PIPE_CAP_POINT_SPRITE:
 114         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 115         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 116         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 117         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 118                 return 1;
 119
 120         case PIPE_CAP_MAX_RENDER_TARGETS:
 121         case PIPE_CAP_FBFETCH:
 122         case PIPE_CAP_FBFETCH_COHERENT:
 123                 return has_mrt ? 8 : 1;
 124
 125         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 126                 return 1;
 127
 128         case PIPE_CAP_SAMPLE_SHADING:
 129                 /* WIP */
 130                 return is_gl3 ? 1 : 0;
 131
 132
 133         /* ES3 features unsupported on Bifrost */
 134         case PIPE_CAP_OCCLUSION_QUERY:
 135         case PIPE_CAP_TGSI_INSTANCEID:
 136         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 137         case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 138         case PIPE_CAP_PRIMITIVE_RESTART:
 139         case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
 140                 return !is_bifrost;
 141
 142         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 143         case PIPE_CAP_TEXTURE_SWIZZLE:
 144         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 145         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 146         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 147         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 148         case PIPE_CAP_INDEP_BLEND_ENABLE:
 149         case PIPE_CAP_INDEP_BLEND_FUNC:
 150         case PIPE_CAP_GENERATE_MIPMAP:
 151         case PIPE_CAP_ACCELERATED:
 152         case PIPE_CAP_UMA:
 153         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 154         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 155         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 156         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 157                 return 1;
 158
 159         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 160                 return is_bifrost ? 0 : 4;
 161         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 162         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 163                 return is_bifrost ? 0 : 64;
 164         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 165                 return is_bifrost ? 0 : 1;
 166
 167         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 168                 return is_bifrost ? 0 : 256;
 169
 170         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 171         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 172                 return is_gl3 ? 330 : (is_bifrost ? 120 : 140);
 173         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 174                 return is_bifrost ? 120 : 300;
 175
 176         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 177                 return 16;
 178
 179         /* For faking GLES 3.1 for dEQP-GLES31 */
 180         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 181         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 182         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 183         case PIPE_CAP_CUBE_MAP_ARRAY:
 184         case PIPE_CAP_COMPUTE:
 185                 return is_deqp;
 186         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 187                 return is_deqp ? 65536 : 0;
 188
 189         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 190         case PIPE_CAP_QUERY_TIMESTAMP:
 191         case PIPE_CAP_CONDITIONAL_RENDER:
 192                 return is_gl3;
 193
 194         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 195                 return 4096;
 196         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 197                 return is_bifrost ? 0 : 13;
 198         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 199                 return 13;
 200
 201         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 202                 /* Hardware is natively upper left */
 203                 return 0;
 204
 205         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 206         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 207         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 208         case PIPE_CAP_TGSI_TEXCOORD:
 209                 return 1;
 210
 211         /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
 212         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 213         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 214         case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 215                 return is_bifrost;
 216
 217         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 218         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 219                 return !is_bifrost;
 220
 221         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 222                 return 0xffff;
 223
 224         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 225                 return 0;
 226
 227         case PIPE_CAP_ENDIANNESS:
 228                 return PIPE_ENDIAN_NATIVE;
 229
 230                 return 1;
 231
 232         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 233                 return -8;
 234
 235         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 236                 return 7;
 237
 238         case PIPE_CAP_VIDEO_MEMORY: {
 239                 uint64_t system_memory;
 240
 241                 if (!os_get_total_physical_memory(&system_memory))
 242                         return 0;
 243
 244                 return (int)(system_memory >> 20);
 245         }
 246
 247         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 248                 return !is_bifrost;
 249
 250         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 251                 return 4;
 252
 253         case PIPE_CAP_MAX_VARYINGS:
 254                 return 16;
 255
 256         case PIPE_CAP_ALPHA_TEST:
 257         case PIPE_CAP_FLATSHADE:
 258         case PIPE_CAP_TWO_SIDED_COLOR:
 259         case PIPE_CAP_CLIP_PLANES:
 260                 return 0;
 261
 262         case PIPE_CAP_PACKED_STREAM_OUTPUT:
 263                 return 0;
 264
 265         case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
 266         case PIPE_CAP_PSIZ_CLAMPED:
 267                 return 1;
 268
 269         default:
 270                 return u_pipe_screen_get_param_defaults(screen, param);
 271         }
 272 }
 273
 274 static int
 275 panfrost_get_shader_param(struct pipe_screen *screen,
 276                           enum pipe_shader_type shader,
 277                           enum pipe_shader_cap param)
 278 {
 279         struct panfrost_device *dev = pan_device(screen);
 280         bool is_deqp = dev->debug & PAN_DBG_DEQP;
 281         bool is_nofp16 = dev->debug & PAN_DBG_NOFP16;
 282         bool is_bifrost = dev->quirks & IS_BIFROST;
 283
 284         if (shader != PIPE_SHADER_VERTEX &&
 285             shader != PIPE_SHADER_FRAGMENT &&
 286             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 287                 return 0;
 288
 289         /* this is probably not totally correct.. but it's a start: */
 290         switch (param) {
 291         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 292         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 293         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 294         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 295                 return 16384;
 296
 297         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 298                 return 1024;
 299
 300         case PIPE_SHADER_CAP_MAX_INPUTS:
 301                 return 16;
 302
 303         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 304                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 16;
 305
 306         case PIPE_SHADER_CAP_MAX_TEMPS:
 307                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 308
 309         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 310                 return 16 * 1024 * sizeof(float);
 311
 312         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 313                 return PAN_MAX_CONST_BUFFERS;
 314
 315         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 316                 return 0;
 317
 318         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 319                 return is_bifrost ? 0 : 1;
 320         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 321                 return 0;
 322
 323         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 324                 return 0;
 325
 326         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 327                 return is_bifrost ? 0 : 1;
 328
 329         case PIPE_SHADER_CAP_SUBROUTINES:
 330                 return 0;
 331
 332         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 333                 return 0;
 334
 335         case PIPE_SHADER_CAP_INTEGERS:
 336                 return 1;
 337
 338         case PIPE_SHADER_CAP_FP16:
 339         case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
 340                 return !is_nofp16;
 341
 342         case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 343         case PIPE_SHADER_CAP_INT16:
 344         case PIPE_SHADER_CAP_INT64_ATOMICS:
 345         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 346         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 347         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 348         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 349         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 350                 return 0;
 351
 352         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 353         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 354                 return 16; /* XXX: How many? */
 355
 356         case PIPE_SHADER_CAP_PREFERRED_IR:
 357                 return PIPE_SHADER_IR_NIR;
 358
 359         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 360                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 361
 362         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 363                 return 32;
 364
 365         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 366         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 367                 return is_deqp ? 8 : 0;
 368         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 369         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 370                 return 0;
 371
 372         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 373         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 374                 return 0;
 375
 376         default:
 377                 /* Other params are unknown */
 378                 return 0;
 379         }
 380
 381         return 0;
 382 }
 383
 384 static float
 385 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 386 {
 387         switch (param) {
 388         case PIPE_CAPF_MAX_LINE_WIDTH:
 389
 390         /* fall-through */
 391         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 392                 return 255.0; /* arbitrary */
 393
 394         case PIPE_CAPF_MAX_POINT_WIDTH:
 395
 396         /* fall-through */
 397         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 398                 return 1024.0;
 399
 400         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 401                 return 16.0;
 402
 403         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 404                 return 16.0; /* arbitrary */
 405
 406         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 407         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 408         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 409                 return 0.0f;
 410
 411         default:
 412                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 413                 return 0.0;
 414         }
 415 }
 416
 417 /**
 418  * Query format support for creating a texture, drawing surface, etc.
 419  * \param format  the format to test
 420  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 421  */
 422 static bool
 423 panfrost_is_format_supported( struct pipe_screen *screen,
 424                               enum pipe_format format,
 425                               enum pipe_texture_target target,
 426                               unsigned sample_count,
 427                               unsigned storage_sample_count,
 428                               unsigned bind)
 429 {
 430         struct panfrost_device *dev = pan_device(screen);
 431         const struct util_format_description *format_desc;
 432
 433         assert(target == PIPE_BUFFER ||
 434                target == PIPE_TEXTURE_1D ||
 435                target == PIPE_TEXTURE_1D_ARRAY ||
 436                target == PIPE_TEXTURE_2D ||
 437                target == PIPE_TEXTURE_2D_ARRAY ||
 438                target == PIPE_TEXTURE_RECT ||
 439                target == PIPE_TEXTURE_3D ||
 440                target == PIPE_TEXTURE_CUBE ||
 441                target == PIPE_TEXTURE_CUBE_ARRAY);
 442
 443         format_desc = util_format_description(format);
 444
 445         if (!format_desc)
 446                 return false;
 447
 448         /* MSAA 4x supported, but no more. Technically some revisions of the
 449          * hardware can go up to 16x but we don't support higher modes yet.
 450          * MSAA 2x is notably not supported and gets rounded up to MSAA 4x. */
 451
 452         if (!(sample_count == 0 || sample_count == 1 || sample_count == 4))
 453                 return false;
 454
 455         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 456                 return false;
 457
 458         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 459          * more alpha than they ask for */
 460
 461         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 462         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 463
 464         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 465                 return false;
 466
 467         /* Check we support the format with the given bind */
 468
 469         unsigned relevant_bind = bind &
 470                 ( PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET
 471                 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_SAMPLER_VIEW);
 472
 473         struct panfrost_format fmt = panfrost_pipe_format_table[format];
 474
 475         /* Also check that compressed texture formats are supported on this
 476          * particular chip. They may not be depending on system integration
 477          * differences. RGTC can be emulated so is always supported. */
 478
 479         bool is_rgtc = format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC;
 480         bool supported = panfrost_supports_compressed_format(dev, fmt.hw);
 481
 482         if (!is_rgtc && !supported)
 483                 return false;
 484
 485         return fmt.hw && ((relevant_bind & ~fmt.bind) == 0);
 486 }
 487
 488 static int
 489 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 490                 enum pipe_compute_cap param, void *ret)
 491 {
 492         struct panfrost_device *dev = pan_device(pscreen);
 493         const char * const ir = "panfrost";
 494
 495         if (!(dev->debug & PAN_DBG_DEQP))
 496                 return 0;
 497
 498 #define RET(x) do {                  \
 499    if (ret)                          \
 500       memcpy(ret, x, sizeof(x));     \
 501    return sizeof(x);                 \
 502 } while (0)
 503
 504         switch (param) {
 505         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 506                 RET((uint32_t []){ 64 });
 507
 508         case PIPE_COMPUTE_CAP_IR_TARGET:
 509                 if (ret)
 510                         sprintf(ret, "%s", ir);
 511                 return strlen(ir) * sizeof(char);
 512
 513         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 514                 RET((uint64_t []) { 3 });
 515
 516         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 517                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 518
 519         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 520                 RET(((uint64_t []) { 1024, 1024, 64 }));
 521
 522         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 523                 RET((uint64_t []) { 1024 });
 524
 525         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 526                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 527
 528         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 529                 RET((uint64_t []) { 32768 });
 530
 531         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 532         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 533                 RET((uint64_t []) { 4096 });
 534
 535         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 536                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 537
 538         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 539                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 540
 541         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 542                 RET((uint32_t []) { 9999 });  // TODO
 543
 544         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 545                 RET((uint32_t []) { 1 }); // TODO
 546
 547         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 548                 RET((uint32_t []) { 32 });  // TODO
 549
 550         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 551                 RET((uint64_t []) { 1024 }); // TODO
 552         }
 553
 554         return 0;
 555 }
 556
 557 static void
 558 panfrost_destroy_screen(struct pipe_screen *pscreen)
 559 {
 560         panfrost_close_device(pan_device(pscreen));
 561         ralloc_free(pscreen);
 562 }
 563
 564 static uint64_t
 565 panfrost_get_timestamp(struct pipe_screen *_screen)
 566 {
 567         return os_time_get_nano();
 568 }
 569
 570 static void
 571 panfrost_fence_reference(struct pipe_screen *pscreen,
 572                          struct pipe_fence_handle **ptr,
 573                          struct pipe_fence_handle *fence)
 574 {
 575         struct panfrost_device *dev = pan_device(pscreen);
 576         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 577         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 578         struct panfrost_fence *old = *p;
 579
 580         if (pipe_reference(&(*p)->reference, &f->reference)) {
 581                 drmSyncobjDestroy(dev->fd, old->syncobj);
 582                 free(old);
 583         }
 584         *p = f;
 585 }
 586
 587 static bool
 588 panfrost_fence_finish(struct pipe_screen *pscreen,
 589                       struct pipe_context *ctx,
 590                       struct pipe_fence_handle *fence,
 591                       uint64_t timeout)
 592 {
 593         struct panfrost_device *dev = pan_device(pscreen);
 594         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 595         int ret;
 596
 597         if (f->signaled)
 598                 return true;
 599
 600         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 601         if (abs_timeout == OS_TIMEOUT_INFINITE)
 602                 abs_timeout = INT64_MAX;
 603
 604         ret = drmSyncobjWait(dev->fd, &f->syncobj,
 605                              1,
 606                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 607                              NULL);
 608
 609         f->signaled = (ret >= 0);
 610         return f->signaled;
 611 }
 612
 613 struct panfrost_fence *
 614 panfrost_fence_create(struct panfrost_context *ctx,
 615                       uint32_t syncobj)
 616 {
 617         struct panfrost_fence *f = calloc(1, sizeof(*f));
 618         if (!f)
 619                 return NULL;
 620
 621         pipe_reference_init(&f->reference, 1);
 622         f->syncobj = syncobj;
 623
 624         return f;
 625 }
 626
 627 static const void *
 628 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 629                                      enum pipe_shader_ir ir,
 630                                      enum pipe_shader_type shader)
 631 {
 632         if (pan_device(pscreen)->quirks & IS_BIFROST)
 633                 return &bifrost_nir_options;
 634         else
 635                 return &midgard_nir_options;
 636 }
 637
 638 struct pipe_screen *
 639 panfrost_create_screen(int fd, struct renderonly *ro)
 640 {
 641         /* Create the screen */
 642         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 643
 644         if (!screen)
 645                 return NULL;
 646
 647         struct panfrost_device *dev = pan_device(&screen->base);
 648         panfrost_open_device(screen, fd, dev);
 649
 650         dev->debug = debug_get_flags_option("PAN_MESA_DEBUG", debug_options, 0);
 651
 652         if (ro) {
 653                 dev->ro = renderonly_dup(ro);
 654                 if (!dev->ro) {
 655                         if (dev->debug & PAN_DBG_MSGS)
 656                                 fprintf(stderr, "Failed to dup renderonly object\n");
 657
 658                         free(screen);
 659                         return NULL;
 660                 }
 661         }
 662
 663         /* Check if we're loading against a supported GPU model. */
 664
 665         switch (dev->gpu_id) {
 666         case 0x720: /* T720 */
 667         case 0x750: /* T760 */
 668         case 0x820: /* T820 */
 669         case 0x860: /* T860 */
 670                 break;
 671         case 0x7093: /* G31 */
 672         case 0x7212: /* G52 */
 673                 if (dev->debug & PAN_DBG_BIFROST)
 674                         break;
 675
 676                 /* fallthrough */
 677         default:
 678                 /* Fail to load against untested models */
 679                 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
 680                 panfrost_destroy_screen(&(screen->base));
 681                 return NULL;
 682         }
 683
 684         if (dev->debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 685                 pandecode_initialize(!(dev->debug & PAN_DBG_TRACE));
 686
 687         screen->base.destroy = panfrost_destroy_screen;
 688
 689         screen->base.get_name = panfrost_get_name;
 690         screen->base.get_vendor = panfrost_get_vendor;
 691         screen->base.get_device_vendor = panfrost_get_device_vendor;
 692         screen->base.get_param = panfrost_get_param;
 693         screen->base.get_shader_param = panfrost_get_shader_param;
 694         screen->base.get_compute_param = panfrost_get_compute_param;
 695         screen->base.get_paramf = panfrost_get_paramf;
 696         screen->base.get_timestamp = panfrost_get_timestamp;
 697         screen->base.is_format_supported = panfrost_is_format_supported;
 698         screen->base.context_create = panfrost_create_context;
 699         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 700         screen->base.fence_reference = panfrost_fence_reference;
 701         screen->base.fence_finish = panfrost_fence_finish;
 702         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 703
 704         panfrost_resource_screen_init(&screen->base);
 705
 706         if (!(dev->quirks & IS_BIFROST))
 707                 panfrost_init_blit_shaders(dev);
 708
 709         return &screen->base;
 710 }