src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_format.h"
  32 #include "util/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "pipe/p_defines.h"
  37 #include "pipe/p_screen.h"
  38 #include "draw/draw_context.h"
  39 #include <xf86drm.h>
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44
  45 #include "pan_screen.h"
  46 #include "pan_resource.h"
  47 #include "pan_public.h"
  48 #include "pan_util.h"
  49 #include "pandecode/decode.h"
  50
  51 #include "pan_context.h"
  52 #include "midgard/midgard_compile.h"
  53
  54 static const struct debug_named_value debug_options[] = {
  55         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  56         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  57         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  58         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  59         DEBUG_NAMED_VALUE_END
  60 };
  61
  62 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  63
  64 int pan_debug = 0;
  65
  66 static const char *
  67 panfrost_get_name(struct pipe_screen *screen)
  68 {
  69         return "panfrost";
  70 }
  71
  72 static const char *
  73 panfrost_get_vendor(struct pipe_screen *screen)
  74 {
  75         return "panfrost";
  76 }
  77
  78 static const char *
  79 panfrost_get_device_vendor(struct pipe_screen *screen)
  80 {
  81         return "Arm";
  82 }
  83
  84 static int
  85 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  86 {
  87         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  88         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  89
  90         switch (param) {
  91         case PIPE_CAP_NPOT_TEXTURES:
  92         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  93         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  94         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
  95         case PIPE_CAP_VERTEX_SHADER_SATURATE:
  96         case PIPE_CAP_POINT_SPRITE:
  97                 return 1;
  98
  99         case PIPE_CAP_MAX_RENDER_TARGETS:
 100                 return is_deqp ? 4 : 1;
 101
 102
 103         case PIPE_CAP_OCCLUSION_QUERY:
 104                 return 1;
 105         case PIPE_CAP_QUERY_TIME_ELAPSED:
 106         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 107         case PIPE_CAP_QUERY_TIMESTAMP:
 108         case PIPE_CAP_QUERY_SO_OVERFLOW:
 109                 return 0;
 110
 111         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 112         case PIPE_CAP_TEXTURE_SWIZZLE:
 113                 return 1;
 114
 115         case PIPE_CAP_TGSI_INSTANCEID:
 116         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 117                 return is_deqp ? 1 : 0;
 118
 119         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 120                 return is_deqp ? 4 : 0;
 121         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 122         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 123                 return is_deqp ? 64 : 0;
 124
 125         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 126                 return is_deqp ? 256 : 0; /* for GL3 */
 127
 128         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 129         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 130                 return is_deqp ? 140 : 120;
 131         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 132                 return is_deqp ? 300 : 120;
 133
 134         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 135                 return is_deqp ? 16 : 0;
 136
 137         case PIPE_CAP_CUBE_MAP_ARRAY:
 138                 return is_deqp;
 139
 140         /* For faking GLES 3.1 for dEQP-GLES31 */
 141         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 142         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 143         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 144         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 145                 return is_deqp;
 146
 147         /* For faking compute shaders */
 148         case PIPE_CAP_COMPUTE:
 149                 return is_deqp;
 150
 151         /* TODO: Where does this req come from in practice? */
 152         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 153                 return 1;
 154
 155         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 156                 return 4096;
 157         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 158         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 159                 return 13;
 160
 161         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 162         case PIPE_CAP_INDEP_BLEND_ENABLE:
 163         case PIPE_CAP_INDEP_BLEND_FUNC:
 164                 return 1;
 165
 166         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 167                 /* Hardware is natively upper left */
 168                 return 0;
 169
 170         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 171         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 172         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 173         case PIPE_CAP_GENERATE_MIPMAP:
 174                 return 1;
 175
 176         /* We would prefer varyings */
 177         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 178         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 179                 return 0;
 180
 181         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 182         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 183                 return 1;
 184
 185         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 186                 return 0xffff;
 187
 188         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 189                 return 1;
 190
 191         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 192                 return 65536;
 193
 194         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 195                 return 0;
 196
 197         case PIPE_CAP_ENDIANNESS:
 198                 return PIPE_ENDIAN_NATIVE;
 199
 200         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 201                 return 1;
 202
 203         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 204                 return -8;
 205
 206         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 207                 return 7;
 208
 209         case PIPE_CAP_VENDOR_ID:
 210         case PIPE_CAP_DEVICE_ID:
 211                 return 0xFFFFFFFF;
 212
 213         case PIPE_CAP_ACCELERATED:
 214         case PIPE_CAP_UMA:
 215         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 216         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 217         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 218         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 219                 return 1;
 220
 221         case PIPE_CAP_VIDEO_MEMORY: {
 222                 uint64_t system_memory;
 223
 224                 if (!os_get_total_physical_memory(&system_memory))
 225                         return 0;
 226
 227                 return (int)(system_memory >> 20);
 228         }
 229
 230         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 231                 return 4;
 232
 233         case PIPE_CAP_MAX_VARYINGS:
 234                 return 16;
 235
 236         default:
 237                 return u_pipe_screen_get_param_defaults(screen, param);
 238         }
 239 }
 240
 241 static int
 242 panfrost_get_shader_param(struct pipe_screen *screen,
 243                           enum pipe_shader_type shader,
 244                           enum pipe_shader_cap param)
 245 {
 246         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 247
 248         if (shader != PIPE_SHADER_VERTEX &&
 249             shader != PIPE_SHADER_FRAGMENT &&
 250             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 251                 return 0;
 252
 253         /* this is probably not totally correct.. but it's a start: */
 254         switch (param) {
 255         case PIPE_SHADER_CAP_SCALAR_ISA:
 256                 return 0;
 257
 258         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 259                 return 0;
 260         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 261         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 262         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 263                 return 16384;
 264
 265         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 266                 return 1024;
 267
 268         case PIPE_SHADER_CAP_MAX_INPUTS:
 269                 return 16;
 270
 271         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 272                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 8;
 273
 274         case PIPE_SHADER_CAP_MAX_TEMPS:
 275                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 276
 277         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 278                 return 16 * 1024 * sizeof(float);
 279
 280         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 281                 return PAN_MAX_CONST_BUFFERS;
 282
 283         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 284                 return 0;
 285
 286         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 287                 return 1;
 288         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 289                 return 0;
 290
 291         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 292                 return 0;
 293
 294         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 295                 return 1;
 296
 297         case PIPE_SHADER_CAP_SUBROUTINES:
 298                 return 0;
 299
 300         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 301                 return 0;
 302
 303         case PIPE_SHADER_CAP_INTEGERS:
 304                 return 1;
 305
 306         case PIPE_SHADER_CAP_INT64_ATOMICS:
 307         case PIPE_SHADER_CAP_FP16:
 308         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 309         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 310         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 311         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 312         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 313                 return 0;
 314
 315         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 316         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 317                 return 16; /* XXX: How many? */
 318
 319         case PIPE_SHADER_CAP_PREFERRED_IR:
 320                 return PIPE_SHADER_IR_NIR;
 321
 322         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 323                 return (1 << PIPE_SHADER_IR_NIR);
 324
 325         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 326                 return 32;
 327
 328         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 329         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 330                 return is_deqp;
 331         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 332         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 333                 return 0;
 334
 335         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 336         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 337                 return 0;
 338
 339         default:
 340                 fprintf(stderr, "unknown shader param %d\n", param);
 341                 return 0;
 342         }
 343
 344         return 0;
 345 }
 346
 347 static float
 348 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 349 {
 350         switch (param) {
 351         case PIPE_CAPF_MAX_LINE_WIDTH:
 352
 353         /* fall-through */
 354         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 355                 return 255.0; /* arbitrary */
 356
 357         case PIPE_CAPF_MAX_POINT_WIDTH:
 358
 359         /* fall-through */
 360         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 361                 return 1024.0;
 362
 363         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 364                 return 16.0;
 365
 366         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 367                 return 16.0; /* arbitrary */
 368
 369         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 370         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 371         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 372                 return 0.0f;
 373
 374         default:
 375                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 376                 return 0.0;
 377         }
 378 }
 379
 380 /**
 381  * Query format support for creating a texture, drawing surface, etc.
 382  * \param format  the format to test
 383  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 384  */
 385 static bool
 386 panfrost_is_format_supported( struct pipe_screen *screen,
 387                               enum pipe_format format,
 388                               enum pipe_texture_target target,
 389                               unsigned sample_count,
 390                               unsigned storage_sample_count,
 391                               unsigned bind)
 392 {
 393         const struct util_format_description *format_desc;
 394
 395         assert(target == PIPE_BUFFER ||
 396                target == PIPE_TEXTURE_1D ||
 397                target == PIPE_TEXTURE_1D_ARRAY ||
 398                target == PIPE_TEXTURE_2D ||
 399                target == PIPE_TEXTURE_2D_ARRAY ||
 400                target == PIPE_TEXTURE_RECT ||
 401                target == PIPE_TEXTURE_3D ||
 402                target == PIPE_TEXTURE_CUBE ||
 403                target == PIPE_TEXTURE_CUBE_ARRAY);
 404
 405         format_desc = util_format_description(format);
 406
 407         if (!format_desc)
 408                 return false;
 409
 410         if (sample_count > 1)
 411                 return false;
 412
 413         /* Format wishlist */
 414         if (format == PIPE_FORMAT_X8Z24_UNORM)
 415                 return false;
 416
 417         if (format == PIPE_FORMAT_A1B5G5R5_UNORM || format == PIPE_FORMAT_X1B5G5R5_UNORM)
 418                 return false;
 419
 420         /* TODO */
 421         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 422                 return FALSE;
 423
 424         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 425          * more alpha than they ask for */
 426
 427         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 428         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 429
 430         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 431                 return false;
 432
 433         if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN &&
 434             format_desc->layout != UTIL_FORMAT_LAYOUT_OTHER) {
 435                 /* Compressed formats not yet hooked up. */
 436                 return false;
 437         }
 438
 439         /* Internally, formats that are depth/stencil renderable are limited.
 440          *
 441          * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
 442          * rendering perspective. That is, we render to Z24S8 (which we can
 443          * AFBC compress), ignore the different when texturing (who cares?),
 444          * and then in the off-chance there's a CPU read we blit back to
 445          * staging.
 446          *
 447          * ...alternatively, we can make the state tracker deal with that. */
 448
 449         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 450                 switch (format) {
 451                         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 452                         case PIPE_FORMAT_Z24X8_UNORM:
 453                         case PIPE_FORMAT_Z32_UNORM:
 454                         case PIPE_FORMAT_Z32_FLOAT:
 455                         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 456                                 return true;
 457
 458                         default:
 459                                 return false;
 460                 }
 461         }
 462
 463         return true;
 464 }
 465
 466 static int
 467 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 468                 enum pipe_compute_cap param, void *ret)
 469 {
 470         const char * const ir = "panfrost";
 471
 472         if (!(pan_debug & PAN_DBG_DEQP))
 473                 return 0;
 474
 475 #define RET(x) do {                  \
 476    if (ret)                          \
 477       memcpy(ret, x, sizeof(x));     \
 478    return sizeof(x);                 \
 479 } while (0)
 480
 481         switch (param) {
 482         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 483                 /* TODO: We'll want 64-bit pointers soon */
 484                 RET((uint32_t []){ 32 });
 485
 486         case PIPE_COMPUTE_CAP_IR_TARGET:
 487                 if (ret)
 488                         sprintf(ret, "%s", ir);
 489                 return strlen(ir) * sizeof(char);
 490
 491         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 492                 RET((uint64_t []) { 3 });
 493
 494         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 495                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 496
 497         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 498                 RET(((uint64_t []) { 1024, 1024, 64 }));
 499
 500         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 501                 RET((uint64_t []) { 1024 });
 502
 503         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 504                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 505
 506         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 507                 RET((uint64_t []) { 32768 });
 508
 509         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 510         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 511                 RET((uint64_t []) { 4096 });
 512
 513         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 514                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 515
 516         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 517                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 518
 519         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 520                 RET((uint32_t []) { 9999 });  // TODO
 521
 522         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 523                 RET((uint32_t []) { 1 }); // TODO
 524
 525         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 526                 RET((uint32_t []) { 32 });  // TODO
 527
 528         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 529                 RET((uint64_t []) { 1024 }); // TODO
 530         }
 531
 532         return 0;
 533 }
 534
 535 static void
 536 panfrost_destroy_screen(struct pipe_screen *pscreen)
 537 {
 538         struct panfrost_screen *screen = pan_screen(pscreen);
 539         panfrost_bo_cache_evict_all(screen);
 540         ralloc_free(screen);
 541 }
 542
 543 static void
 544 panfrost_flush_frontbuffer(struct pipe_screen *_screen,
 545                            struct pipe_resource *resource,
 546                            unsigned level, unsigned layer,
 547                            void *context_private,
 548                            struct pipe_box *sub_box)
 549 {
 550         /* TODO: Display target integration */
 551 }
 552
 553 static uint64_t
 554 panfrost_get_timestamp(struct pipe_screen *_screen)
 555 {
 556         return os_time_get_nano();
 557 }
 558
 559 static void
 560 panfrost_fence_reference(struct pipe_screen *pscreen,
 561                          struct pipe_fence_handle **ptr,
 562                          struct pipe_fence_handle *fence)
 563 {
 564         panfrost_drm_fence_reference(pscreen, ptr, fence);
 565 }
 566
 567 static bool
 568 panfrost_fence_finish(struct pipe_screen *pscreen,
 569                       struct pipe_context *ctx,
 570                       struct pipe_fence_handle *fence,
 571                       uint64_t timeout)
 572 {
 573         return panfrost_drm_fence_finish(pscreen, ctx, fence, timeout);
 574 }
 575
 576 static const void *
 577 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 578                                      enum pipe_shader_ir ir,
 579                                      enum pipe_shader_type shader)
 580 {
 581         return &midgard_nir_options;
 582 }
 583
 584 struct pipe_screen *
 585 panfrost_create_screen(int fd, struct renderonly *ro)
 586 {
 587         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 588
 589         pan_debug = debug_get_option_pan_debug();
 590
 591         if (!screen)
 592                 return NULL;
 593
 594         if (ro) {
 595                 screen->ro = renderonly_dup(ro);
 596                 if (!screen->ro) {
 597                         fprintf(stderr, "Failed to dup renderonly object\n");
 598                         free(screen);
 599                         return NULL;
 600                 }
 601         }
 602
 603         screen->fd = fd;
 604
 605         screen->gpu_id = panfrost_drm_query_gpu_version(screen);
 606         screen->require_sfbd = screen->gpu_id < 0x0750; /* T760 is the first to support MFBD */
 607
 608         /* Check if we're loading against a supported GPU model. */
 609
 610         switch (screen->gpu_id) {
 611         case 0x750: /* T760 */
 612         case 0x820: /* T820 */
 613         case 0x860: /* T860 */
 614                 break;
 615         default:
 616                 /* Fail to load against untested models */
 617                 debug_printf("panfrost: Unsupported model %X",
 618                              screen->gpu_id);
 619                 return NULL;
 620         }
 621
 622         util_dynarray_init(&screen->transient_bo, screen);
 623
 624         for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache); ++i)
 625                 list_inithead(&screen->bo_cache[i]);
 626
 627         if (pan_debug & PAN_DBG_TRACE)
 628                 pandecode_initialize();
 629
 630         screen->base.destroy = panfrost_destroy_screen;
 631
 632         screen->base.get_name = panfrost_get_name;
 633         screen->base.get_vendor = panfrost_get_vendor;
 634         screen->base.get_device_vendor = panfrost_get_device_vendor;
 635         screen->base.get_param = panfrost_get_param;
 636         screen->base.get_shader_param = panfrost_get_shader_param;
 637         screen->base.get_compute_param = panfrost_get_compute_param;
 638         screen->base.get_paramf = panfrost_get_paramf;
 639         screen->base.get_timestamp = panfrost_get_timestamp;
 640         screen->base.is_format_supported = panfrost_is_format_supported;
 641         screen->base.context_create = panfrost_create_context;
 642         screen->base.flush_frontbuffer = panfrost_flush_frontbuffer;
 643         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 644         screen->base.fence_reference = panfrost_fence_reference;
 645         screen->base.fence_finish = panfrost_fence_finish;
 646
 647         screen->last_fragment_flushed = true;
 648         screen->last_job = NULL;
 649
 650         panfrost_resource_screen_init(screen);
 651
 652         return &screen->base;
 653 }