src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "bifrost/bifrost_compile.h"
  56 #include "panfrost-quirks.h"
  57
  58 static const struct debug_named_value debug_options[] = {
  59         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  60         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  61         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  62         {"afbc",      PAN_DBG_AFBC,     "Enable AFBC buffer sharing"},
  63         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  64         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  65         {"nofp16",     PAN_DBG_NOFP16,     "Disable 16-bit support"},
  66         {"bifrost",   PAN_DBG_BIFROST, "Enable experimental Mali G31 and G52 support"},
  67         {"gl3",       PAN_DBG_GL3,      "Enable experimental GL 3.x implementation, up to 3.3"},
  68         DEBUG_NAMED_VALUE_END
  69 };
  70
  71 static const char *
  72 panfrost_get_name(struct pipe_screen *screen)
  73 {
  74         return panfrost_model_name(pan_device(screen)->gpu_id);
  75 }
  76
  77 static const char *
  78 panfrost_get_vendor(struct pipe_screen *screen)
  79 {
  80         return "Panfrost";
  81 }
  82
  83 static const char *
  84 panfrost_get_device_vendor(struct pipe_screen *screen)
  85 {
  86         return "Arm";
  87 }
  88
  89 static int
  90 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  91 {
  92         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  93         struct panfrost_device *dev = pan_device(screen);
  94         bool is_deqp = dev->debug & PAN_DBG_DEQP;
  95
  96         /* Our GL 3.x implementation is WIP */
  97         bool is_gl3 = dev->debug & PAN_DBG_GL3;
  98         is_gl3 |= is_deqp;
  99
 100         /* Don't expose MRT related CAPs on GPUs that don't implement them */
 101         bool has_mrt = !(dev->quirks & MIDGARD_SFBD);
 102
 103         /* Bifrost is WIP. No MRT support yet. */
 104         bool is_bifrost = (dev->quirks & IS_BIFROST);
 105         has_mrt &= !is_bifrost;
 106
 107         switch (param) {
 108         case PIPE_CAP_NPOT_TEXTURES:
 109         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 110         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 111         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 112         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 113         case PIPE_CAP_POINT_SPRITE:
 114         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 115         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 116         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 117         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 118                 return 1;
 119
 120         case PIPE_CAP_MAX_RENDER_TARGETS:
 121         case PIPE_CAP_FBFETCH:
 122         case PIPE_CAP_FBFETCH_COHERENT:
 123                 return has_mrt ? 8 : 1;
 124
 125         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 126                 return 1;
 127
 128         case PIPE_CAP_SAMPLE_SHADING:
 129                 /* WIP */
 130                 return is_gl3 ? 1 : 0;
 131
 132
 133         /* ES3 features unsupported on Bifrost */
 134         case PIPE_CAP_OCCLUSION_QUERY:
 135         case PIPE_CAP_TGSI_INSTANCEID:
 136         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 137         case PIPE_CAP_SURFACE_SAMPLE_COUNT:
 138         case PIPE_CAP_PRIMITIVE_RESTART:
 139         case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
 140                 return !is_bifrost;
 141
 142         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 143         case PIPE_CAP_TEXTURE_SWIZZLE:
 144         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 145         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 146         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 147         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 148         case PIPE_CAP_INDEP_BLEND_ENABLE:
 149         case PIPE_CAP_INDEP_BLEND_FUNC:
 150         case PIPE_CAP_GENERATE_MIPMAP:
 151         case PIPE_CAP_ACCELERATED:
 152         case PIPE_CAP_UMA:
 153         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 154         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 155         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 156         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 157                 return 1;
 158
 159         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 160                 return is_bifrost ? 0 : 4;
 161         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 162         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 163                 return is_bifrost ? 0 : 64;
 164         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 165         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 166                 return is_bifrost ? 0 : 1;
 167
 168         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 169                 return is_bifrost ? 0 : 256;
 170
 171         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 172         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 173                 return is_gl3 ? 330 : (is_bifrost ? 120 : 140);
 174         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 175                 return is_bifrost ? 120 : 300;
 176
 177         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 178                 return 16;
 179
 180         /* For faking GLES 3.1 for dEQP-GLES31 */
 181         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 182         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 183         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 184         case PIPE_CAP_CUBE_MAP_ARRAY:
 185         case PIPE_CAP_COMPUTE:
 186                 return is_deqp;
 187         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 188                 return is_deqp ? 65536 : 0;
 189
 190         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 191         case PIPE_CAP_QUERY_TIMESTAMP:
 192         case PIPE_CAP_CONDITIONAL_RENDER:
 193                 return is_gl3;
 194
 195         /* TODO: Where does this req come from in practice? */
 196         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 197                 return 1;
 198
 199         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 200                 return 4096;
 201         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 202                 return is_bifrost ? 0 : 13;
 203         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 204                 return 13;
 205
 206         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 207                 /* Hardware is natively upper left */
 208                 return 0;
 209
 210         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 211         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 212         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 213         case PIPE_CAP_TGSI_TEXCOORD:
 214                 return 1;
 215
 216         /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
 217         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 218         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 219         case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 220                 return is_bifrost;
 221
 222         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 223         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 224                 return !is_bifrost;
 225
 226         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 227                 return 0xffff;
 228
 229         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 230                 return 0;
 231
 232         case PIPE_CAP_ENDIANNESS:
 233                 return PIPE_ENDIAN_NATIVE;
 234
 235                 return 1;
 236
 237         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 238                 return is_deqp ? 4 : 0;
 239
 240         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 241                 return -8;
 242
 243         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 244                 return 7;
 245
 246         case PIPE_CAP_VIDEO_MEMORY: {
 247                 uint64_t system_memory;
 248
 249                 if (!os_get_total_physical_memory(&system_memory))
 250                         return 0;
 251
 252                 return (int)(system_memory >> 20);
 253         }
 254
 255         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 256                 return !is_bifrost;
 257
 258         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 259                 return 4;
 260
 261         case PIPE_CAP_MAX_VARYINGS:
 262                 return 16;
 263
 264         case PIPE_CAP_ALPHA_TEST:
 265         case PIPE_CAP_FLATSHADE:
 266         case PIPE_CAP_TWO_SIDED_COLOR:
 267         case PIPE_CAP_CLIP_PLANES:
 268                 return 0;
 269
 270         case PIPE_CAP_PACKED_STREAM_OUTPUT:
 271                 return 0;
 272
 273         case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
 274         case PIPE_CAP_PSIZ_CLAMPED:
 275                 return 1;
 276
 277         default:
 278                 return u_pipe_screen_get_param_defaults(screen, param);
 279         }
 280 }
 281
 282 static int
 283 panfrost_get_shader_param(struct pipe_screen *screen,
 284                           enum pipe_shader_type shader,
 285                           enum pipe_shader_cap param)
 286 {
 287         struct panfrost_device *dev = pan_device(screen);
 288         bool is_deqp = dev->debug & PAN_DBG_DEQP;
 289         bool is_nofp16 = dev->debug & PAN_DBG_NOFP16;
 290         bool is_bifrost = dev->quirks & IS_BIFROST;
 291
 292         if (shader != PIPE_SHADER_VERTEX &&
 293             shader != PIPE_SHADER_FRAGMENT &&
 294             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 295                 return 0;
 296
 297         /* this is probably not totally correct.. but it's a start: */
 298         switch (param) {
 299         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 300         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 301         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 302         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 303                 return 16384;
 304
 305         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 306                 return 1024;
 307
 308         case PIPE_SHADER_CAP_MAX_INPUTS:
 309                 return 16;
 310
 311         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 312                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 16;
 313
 314         case PIPE_SHADER_CAP_MAX_TEMPS:
 315                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 316
 317         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 318                 return 16 * 1024 * sizeof(float);
 319
 320         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 321                 return PAN_MAX_CONST_BUFFERS;
 322
 323         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 324                 return 0;
 325
 326         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 327                 return is_bifrost ? 0 : 1;
 328         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 329                 return 0;
 330
 331         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 332                 return 0;
 333
 334         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 335                 return is_bifrost ? 0 : 1;
 336
 337         case PIPE_SHADER_CAP_SUBROUTINES:
 338                 return 0;
 339
 340         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 341                 return 0;
 342
 343         case PIPE_SHADER_CAP_INTEGERS:
 344                 return 1;
 345
 346         case PIPE_SHADER_CAP_FP16:
 347         case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
 348                 return !is_nofp16;
 349
 350         case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 351         case PIPE_SHADER_CAP_INT16:
 352         case PIPE_SHADER_CAP_INT64_ATOMICS:
 353         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 354         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 355         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 356         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 357         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 358                 return 0;
 359
 360         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 361         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 362                 return 16; /* XXX: How many? */
 363
 364         case PIPE_SHADER_CAP_PREFERRED_IR:
 365                 return PIPE_SHADER_IR_NIR;
 366
 367         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 368                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 369
 370         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 371                 return 32;
 372
 373         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 374         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 375                 return is_deqp ? 8 : 0;
 376         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 377         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 378                 return 0;
 379
 380         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 381         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 382                 return 0;
 383
 384         default:
 385                 /* Other params are unknown */
 386                 return 0;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static float
 393 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 394 {
 395         switch (param) {
 396         case PIPE_CAPF_MAX_LINE_WIDTH:
 397
 398         /* fall-through */
 399         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 400                 return 255.0; /* arbitrary */
 401
 402         case PIPE_CAPF_MAX_POINT_WIDTH:
 403
 404         /* fall-through */
 405         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 406                 return 1024.0;
 407
 408         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 409                 return 16.0;
 410
 411         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 412                 return 16.0; /* arbitrary */
 413
 414         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 415         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 416         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 417                 return 0.0f;
 418
 419         default:
 420                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 421                 return 0.0;
 422         }
 423 }
 424
 425 /**
 426  * Query format support for creating a texture, drawing surface, etc.
 427  * \param format  the format to test
 428  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 429  */
 430 static bool
 431 panfrost_is_format_supported( struct pipe_screen *screen,
 432                               enum pipe_format format,
 433                               enum pipe_texture_target target,
 434                               unsigned sample_count,
 435                               unsigned storage_sample_count,
 436                               unsigned bind)
 437 {
 438         struct panfrost_device *dev = pan_device(screen);
 439         const struct util_format_description *format_desc;
 440
 441         assert(target == PIPE_BUFFER ||
 442                target == PIPE_TEXTURE_1D ||
 443                target == PIPE_TEXTURE_1D_ARRAY ||
 444                target == PIPE_TEXTURE_2D ||
 445                target == PIPE_TEXTURE_2D_ARRAY ||
 446                target == PIPE_TEXTURE_RECT ||
 447                target == PIPE_TEXTURE_3D ||
 448                target == PIPE_TEXTURE_CUBE ||
 449                target == PIPE_TEXTURE_CUBE_ARRAY);
 450
 451         format_desc = util_format_description(format);
 452
 453         if (!format_desc)
 454                 return false;
 455
 456         /* MSAA 4x supported, but no more. Technically some revisions of the
 457          * hardware can go up to 16x but we don't support higher modes yet.
 458          * MSAA 2x is notably not supported and gets rounded up to MSAA 4x. */
 459
 460         if (!(sample_count == 0 || sample_count == 1 || sample_count == 4))
 461                 return false;
 462
 463         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 464                 return false;
 465
 466         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 467          * more alpha than they ask for */
 468
 469         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 470         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 471
 472         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 473                 return false;
 474
 475         /* Check we support the format with the given bind */
 476
 477         unsigned relevant_bind = bind &
 478                 ( PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET
 479                 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_SAMPLER_VIEW);
 480
 481         struct panfrost_format fmt = panfrost_pipe_format_table[format];
 482
 483         /* Also check that compressed texture formats are supported on this
 484          * particular chip. They may not be depending on system integration
 485          * differences. RGTC can be emulated so is always supported. */
 486
 487         bool is_rgtc = format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC;
 488         bool supported = panfrost_supports_compressed_format(dev, fmt.hw);
 489
 490         if (!is_rgtc && !supported)
 491                 return false;
 492
 493         return fmt.hw && ((relevant_bind & ~fmt.bind) == 0);
 494 }
 495
 496 /* We always support linear and tiled operations, both external and internal.
 497  * We support AFBC for a subset of formats, and colourspace transform for a
 498  * subset of those. */
 499
 500 static void
 501 panfrost_query_dmabuf_modifiers(struct pipe_screen *screen,
 502                 enum pipe_format format, int max, uint64_t *modifiers, unsigned
 503                 int *external_only, int *out_count)
 504 {
 505         /* Query AFBC status */
 506         bool afbc = panfrost_format_supports_afbc(format);
 507         bool ytr = panfrost_afbc_can_ytr(format);
 508
 509         /* Don't advertise AFBC before T760 */
 510         struct panfrost_device *dev = pan_device(screen);
 511         afbc &= !(dev->quirks & MIDGARD_NO_AFBC);
 512
 513         /* XXX: AFBC scanout is broken on mainline RK3399 with older kernels */
 514         afbc &= (dev->debug & PAN_DBG_AFBC);
 515
 516         unsigned count = 0;
 517
 518         for (unsigned i = 0; i < PAN_MODIFIER_COUNT; ++i) {
 519                 if (drm_is_afbc(pan_best_modifiers[i]) && !afbc)
 520                         continue;
 521
 522                 if ((pan_best_modifiers[i] & AFBC_FORMAT_MOD_YTR) && !ytr)
 523                         continue;
 524
 525                 count++;
 526
 527                 if (max > (int) count) {
 528                         modifiers[count] = pan_best_modifiers[i];
 529
 530                         if (external_only)
 531                                 external_only[count] = false;
 532                 }
 533         }
 534
 535         *out_count = count;
 536 }
 537
 538 static int
 539 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 540                 enum pipe_compute_cap param, void *ret)
 541 {
 542         struct panfrost_device *dev = pan_device(pscreen);
 543         const char * const ir = "panfrost";
 544
 545         if (!(dev->debug & PAN_DBG_DEQP))
 546                 return 0;
 547
 548 #define RET(x) do {                  \
 549    if (ret)                          \
 550       memcpy(ret, x, sizeof(x));     \
 551    return sizeof(x);                 \
 552 } while (0)
 553
 554         switch (param) {
 555         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 556                 RET((uint32_t []){ 64 });
 557
 558         case PIPE_COMPUTE_CAP_IR_TARGET:
 559                 if (ret)
 560                         sprintf(ret, "%s", ir);
 561                 return strlen(ir) * sizeof(char);
 562
 563         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 564                 RET((uint64_t []) { 3 });
 565
 566         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 567                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 568
 569         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 570                 RET(((uint64_t []) { 1024, 1024, 64 }));
 571
 572         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 573                 RET((uint64_t []) { 1024 });
 574
 575         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 576                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 577
 578         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 579                 RET((uint64_t []) { 32768 });
 580
 581         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 582         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 583                 RET((uint64_t []) { 4096 });
 584
 585         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 586                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 587
 588         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 589                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 590
 591         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 592                 RET((uint32_t []) { 9999 });  // TODO
 593
 594         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 595                 RET((uint32_t []) { 1 }); // TODO
 596
 597         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 598                 RET((uint32_t []) { 32 });  // TODO
 599
 600         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 601                 RET((uint64_t []) { 1024 }); // TODO
 602         }
 603
 604         return 0;
 605 }
 606
 607 static void
 608 panfrost_destroy_screen(struct pipe_screen *pscreen)
 609 {
 610         panfrost_close_device(pan_device(pscreen));
 611         ralloc_free(pscreen);
 612 }
 613
 614 static uint64_t
 615 panfrost_get_timestamp(struct pipe_screen *_screen)
 616 {
 617         return os_time_get_nano();
 618 }
 619
 620 static void
 621 panfrost_fence_reference(struct pipe_screen *pscreen,
 622                          struct pipe_fence_handle **ptr,
 623                          struct pipe_fence_handle *fence)
 624 {
 625         struct panfrost_device *dev = pan_device(pscreen);
 626         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 627         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 628         struct panfrost_fence *old = *p;
 629
 630         if (pipe_reference(&(*p)->reference, &f->reference)) {
 631                 drmSyncobjDestroy(dev->fd, old->syncobj);
 632                 free(old);
 633         }
 634         *p = f;
 635 }
 636
 637 static bool
 638 panfrost_fence_finish(struct pipe_screen *pscreen,
 639                       struct pipe_context *ctx,
 640                       struct pipe_fence_handle *fence,
 641                       uint64_t timeout)
 642 {
 643         struct panfrost_device *dev = pan_device(pscreen);
 644         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 645         int ret;
 646
 647         if (f->signaled)
 648                 return true;
 649
 650         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 651         if (abs_timeout == OS_TIMEOUT_INFINITE)
 652                 abs_timeout = INT64_MAX;
 653
 654         ret = drmSyncobjWait(dev->fd, &f->syncobj,
 655                              1,
 656                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 657                              NULL);
 658
 659         f->signaled = (ret >= 0);
 660         return f->signaled;
 661 }
 662
 663 struct panfrost_fence *
 664 panfrost_fence_create(struct panfrost_context *ctx,
 665                       uint32_t syncobj)
 666 {
 667         struct panfrost_fence *f = calloc(1, sizeof(*f));
 668         if (!f)
 669                 return NULL;
 670
 671         pipe_reference_init(&f->reference, 1);
 672         f->syncobj = syncobj;
 673
 674         return f;
 675 }
 676
 677 static const void *
 678 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 679                                      enum pipe_shader_ir ir,
 680                                      enum pipe_shader_type shader)
 681 {
 682         if (pan_device(pscreen)->quirks & IS_BIFROST)
 683                 return &bifrost_nir_options;
 684         else
 685                 return &midgard_nir_options;
 686 }
 687
 688 struct pipe_screen *
 689 panfrost_create_screen(int fd, struct renderonly *ro)
 690 {
 691         /* Create the screen */
 692         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 693
 694         if (!screen)
 695                 return NULL;
 696
 697         struct panfrost_device *dev = pan_device(&screen->base);
 698         panfrost_open_device(screen, fd, dev);
 699
 700         dev->debug = debug_get_flags_option("PAN_MESA_DEBUG", debug_options, 0);
 701
 702         if (ro) {
 703                 dev->ro = renderonly_dup(ro);
 704                 if (!dev->ro) {
 705                         if (dev->debug & PAN_DBG_MSGS)
 706                                 fprintf(stderr, "Failed to dup renderonly object\n");
 707
 708                         free(screen);
 709                         return NULL;
 710                 }
 711         }
 712
 713         /* Check if we're loading against a supported GPU model. */
 714
 715         switch (dev->gpu_id) {
 716         case 0x720: /* T720 */
 717         case 0x750: /* T760 */
 718         case 0x820: /* T820 */
 719         case 0x860: /* T860 */
 720                 break;
 721         case 0x7093: /* G31 */
 722         case 0x7212: /* G52 */
 723                 if (dev->debug & PAN_DBG_BIFROST)
 724                         break;
 725
 726                 /* fallthrough */
 727         default:
 728                 /* Fail to load against untested models */
 729                 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
 730                 panfrost_destroy_screen(&(screen->base));
 731                 return NULL;
 732         }
 733
 734         if (dev->debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 735                 pandecode_initialize(!(dev->debug & PAN_DBG_TRACE));
 736
 737         screen->base.destroy = panfrost_destroy_screen;
 738
 739         screen->base.get_name = panfrost_get_name;
 740         screen->base.get_vendor = panfrost_get_vendor;
 741         screen->base.get_device_vendor = panfrost_get_device_vendor;
 742         screen->base.get_param = panfrost_get_param;
 743         screen->base.get_shader_param = panfrost_get_shader_param;
 744         screen->base.get_compute_param = panfrost_get_compute_param;
 745         screen->base.get_paramf = panfrost_get_paramf;
 746         screen->base.get_timestamp = panfrost_get_timestamp;
 747         screen->base.is_format_supported = panfrost_is_format_supported;
 748         screen->base.query_dmabuf_modifiers = panfrost_query_dmabuf_modifiers;
 749         screen->base.context_create = panfrost_create_context;
 750         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 751         screen->base.fence_reference = panfrost_fence_reference;
 752         screen->base.fence_finish = panfrost_fence_finish;
 753         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 754
 755         panfrost_resource_screen_init(&screen->base);
 756
 757         if (!(dev->quirks & IS_BIFROST))
 758                 panfrost_init_blit_shaders(dev);
 759
 760         return &screen->base;
 761 }