panfrost: Don't advertise MSAA 2x
[mesa.git] / src / gallium / drivers / panfrost / pan_screen.c
1 /*
2 * Copyright (C) 2008 VMware, Inc.
3 * Copyright (C) 2014 Broadcom
4 * Copyright (C) 2018 Alyssa Rosenzweig
5 * Copyright (C) 2019 Collabora, Ltd.
6 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * SOFTWARE.
26 *
27 */
28
29 #include "util/u_debug.h"
30 #include "util/u_memory.h"
31 #include "util/format/u_format.h"
32 #include "util/format/u_format_s3tc.h"
33 #include "util/u_video.h"
34 #include "util/u_screen.h"
35 #include "util/os_time.h"
36 #include "util/u_process.h"
37 #include "pipe/p_defines.h"
38 #include "pipe/p_screen.h"
39 #include "draw/draw_context.h"
40
41 #include <fcntl.h>
42
43 #include "drm-uapi/drm_fourcc.h"
44 #include "drm-uapi/panfrost_drm.h"
45
46 #include "pan_bo.h"
47 #include "pan_screen.h"
48 #include "pan_resource.h"
49 #include "pan_public.h"
50 #include "pan_util.h"
51 #include "pandecode/decode.h"
52
53 #include "pan_context.h"
54 #include "midgard/midgard_compile.h"
55 #include "bifrost/bifrost_compile.h"
56 #include "panfrost-quirks.h"
57
58 static const struct debug_named_value debug_options[] = {
59 {"msgs", PAN_DBG_MSGS, "Print debug messages"},
60 {"trace", PAN_DBG_TRACE, "Trace the command stream"},
61 {"deqp", PAN_DBG_DEQP, "Hacks for dEQP"},
62 {"afbc", PAN_DBG_AFBC, "Enable non-conformant AFBC impl"},
63 {"sync", PAN_DBG_SYNC, "Wait for each job's completion and check for any GPU fault"},
64 {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
65 {"gles3", PAN_DBG_GLES3, "Enable experimental GLES3 implementation"},
66 {"fp16", PAN_DBG_FP16, "Enable buggy experimental (don't use!) fp16"},
67 {"bifrost", PAN_DBG_BIFROST, "Enable experimental Mali G31 and G52 support"},
68 {"gl3", PAN_DBG_GL3, "Enable experimental GL 3.x implementation, up to 3.3"},
69 DEBUG_NAMED_VALUE_END
70 };
71
72 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
73
74 int pan_debug = 0;
75
76 static const char *
77 panfrost_get_name(struct pipe_screen *screen)
78 {
79 return panfrost_model_name(pan_device(screen)->gpu_id);
80 }
81
82 static const char *
83 panfrost_get_vendor(struct pipe_screen *screen)
84 {
85 return "Panfrost";
86 }
87
88 static const char *
89 panfrost_get_device_vendor(struct pipe_screen *screen)
90 {
91 return "Arm";
92 }
93
94 static int
95 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
96 {
97 /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
98 bool is_deqp = pan_debug & PAN_DBG_DEQP;
99 struct panfrost_device *dev = pan_device(screen);
100
101 /* Our GL 3.x implementation is WIP */
102 bool is_gl3 = pan_debug & PAN_DBG_GL3;
103 is_gl3 |= is_deqp;
104
105 /* Same with GLES 3 */
106 bool is_gles3 = pan_debug & PAN_DBG_GLES3;
107 is_gles3 |= is_gl3;
108
109 switch (param) {
110 case PIPE_CAP_NPOT_TEXTURES:
111 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
112 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
113 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
114 case PIPE_CAP_VERTEX_SHADER_SATURATE:
115 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
116 case PIPE_CAP_POINT_SPRITE:
117 case PIPE_CAP_DEPTH_CLIP_DISABLE:
118 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
119 return 1;
120
121 case PIPE_CAP_MAX_RENDER_TARGETS:
122 return is_gles3 ? 4 : 1;
123
124 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
125 return is_gl3 ? 1 : 0;
126
127 /* Throttling frames breaks pipelining */
128 case PIPE_CAP_THROTTLE:
129 return 0;
130
131 case PIPE_CAP_OCCLUSION_QUERY:
132 return 1;
133 case PIPE_CAP_QUERY_TIME_ELAPSED:
134 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
135 case PIPE_CAP_QUERY_SO_OVERFLOW:
136 return 0;
137
138 case PIPE_CAP_TEXTURE_SWIZZLE:
139 return 1;
140
141 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
142 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
143 return 1;
144
145 case PIPE_CAP_TGSI_INSTANCEID:
146 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
147 case PIPE_CAP_PRIMITIVE_RESTART:
148 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
149 return 1;
150
151 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
152 return is_gles3 ? 4 : 0;
153 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
154 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
155 return is_gles3 ? 64 : 0;
156 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
157 return 1;
158
159 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
160 return 256;
161
162 case PIPE_CAP_GLSL_FEATURE_LEVEL:
163 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
164 return is_gl3 ? 330 : (is_gles3 ? 140 : 120);
165 case PIPE_CAP_ESSL_FEATURE_LEVEL:
166 return is_gles3 ? 300 : 120;
167
168 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
169 return 16;
170
171 case PIPE_CAP_TEXTURE_MULTISAMPLE:
172 return is_gles3;
173
174 /* For faking GLES 3.1 for dEQP-GLES31 */
175 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
176 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
177 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
178 case PIPE_CAP_CUBE_MAP_ARRAY:
179 return is_deqp;
180
181 /* For faking compute shaders */
182 case PIPE_CAP_COMPUTE:
183 return is_deqp;
184
185 case PIPE_CAP_QUERY_TIMESTAMP:
186 case PIPE_CAP_CONDITIONAL_RENDER:
187 return is_gl3;
188
189 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
190 return 4096;
191 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
192 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
193 return 13;
194
195 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
196 case PIPE_CAP_INDEP_BLEND_ENABLE:
197 case PIPE_CAP_INDEP_BLEND_FUNC:
198 return 1;
199
200 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
201 /* Hardware is natively upper left */
202 return 0;
203
204 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
205 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
206 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
207 case PIPE_CAP_GENERATE_MIPMAP:
208 return 1;
209
210 /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
211 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
212 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
213 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
214 return dev->quirks & IS_BIFROST;
215
216 /* I really don't want to set this CAP but let's not swim against the
217 * tide.. */
218 case PIPE_CAP_TGSI_TEXCOORD:
219 return 1;
220
221 case PIPE_CAP_SEAMLESS_CUBE_MAP:
222 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
223 return 1;
224
225 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
226 return 0xffff;
227
228 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
229 return 1;
230
231 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
232 return 65536;
233
234 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
235 return 0;
236
237 case PIPE_CAP_ENDIANNESS:
238 return PIPE_ENDIAN_NATIVE;
239
240 case PIPE_CAP_SAMPLER_VIEW_TARGET:
241 return 1;
242
243 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
244 return -8;
245
246 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
247 return 7;
248
249 case PIPE_CAP_VENDOR_ID:
250 case PIPE_CAP_DEVICE_ID:
251 return 0xFFFFFFFF;
252
253 case PIPE_CAP_ACCELERATED:
254 case PIPE_CAP_UMA:
255 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
256 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
257 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
258 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
259 return 1;
260
261 case PIPE_CAP_VIDEO_MEMORY: {
262 uint64_t system_memory;
263
264 if (!os_get_total_physical_memory(&system_memory))
265 return 0;
266
267 return (int)(system_memory >> 20);
268 }
269
270 case PIPE_CAP_SHADER_STENCIL_EXPORT:
271 return 1;
272
273 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
274 return 4;
275
276 case PIPE_CAP_MAX_VARYINGS:
277 return 16;
278
279 case PIPE_CAP_ALPHA_TEST:
280 case PIPE_CAP_FLATSHADE:
281 case PIPE_CAP_TWO_SIDED_COLOR:
282 case PIPE_CAP_CLIP_PLANES:
283 return 0;
284
285 case PIPE_CAP_PACKED_STREAM_OUTPUT:
286 return 0;
287
288 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
289 case PIPE_CAP_PSIZ_CLAMPED:
290 return 1;
291
292 default:
293 return u_pipe_screen_get_param_defaults(screen, param);
294 }
295 }
296
297 static int
298 panfrost_get_shader_param(struct pipe_screen *screen,
299 enum pipe_shader_type shader,
300 enum pipe_shader_cap param)
301 {
302 bool is_deqp = pan_debug & PAN_DBG_DEQP;
303 bool is_fp16 = pan_debug & PAN_DBG_FP16;
304 struct panfrost_device *dev = pan_device(screen);
305
306 if (shader != PIPE_SHADER_VERTEX &&
307 shader != PIPE_SHADER_FRAGMENT &&
308 !(shader == PIPE_SHADER_COMPUTE && is_deqp))
309 return 0;
310
311 /* this is probably not totally correct.. but it's a start: */
312 switch (param) {
313 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
314 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
315 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
316 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
317 return 16384;
318
319 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
320 return 1024;
321
322 case PIPE_SHADER_CAP_MAX_INPUTS:
323 return 16;
324
325 case PIPE_SHADER_CAP_MAX_OUTPUTS:
326 return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
327
328 case PIPE_SHADER_CAP_MAX_TEMPS:
329 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
330
331 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
332 return 16 * 1024 * sizeof(float);
333
334 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
335 return PAN_MAX_CONST_BUFFERS;
336
337 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
338 return 0;
339
340 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
341 return 1;
342 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
343 return 0;
344
345 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
346 return 0;
347
348 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
349 return 1;
350
351 case PIPE_SHADER_CAP_SUBROUTINES:
352 return 0;
353
354 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
355 return 0;
356
357 case PIPE_SHADER_CAP_INTEGERS:
358 return 1;
359
360 case PIPE_SHADER_CAP_FP16:
361 return !(dev->quirks & MIDGARD_BROKEN_FP16) || is_fp16;
362
363 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
364 case PIPE_SHADER_CAP_INT16:
365 case PIPE_SHADER_CAP_INT64_ATOMICS:
366 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
367 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
368 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
369 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
370 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
371 return 0;
372
373 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
374 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
375 return 16; /* XXX: How many? */
376
377 case PIPE_SHADER_CAP_PREFERRED_IR:
378 return PIPE_SHADER_IR_NIR;
379
380 case PIPE_SHADER_CAP_SUPPORTED_IRS:
381 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
382
383 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
384 return 32;
385
386 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
387 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
388 return is_deqp ? 8 : 0;
389 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
390 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
391 return 0;
392
393 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
394 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
395 return 0;
396
397 default:
398 DBG("unknown shader param %d\n", param);
399 return 0;
400 }
401
402 return 0;
403 }
404
405 static float
406 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
407 {
408 switch (param) {
409 case PIPE_CAPF_MAX_LINE_WIDTH:
410
411 /* fall-through */
412 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
413 return 255.0; /* arbitrary */
414
415 case PIPE_CAPF_MAX_POINT_WIDTH:
416
417 /* fall-through */
418 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
419 return 1024.0;
420
421 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
422 return 16.0;
423
424 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
425 return 16.0; /* arbitrary */
426
427 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
428 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
429 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
430 return 0.0f;
431
432 default:
433 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
434 return 0.0;
435 }
436 }
437
438 /**
439 * Query format support for creating a texture, drawing surface, etc.
440 * \param format the format to test
441 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
442 */
443 static bool
444 panfrost_is_format_supported( struct pipe_screen *screen,
445 enum pipe_format format,
446 enum pipe_texture_target target,
447 unsigned sample_count,
448 unsigned storage_sample_count,
449 unsigned bind)
450 {
451 const struct util_format_description *format_desc;
452
453 assert(target == PIPE_BUFFER ||
454 target == PIPE_TEXTURE_1D ||
455 target == PIPE_TEXTURE_1D_ARRAY ||
456 target == PIPE_TEXTURE_2D ||
457 target == PIPE_TEXTURE_2D_ARRAY ||
458 target == PIPE_TEXTURE_RECT ||
459 target == PIPE_TEXTURE_3D ||
460 target == PIPE_TEXTURE_CUBE ||
461 target == PIPE_TEXTURE_CUBE_ARRAY);
462
463 format_desc = util_format_description(format);
464
465 if (!format_desc)
466 return false;
467
468 /* MSAA 4x supported, but no more. Technically some revisions of the
469 * hardware can go up to 16x but we don't support higher modes yet.
470 * MSAA 2x is notably not supported and gets rounded up to MSAA 4x. */
471
472 if (sample_count > 1 && !(pan_debug & (PAN_DBG_GL3 | PAN_DBG_DEQP)))
473 return false;
474
475 if (!(sample_count == 0 || sample_count == 1 || sample_count == 4))
476 return false;
477
478 if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
479 return false;
480
481 /* Don't confuse poorly written apps (workaround dEQP bug) that expect
482 * more alpha than they ask for */
483
484 bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
485 bool renderable = bind & PIPE_BIND_RENDER_TARGET;
486
487 if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
488 return false;
489
490 if (pan_debug & (PAN_DBG_GL3 | PAN_DBG_DEQP)) {
491 if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC)
492 return true;
493 }
494
495 /* Check we support the format with the given bind */
496
497 unsigned relevant_bind = bind &
498 ( PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET
499 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_SAMPLER_VIEW);
500
501 struct panfrost_format fmt = panfrost_pipe_format_table[format];
502 return fmt.hw && ((relevant_bind & ~fmt.bind) == 0);
503 }
504
505 static int
506 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
507 enum pipe_compute_cap param, void *ret)
508 {
509 const char * const ir = "panfrost";
510
511 if (!(pan_debug & PAN_DBG_DEQP))
512 return 0;
513
514 #define RET(x) do { \
515 if (ret) \
516 memcpy(ret, x, sizeof(x)); \
517 return sizeof(x); \
518 } while (0)
519
520 switch (param) {
521 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
522 RET((uint32_t []){ 64 });
523
524 case PIPE_COMPUTE_CAP_IR_TARGET:
525 if (ret)
526 sprintf(ret, "%s", ir);
527 return strlen(ir) * sizeof(char);
528
529 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
530 RET((uint64_t []) { 3 });
531
532 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
533 RET(((uint64_t []) { 65535, 65535, 65535 }));
534
535 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
536 RET(((uint64_t []) { 1024, 1024, 64 }));
537
538 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
539 RET((uint64_t []) { 1024 });
540
541 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
542 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
543
544 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
545 RET((uint64_t []) { 32768 });
546
547 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
548 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
549 RET((uint64_t []) { 4096 });
550
551 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
552 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
553
554 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
555 RET((uint32_t []) { 800 /* MHz -- TODO */ });
556
557 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
558 RET((uint32_t []) { 9999 }); // TODO
559
560 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
561 RET((uint32_t []) { 1 }); // TODO
562
563 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
564 RET((uint32_t []) { 32 }); // TODO
565
566 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
567 RET((uint64_t []) { 1024 }); // TODO
568 }
569
570 return 0;
571 }
572
573 static void
574 panfrost_destroy_screen(struct pipe_screen *pscreen)
575 {
576 panfrost_close_device(pan_device(pscreen));
577 ralloc_free(pscreen);
578 }
579
580 static uint64_t
581 panfrost_get_timestamp(struct pipe_screen *_screen)
582 {
583 return os_time_get_nano();
584 }
585
586 static void
587 panfrost_fence_reference(struct pipe_screen *pscreen,
588 struct pipe_fence_handle **ptr,
589 struct pipe_fence_handle *fence)
590 {
591 struct panfrost_fence **p = (struct panfrost_fence **)ptr;
592 struct panfrost_fence *f = (struct panfrost_fence *)fence;
593 struct panfrost_fence *old = *p;
594
595 if (pipe_reference(&(*p)->reference, &f->reference)) {
596 util_dynarray_foreach(&old->syncfds, int, fd)
597 close(*fd);
598 util_dynarray_fini(&old->syncfds);
599 free(old);
600 }
601 *p = f;
602 }
603
604 static bool
605 panfrost_fence_finish(struct pipe_screen *pscreen,
606 struct pipe_context *ctx,
607 struct pipe_fence_handle *fence,
608 uint64_t timeout)
609 {
610 struct panfrost_device *dev = pan_device(pscreen);
611 struct panfrost_fence *f = (struct panfrost_fence *)fence;
612 struct util_dynarray syncobjs;
613 int ret;
614
615 /* All fences were already signaled */
616 if (!util_dynarray_num_elements(&f->syncfds, int))
617 return true;
618
619 util_dynarray_init(&syncobjs, NULL);
620 util_dynarray_foreach(&f->syncfds, int, fd) {
621 uint32_t syncobj;
622
623 ret = drmSyncobjCreate(dev->fd, 0, &syncobj);
624 assert(!ret);
625
626 ret = drmSyncobjImportSyncFile(dev->fd, syncobj, *fd);
627 assert(!ret);
628 util_dynarray_append(&syncobjs, uint32_t, syncobj);
629 }
630
631 uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
632 if (abs_timeout == OS_TIMEOUT_INFINITE)
633 abs_timeout = INT64_MAX;
634
635 ret = drmSyncobjWait(dev->fd, util_dynarray_begin(&syncobjs),
636 util_dynarray_num_elements(&syncobjs, uint32_t),
637 abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
638 NULL);
639
640 util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
641 drmSyncobjDestroy(dev->fd, *syncobj);
642
643 return ret >= 0;
644 }
645
646 struct panfrost_fence *
647 panfrost_fence_create(struct panfrost_context *ctx,
648 struct util_dynarray *fences)
649 {
650 struct panfrost_device *device = pan_device(ctx->base.screen);
651 struct panfrost_fence *f = calloc(1, sizeof(*f));
652 if (!f)
653 return NULL;
654
655 util_dynarray_init(&f->syncfds, NULL);
656
657 /* Export fences from all pending batches. */
658 util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
659 int fd = -1;
660
661 /* The fence is already signaled, no need to export it. */
662 if ((*fence)->signaled)
663 continue;
664
665 drmSyncobjExportSyncFile(device->fd, (*fence)->syncobj, &fd);
666 if (fd == -1)
667 fprintf(stderr, "export failed: %m\n");
668
669 assert(fd != -1);
670 util_dynarray_append(&f->syncfds, int, fd);
671 }
672
673 pipe_reference_init(&f->reference, 1);
674
675 return f;
676 }
677
678 static const void *
679 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
680 enum pipe_shader_ir ir,
681 enum pipe_shader_type shader)
682 {
683 if (pan_device(pscreen)->quirks & IS_BIFROST)
684 return &bifrost_nir_options;
685 else
686 return &midgard_nir_options;
687 }
688
689 struct pipe_screen *
690 panfrost_create_screen(int fd, struct renderonly *ro)
691 {
692 pan_debug = debug_get_option_pan_debug();
693
694 /* Blacklist apps known to be buggy under Panfrost */
695 const char *proc = util_get_process_name();
696 const char *blacklist[] = {
697 "chromium",
698 "chrome",
699 };
700
701 for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
702 if ((strcmp(blacklist[i], proc) == 0))
703 return NULL;
704 }
705
706 /* Create the screen */
707 struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
708
709 if (!screen)
710 return NULL;
711
712 struct panfrost_device *dev = pan_device(&screen->base);
713 panfrost_open_device(screen, fd, dev);
714
715 if (ro) {
716 dev->ro = renderonly_dup(ro);
717 if (!dev->ro) {
718 DBG("Failed to dup renderonly object\n");
719 free(screen);
720 return NULL;
721 }
722 }
723
724 /* Check if we're loading against a supported GPU model. */
725
726 switch (dev->gpu_id) {
727 case 0x720: /* T720 */
728 case 0x750: /* T760 */
729 case 0x820: /* T820 */
730 case 0x860: /* T860 */
731 break;
732 case 0x7093: /* G31 */
733 case 0x7212: /* G52 */
734 if (pan_debug & PAN_DBG_BIFROST)
735 break;
736
737 /* fallthrough */
738 default:
739 /* Fail to load against untested models */
740 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
741 panfrost_destroy_screen(&(screen->base));
742 return NULL;
743 }
744
745 if (pan_debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
746 pandecode_initialize(!(pan_debug & PAN_DBG_TRACE));
747
748 screen->base.destroy = panfrost_destroy_screen;
749
750 screen->base.get_name = panfrost_get_name;
751 screen->base.get_vendor = panfrost_get_vendor;
752 screen->base.get_device_vendor = panfrost_get_device_vendor;
753 screen->base.get_param = panfrost_get_param;
754 screen->base.get_shader_param = panfrost_get_shader_param;
755 screen->base.get_compute_param = panfrost_get_compute_param;
756 screen->base.get_paramf = panfrost_get_paramf;
757 screen->base.get_timestamp = panfrost_get_timestamp;
758 screen->base.is_format_supported = panfrost_is_format_supported;
759 screen->base.context_create = panfrost_create_context;
760 screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
761 screen->base.fence_reference = panfrost_fence_reference;
762 screen->base.fence_finish = panfrost_fence_finish;
763 screen->base.set_damage_region = panfrost_resource_set_damage_region;
764
765 panfrost_resource_screen_init(&screen->base);
766
767 return &screen->base;
768 }