src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "bifrost/bifrost_compile.h"
  56 #include "panfrost-quirks.h"
  57
  58 static const struct debug_named_value debug_options[] = {
  59         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  60         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  61         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  62         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  63         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  64         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  65         {"nofp16",     PAN_DBG_NOFP16,     "Disable 16-bit support"},
  66         {"bifrost",   PAN_DBG_BIFROST, "Enable experimental Mali G31 and G52 support"},
  67         {"gl3",       PAN_DBG_GL3,      "Enable experimental GL 3.x implementation, up to 3.3"},
  68         DEBUG_NAMED_VALUE_END
  69 };
  70
  71 static const char *
  72 panfrost_get_name(struct pipe_screen *screen)
  73 {
  74         return panfrost_model_name(pan_device(screen)->gpu_id);
  75 }
  76
  77 static const char *
  78 panfrost_get_vendor(struct pipe_screen *screen)
  79 {
  80         return "Panfrost";
  81 }
  82
  83 static const char *
  84 panfrost_get_device_vendor(struct pipe_screen *screen)
  85 {
  86         return "Arm";
  87 }
  88
  89 static int
  90 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  91 {
  92         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  93         struct panfrost_device *dev = pan_device(screen);
  94         bool is_deqp = dev->debug & PAN_DBG_DEQP;
  95
  96         /* Our GL 3.x implementation is WIP */
  97         bool is_gl3 = dev->debug & PAN_DBG_GL3;
  98         is_gl3 |= is_deqp;
  99
 100         /* Don't expose MRT related CAPs on GPUs that don't implement them */
 101         bool has_mrt = !(dev->quirks & MIDGARD_SFBD);
 102
 103         /* Bifrost is WIP. No MRT support yet. */
 104         bool is_bifrost = (dev->quirks & IS_BIFROST);
 105         has_mrt &= !is_bifrost;
 106
 107         switch (param) {
 108         case PIPE_CAP_NPOT_TEXTURES:
 109         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 110         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 111         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 112         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 113         case PIPE_CAP_POINT_SPRITE:
 114         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 115         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 116         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 117         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 118                 return 1;
 119
 120         case PIPE_CAP_MAX_RENDER_TARGETS:
 121         case PIPE_CAP_FBFETCH:
 122         case PIPE_CAP_FBFETCH_COHERENT:
 123                 return has_mrt ? 8 : 1;
 124
 125         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 126                 return 1;
 127
 128         case PIPE_CAP_SAMPLE_SHADING:
 129                 /* WIP */
 130                 return is_gl3 ? 1 : 0;
 131
 132
 133         /* ES3 features unsupported on Bifrost */
 134         case PIPE_CAP_OCCLUSION_QUERY:
 135         case PIPE_CAP_TGSI_INSTANCEID:
 136         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 137         case PIPE_CAP_PRIMITIVE_RESTART:
 138         case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
 139                 return !is_bifrost;
 140
 141         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 142         case PIPE_CAP_TEXTURE_SWIZZLE:
 143         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 144         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 145         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 146         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 147         case PIPE_CAP_INDEP_BLEND_ENABLE:
 148         case PIPE_CAP_INDEP_BLEND_FUNC:
 149         case PIPE_CAP_GENERATE_MIPMAP:
 150         case PIPE_CAP_ACCELERATED:
 151         case PIPE_CAP_UMA:
 152         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 153         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 154         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 155         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 156                 return 1;
 157
 158         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 159                 return is_bifrost ? 0 : 4;
 160         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 161         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 162                 return is_bifrost ? 0 : 64;
 163         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 164                 return is_bifrost ? 0 : 1;
 165
 166         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 167                 return is_bifrost ? 0 : 256;
 168
 169         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 170         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 171                 return is_gl3 ? 330 : (is_bifrost ? 120 : 140);
 172         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 173                 return is_bifrost ? 120 : 300;
 174
 175         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 176                 return 16;
 177
 178         /* For faking GLES 3.1 for dEQP-GLES31 */
 179         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 180         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 181         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 182         case PIPE_CAP_CUBE_MAP_ARRAY:
 183         case PIPE_CAP_COMPUTE:
 184                 return is_deqp;
 185         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 186                 return is_deqp ? 65536 : 0;
 187
 188         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 189         case PIPE_CAP_QUERY_TIMESTAMP:
 190         case PIPE_CAP_CONDITIONAL_RENDER:
 191                 return is_gl3;
 192
 193         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 194                 return 4096;
 195         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 196                 return is_bifrost ? 0 : 13;
 197         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 198                 return 13;
 199
 200         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 201                 /* Hardware is natively upper left */
 202                 return 0;
 203
 204         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 205         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 206         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 207         case PIPE_CAP_TGSI_TEXCOORD:
 208                 return 1;
 209
 210         /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
 211         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 212         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 213         case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 214                 return is_bifrost;
 215
 216         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 217         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 218                 return !is_bifrost;
 219
 220         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 221                 return 0xffff;
 222
 223         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 224                 return 0;
 225
 226         case PIPE_CAP_ENDIANNESS:
 227                 return PIPE_ENDIAN_NATIVE;
 228
 229                 return 1;
 230
 231         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 232                 return -8;
 233
 234         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 235                 return 7;
 236
 237         case PIPE_CAP_VIDEO_MEMORY: {
 238                 uint64_t system_memory;
 239
 240                 if (!os_get_total_physical_memory(&system_memory))
 241                         return 0;
 242
 243                 return (int)(system_memory >> 20);
 244         }
 245
 246         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 247                 return !is_bifrost;
 248
 249         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 250                 return 4;
 251
 252         case PIPE_CAP_MAX_VARYINGS:
 253                 return 16;
 254
 255         case PIPE_CAP_ALPHA_TEST:
 256         case PIPE_CAP_FLATSHADE:
 257         case PIPE_CAP_TWO_SIDED_COLOR:
 258         case PIPE_CAP_CLIP_PLANES:
 259                 return 0;
 260
 261         case PIPE_CAP_PACKED_STREAM_OUTPUT:
 262                 return 0;
 263
 264         case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
 265         case PIPE_CAP_PSIZ_CLAMPED:
 266                 return 1;
 267
 268         default:
 269                 return u_pipe_screen_get_param_defaults(screen, param);
 270         }
 271 }
 272
 273 static int
 274 panfrost_get_shader_param(struct pipe_screen *screen,
 275                           enum pipe_shader_type shader,
 276                           enum pipe_shader_cap param)
 277 {
 278         struct panfrost_device *dev = pan_device(screen);
 279         bool is_deqp = dev->debug & PAN_DBG_DEQP;
 280         bool is_nofp16 = dev->debug & PAN_DBG_NOFP16;
 281         bool is_bifrost = dev->quirks & IS_BIFROST;
 282
 283         if (shader != PIPE_SHADER_VERTEX &&
 284             shader != PIPE_SHADER_FRAGMENT &&
 285             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 286                 return 0;
 287
 288         /* this is probably not totally correct.. but it's a start: */
 289         switch (param) {
 290         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 291         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 292         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 293         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 294                 return 16384;
 295
 296         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 297                 return 1024;
 298
 299         case PIPE_SHADER_CAP_MAX_INPUTS:
 300                 return 16;
 301
 302         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 303                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 16;
 304
 305         case PIPE_SHADER_CAP_MAX_TEMPS:
 306                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 307
 308         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 309                 return 16 * 1024 * sizeof(float);
 310
 311         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 312                 return PAN_MAX_CONST_BUFFERS;
 313
 314         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 315                 return 0;
 316
 317         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 318                 return is_bifrost ? 0 : 1;
 319         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 320                 return 0;
 321
 322         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 323                 return 0;
 324
 325         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 326                 return is_bifrost ? 0 : 1;
 327
 328         case PIPE_SHADER_CAP_SUBROUTINES:
 329                 return 0;
 330
 331         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 332                 return 0;
 333
 334         case PIPE_SHADER_CAP_INTEGERS:
 335                 return 1;
 336
 337         case PIPE_SHADER_CAP_FP16:
 338         case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS:
 339                 return !is_nofp16;
 340
 341         case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 342         case PIPE_SHADER_CAP_INT16:
 343         case PIPE_SHADER_CAP_INT64_ATOMICS:
 344         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 345         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 346         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 347         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 348         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 349                 return 0;
 350
 351         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 352         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 353                 return 16; /* XXX: How many? */
 354
 355         case PIPE_SHADER_CAP_PREFERRED_IR:
 356                 return PIPE_SHADER_IR_NIR;
 357
 358         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 359                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 360
 361         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 362                 return 32;
 363
 364         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 365         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 366                 return is_deqp ? 8 : 0;
 367         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 368         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 369                 return 0;
 370
 371         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 372         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 373                 return 0;
 374
 375         default:
 376                 /* Other params are unknown */
 377                 return 0;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static float
 384 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 385 {
 386         switch (param) {
 387         case PIPE_CAPF_MAX_LINE_WIDTH:
 388
 389         /* fall-through */
 390         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 391                 return 255.0; /* arbitrary */
 392
 393         case PIPE_CAPF_MAX_POINT_WIDTH:
 394
 395         /* fall-through */
 396         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 397                 return 1024.0;
 398
 399         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 400                 return 16.0;
 401
 402         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 403                 return 16.0; /* arbitrary */
 404
 405         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 406         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 407         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 408                 return 0.0f;
 409
 410         default:
 411                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 412                 return 0.0;
 413         }
 414 }
 415
 416 /**
 417  * Query format support for creating a texture, drawing surface, etc.
 418  * \param format  the format to test
 419  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 420  */
 421 static bool
 422 panfrost_is_format_supported( struct pipe_screen *screen,
 423                               enum pipe_format format,
 424                               enum pipe_texture_target target,
 425                               unsigned sample_count,
 426                               unsigned storage_sample_count,
 427                               unsigned bind)
 428 {
 429         struct panfrost_device *dev = pan_device(screen);
 430         const struct util_format_description *format_desc;
 431
 432         assert(target == PIPE_BUFFER ||
 433                target == PIPE_TEXTURE_1D ||
 434                target == PIPE_TEXTURE_1D_ARRAY ||
 435                target == PIPE_TEXTURE_2D ||
 436                target == PIPE_TEXTURE_2D_ARRAY ||
 437                target == PIPE_TEXTURE_RECT ||
 438                target == PIPE_TEXTURE_3D ||
 439                target == PIPE_TEXTURE_CUBE ||
 440                target == PIPE_TEXTURE_CUBE_ARRAY);
 441
 442         format_desc = util_format_description(format);
 443
 444         if (!format_desc)
 445                 return false;
 446
 447         /* MSAA 4x supported, but no more. Technically some revisions of the
 448          * hardware can go up to 16x but we don't support higher modes yet.
 449          * MSAA 2x is notably not supported and gets rounded up to MSAA 4x. */
 450
 451         if (!(sample_count == 0 || sample_count == 1 || sample_count == 4))
 452                 return false;
 453
 454         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 455                 return false;
 456
 457         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 458          * more alpha than they ask for */
 459
 460         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 461         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 462
 463         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 464                 return false;
 465
 466         /* Check we support the format with the given bind */
 467
 468         unsigned relevant_bind = bind &
 469                 ( PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET
 470                 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_SAMPLER_VIEW);
 471
 472         struct panfrost_format fmt = panfrost_pipe_format_table[format];
 473
 474         /* Also check that compressed texture formats are supported on this
 475          * particular chip. They may not be depending on system integration
 476          * differences. RGTC can be emulated so is always supported. */
 477
 478         bool is_rgtc = format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC;
 479         bool supported = panfrost_supports_compressed_format(dev, fmt.hw);
 480
 481         if (!is_rgtc && !supported)
 482                 return false;
 483
 484         return fmt.hw && ((relevant_bind & ~fmt.bind) == 0);
 485 }
 486
 487 static int
 488 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 489                 enum pipe_compute_cap param, void *ret)
 490 {
 491         struct panfrost_device *dev = pan_device(pscreen);
 492         const char * const ir = "panfrost";
 493
 494         if (!(dev->debug & PAN_DBG_DEQP))
 495                 return 0;
 496
 497 #define RET(x) do {                  \
 498    if (ret)                          \
 499       memcpy(ret, x, sizeof(x));     \
 500    return sizeof(x);                 \
 501 } while (0)
 502
 503         switch (param) {
 504         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 505                 RET((uint32_t []){ 64 });
 506
 507         case PIPE_COMPUTE_CAP_IR_TARGET:
 508                 if (ret)
 509                         sprintf(ret, "%s", ir);
 510                 return strlen(ir) * sizeof(char);
 511
 512         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 513                 RET((uint64_t []) { 3 });
 514
 515         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 516                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 517
 518         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 519                 RET(((uint64_t []) { 1024, 1024, 64 }));
 520
 521         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 522                 RET((uint64_t []) { 1024 });
 523
 524         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 525                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 526
 527         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 528                 RET((uint64_t []) { 32768 });
 529
 530         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 531         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 532                 RET((uint64_t []) { 4096 });
 533
 534         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 535                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 536
 537         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 538                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 539
 540         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 541                 RET((uint32_t []) { 9999 });  // TODO
 542
 543         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 544                 RET((uint32_t []) { 1 }); // TODO
 545
 546         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 547                 RET((uint32_t []) { 32 });  // TODO
 548
 549         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 550                 RET((uint64_t []) { 1024 }); // TODO
 551         }
 552
 553         return 0;
 554 }
 555
 556 static void
 557 panfrost_destroy_screen(struct pipe_screen *pscreen)
 558 {
 559         panfrost_close_device(pan_device(pscreen));
 560         ralloc_free(pscreen);
 561 }
 562
 563 static uint64_t
 564 panfrost_get_timestamp(struct pipe_screen *_screen)
 565 {
 566         return os_time_get_nano();
 567 }
 568
 569 static void
 570 panfrost_fence_reference(struct pipe_screen *pscreen,
 571                          struct pipe_fence_handle **ptr,
 572                          struct pipe_fence_handle *fence)
 573 {
 574         struct panfrost_device *dev = pan_device(pscreen);
 575         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 576         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 577         struct panfrost_fence *old = *p;
 578
 579         if (pipe_reference(&(*p)->reference, &f->reference)) {
 580                 drmSyncobjDestroy(dev->fd, old->syncobj);
 581                 free(old);
 582         }
 583         *p = f;
 584 }
 585
 586 static bool
 587 panfrost_fence_finish(struct pipe_screen *pscreen,
 588                       struct pipe_context *ctx,
 589                       struct pipe_fence_handle *fence,
 590                       uint64_t timeout)
 591 {
 592         struct panfrost_device *dev = pan_device(pscreen);
 593         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 594         int ret;
 595
 596         if (f->signaled)
 597                 return true;
 598
 599         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 600         if (abs_timeout == OS_TIMEOUT_INFINITE)
 601                 abs_timeout = INT64_MAX;
 602
 603         ret = drmSyncobjWait(dev->fd, &f->syncobj,
 604                              1,
 605                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 606                              NULL);
 607
 608         f->signaled = (ret >= 0);
 609         return f->signaled;
 610 }
 611
 612 struct panfrost_fence *
 613 panfrost_fence_create(struct panfrost_context *ctx,
 614                       uint32_t syncobj)
 615 {
 616         struct panfrost_fence *f = calloc(1, sizeof(*f));
 617         if (!f)
 618                 return NULL;
 619
 620         pipe_reference_init(&f->reference, 1);
 621         f->syncobj = syncobj;
 622
 623         return f;
 624 }
 625
 626 static const void *
 627 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 628                                      enum pipe_shader_ir ir,
 629                                      enum pipe_shader_type shader)
 630 {
 631         if (pan_device(pscreen)->quirks & IS_BIFROST)
 632                 return &bifrost_nir_options;
 633         else
 634                 return &midgard_nir_options;
 635 }
 636
 637 struct pipe_screen *
 638 panfrost_create_screen(int fd, struct renderonly *ro)
 639 {
 640         /* Create the screen */
 641         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 642
 643         if (!screen)
 644                 return NULL;
 645
 646         struct panfrost_device *dev = pan_device(&screen->base);
 647         panfrost_open_device(screen, fd, dev);
 648
 649         dev->debug = debug_get_flags_option("PAN_MESA_DEBUG", debug_options, 0);
 650
 651         if (ro) {
 652                 dev->ro = renderonly_dup(ro);
 653                 if (!dev->ro) {
 654                         if (dev->debug & PAN_DBG_MSGS)
 655                                 fprintf(stderr, "Failed to dup renderonly object\n");
 656
 657                         free(screen);
 658                         return NULL;
 659                 }
 660         }
 661
 662         /* Check if we're loading against a supported GPU model. */
 663
 664         switch (dev->gpu_id) {
 665         case 0x720: /* T720 */
 666         case 0x750: /* T760 */
 667         case 0x820: /* T820 */
 668         case 0x860: /* T860 */
 669                 break;
 670         case 0x7093: /* G31 */
 671         case 0x7212: /* G52 */
 672                 if (dev->debug & PAN_DBG_BIFROST)
 673                         break;
 674
 675                 /* fallthrough */
 676         default:
 677                 /* Fail to load against untested models */
 678                 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
 679                 panfrost_destroy_screen(&(screen->base));
 680                 return NULL;
 681         }
 682
 683         if (dev->debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 684                 pandecode_initialize(!(dev->debug & PAN_DBG_TRACE));
 685
 686         screen->base.destroy = panfrost_destroy_screen;
 687
 688         screen->base.get_name = panfrost_get_name;
 689         screen->base.get_vendor = panfrost_get_vendor;
 690         screen->base.get_device_vendor = panfrost_get_device_vendor;
 691         screen->base.get_param = panfrost_get_param;
 692         screen->base.get_shader_param = panfrost_get_shader_param;
 693         screen->base.get_compute_param = panfrost_get_compute_param;
 694         screen->base.get_paramf = panfrost_get_paramf;
 695         screen->base.get_timestamp = panfrost_get_timestamp;
 696         screen->base.is_format_supported = panfrost_is_format_supported;
 697         screen->base.context_create = panfrost_create_context;
 698         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 699         screen->base.fence_reference = panfrost_fence_reference;
 700         screen->base.fence_finish = panfrost_fence_finish;
 701         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 702
 703         panfrost_resource_screen_init(&screen->base);
 704
 705         if (!(dev->quirks & IS_BIFROST))
 706                 panfrost_init_blit_shaders(dev);
 707
 708         return &screen->base;
 709 }