2 * Copyright (C) 2008 VMware, Inc.
3 * Copyright (C) 2014 Broadcom
4 * Copyright (C) 2018 Alyssa Rosenzweig
5 * Copyright (C) 2019 Collabora, Ltd.
6 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 #include "util/u_debug.h"
30 #include "util/u_memory.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_video.h"
34 #include "util/u_screen.h"
35 #include "util/os_time.h"
36 #include "util/u_process.h"
37 #include "pipe/p_defines.h"
38 #include "pipe/p_screen.h"
39 #include "draw/draw_context.h"
43 #include "drm-uapi/drm_fourcc.h"
45 #include "pan_screen.h"
46 #include "pan_resource.h"
47 #include "pan_public.h"
49 #include "pandecode/decode.h"
51 #include "pan_context.h"
52 #include "midgard/midgard_compile.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", PAN_DBG_MSGS
, "Print debug messages"},
56 {"trace", PAN_DBG_TRACE
, "Trace the command stream"},
57 {"deqp", PAN_DBG_DEQP
, "Hacks for dEQP"},
58 {"afbc", PAN_DBG_AFBC
, "Enable non-conformant AFBC impl"},
62 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug
, "PAN_MESA_DEBUG", debug_options
, 0)
67 panfrost_get_name(struct pipe_screen
*screen
)
73 panfrost_get_vendor(struct pipe_screen
*screen
)
79 panfrost_get_device_vendor(struct pipe_screen
*screen
)
85 panfrost_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
87 /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
88 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
91 case PIPE_CAP_NPOT_TEXTURES
:
92 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
93 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
94 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
95 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
96 case PIPE_CAP_POINT_SPRITE
:
99 case PIPE_CAP_MAX_RENDER_TARGETS
:
100 return is_deqp
? 4 : 1;
103 case PIPE_CAP_OCCLUSION_QUERY
:
105 case PIPE_CAP_QUERY_TIME_ELAPSED
:
106 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
107 case PIPE_CAP_QUERY_TIMESTAMP
:
108 case PIPE_CAP_QUERY_SO_OVERFLOW
:
111 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
112 case PIPE_CAP_TEXTURE_SWIZZLE
:
115 case PIPE_CAP_TGSI_INSTANCEID
:
116 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
117 return is_deqp
? 1 : 0;
119 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
120 return is_deqp
? 4 : 0;
121 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
122 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
123 return is_deqp
? 64 : 0;
124 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
127 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
128 return is_deqp
? 256 : 0; /* for GL3 */
130 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
131 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
132 return is_deqp
? 140 : 120;
133 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
134 return is_deqp
? 300 : 120;
136 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
137 return is_deqp
? 16 : 0;
139 case PIPE_CAP_CUBE_MAP_ARRAY
:
142 /* For faking GLES 3.1 for dEQP-GLES31 */
143 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
144 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
:
145 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
:
146 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
149 /* For faking compute shaders */
150 case PIPE_CAP_COMPUTE
:
153 /* TODO: Where does this req come from in practice? */
154 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
157 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
159 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
160 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
163 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
164 case PIPE_CAP_INDEP_BLEND_ENABLE
:
165 case PIPE_CAP_INDEP_BLEND_FUNC
:
168 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
169 /* Hardware is natively upper left */
172 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
173 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
174 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
175 case PIPE_CAP_GENERATE_MIPMAP
:
178 /* We would prefer varyings */
179 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
180 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
183 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
184 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
187 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
:
190 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
193 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
196 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
199 case PIPE_CAP_ENDIANNESS
:
200 return PIPE_ENDIAN_NATIVE
;
202 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
205 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
208 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
211 case PIPE_CAP_VENDOR_ID
:
212 case PIPE_CAP_DEVICE_ID
:
215 case PIPE_CAP_ACCELERATED
:
217 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
218 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
219 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
220 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
223 case PIPE_CAP_VIDEO_MEMORY
: {
224 uint64_t system_memory
;
226 if (!os_get_total_physical_memory(&system_memory
))
229 return (int)(system_memory
>> 20);
232 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
235 case PIPE_CAP_MAX_VARYINGS
:
239 return u_pipe_screen_get_param_defaults(screen
, param
);
244 panfrost_get_shader_param(struct pipe_screen
*screen
,
245 enum pipe_shader_type shader
,
246 enum pipe_shader_cap param
)
248 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
250 if (shader
!= PIPE_SHADER_VERTEX
&&
251 shader
!= PIPE_SHADER_FRAGMENT
&&
252 !(shader
== PIPE_SHADER_COMPUTE
&& is_deqp
))
255 /* this is probably not totally correct.. but it's a start: */
257 case PIPE_SHADER_CAP_SCALAR_ISA
:
260 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
261 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
262 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
263 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
266 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
269 case PIPE_SHADER_CAP_MAX_INPUTS
:
272 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
273 return shader
== PIPE_SHADER_FRAGMENT
? 4 : 8;
275 case PIPE_SHADER_CAP_MAX_TEMPS
:
276 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
278 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
279 return 16 * 1024 * sizeof(float);
281 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
282 return PAN_MAX_CONST_BUFFERS
;
284 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
287 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
289 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
292 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
295 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
298 case PIPE_SHADER_CAP_SUBROUTINES
:
301 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
304 case PIPE_SHADER_CAP_INTEGERS
:
307 case PIPE_SHADER_CAP_INT64_ATOMICS
:
308 case PIPE_SHADER_CAP_FP16
:
309 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
310 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
311 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
312 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
313 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
316 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
317 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
318 return 16; /* XXX: How many? */
320 case PIPE_SHADER_CAP_PREFERRED_IR
:
321 return PIPE_SHADER_IR_NIR
;
323 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
324 return (1 << PIPE_SHADER_IR_NIR
);
326 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
329 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
330 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
331 return is_deqp
? 4 : 0;
332 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
333 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
336 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
337 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
341 fprintf(stderr
, "unknown shader param %d\n", param
);
349 panfrost_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
352 case PIPE_CAPF_MAX_LINE_WIDTH
:
355 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
356 return 255.0; /* arbitrary */
358 case PIPE_CAPF_MAX_POINT_WIDTH
:
361 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
364 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
367 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
368 return 16.0; /* arbitrary */
370 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
371 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
372 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
376 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
382 * Query format support for creating a texture, drawing surface, etc.
383 * \param format the format to test
384 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
387 panfrost_is_format_supported( struct pipe_screen
*screen
,
388 enum pipe_format format
,
389 enum pipe_texture_target target
,
390 unsigned sample_count
,
391 unsigned storage_sample_count
,
394 const struct util_format_description
*format_desc
;
396 assert(target
== PIPE_BUFFER
||
397 target
== PIPE_TEXTURE_1D
||
398 target
== PIPE_TEXTURE_1D_ARRAY
||
399 target
== PIPE_TEXTURE_2D
||
400 target
== PIPE_TEXTURE_2D_ARRAY
||
401 target
== PIPE_TEXTURE_RECT
||
402 target
== PIPE_TEXTURE_3D
||
403 target
== PIPE_TEXTURE_CUBE
||
404 target
== PIPE_TEXTURE_CUBE_ARRAY
);
406 format_desc
= util_format_description(format
);
411 if (sample_count
> 1)
414 /* Format wishlist */
415 if (format
== PIPE_FORMAT_X8Z24_UNORM
)
418 if (format
== PIPE_FORMAT_A1B5G5R5_UNORM
|| format
== PIPE_FORMAT_X1B5G5R5_UNORM
)
422 if (format
== PIPE_FORMAT_B5G5R5A1_UNORM
)
425 /* Don't confuse poorly written apps (workaround dEQP bug) that expect
426 * more alpha than they ask for */
428 bool scanout
= bind
& (PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
| PIPE_BIND_DISPLAY_TARGET
);
429 bool renderable
= bind
& PIPE_BIND_RENDER_TARGET
;
431 if (scanout
&& renderable
&& !util_format_is_rgba8_variant(format_desc
))
434 if (format_desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
&&
435 format_desc
->layout
!= UTIL_FORMAT_LAYOUT_OTHER
) {
436 /* Compressed formats not yet hooked up. */
440 /* Internally, formats that are depth/stencil renderable are limited.
442 * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
443 * rendering perspective. That is, we render to Z24S8 (which we can
444 * AFBC compress), ignore the different when texturing (who cares?),
445 * and then in the off-chance there's a CPU read we blit back to
448 * ...alternatively, we can make the state tracker deal with that. */
450 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
452 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
453 case PIPE_FORMAT_Z24X8_UNORM
:
454 case PIPE_FORMAT_Z32_UNORM
:
455 case PIPE_FORMAT_Z32_FLOAT
:
456 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
468 panfrost_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
469 enum pipe_compute_cap param
, void *ret
)
471 const char * const ir
= "panfrost";
473 if (!(pan_debug
& PAN_DBG_DEQP
))
476 #define RET(x) do { \
478 memcpy(ret, x, sizeof(x)); \
483 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
484 /* TODO: We'll want 64-bit pointers soon */
485 RET((uint32_t []){ 32 });
487 case PIPE_COMPUTE_CAP_IR_TARGET
:
489 sprintf(ret
, "%s", ir
);
490 return strlen(ir
) * sizeof(char);
492 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
493 RET((uint64_t []) { 3 });
495 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
496 RET(((uint64_t []) { 65535, 65535, 65535 }));
498 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
499 RET(((uint64_t []) { 1024, 1024, 64 }));
501 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
502 RET((uint64_t []) { 1024 });
504 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
505 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
507 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
508 RET((uint64_t []) { 32768 });
510 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
511 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
512 RET((uint64_t []) { 4096 });
514 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
515 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
517 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
518 RET((uint32_t []) { 800 /* MHz -- TODO */ });
520 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
521 RET((uint32_t []) { 9999 }); // TODO
523 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
524 RET((uint32_t []) { 1 }); // TODO
526 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
527 RET((uint32_t []) { 32 }); // TODO
529 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
530 RET((uint64_t []) { 1024 }); // TODO
537 panfrost_destroy_screen(struct pipe_screen
*pscreen
)
539 struct panfrost_screen
*screen
= pan_screen(pscreen
);
540 panfrost_bo_cache_evict_all(screen
);
541 drmFreeVersion(screen
->kernel_version
);
546 panfrost_flush_frontbuffer(struct pipe_screen
*_screen
,
547 struct pipe_resource
*resource
,
548 unsigned level
, unsigned layer
,
549 void *context_private
,
550 struct pipe_box
*sub_box
)
552 /* TODO: Display target integration */
556 panfrost_get_timestamp(struct pipe_screen
*_screen
)
558 return os_time_get_nano();
562 panfrost_fence_reference(struct pipe_screen
*pscreen
,
563 struct pipe_fence_handle
**ptr
,
564 struct pipe_fence_handle
*fence
)
566 panfrost_drm_fence_reference(pscreen
, ptr
, fence
);
570 panfrost_fence_finish(struct pipe_screen
*pscreen
,
571 struct pipe_context
*ctx
,
572 struct pipe_fence_handle
*fence
,
575 return panfrost_drm_fence_finish(pscreen
, ctx
, fence
, timeout
);
579 panfrost_screen_get_compiler_options(struct pipe_screen
*pscreen
,
580 enum pipe_shader_ir ir
,
581 enum pipe_shader_type shader
)
583 return &midgard_nir_options
;
587 panfrost_create_screen(int fd
, struct renderonly
*ro
)
589 pan_debug
= debug_get_option_pan_debug();
591 /* Blacklist apps known to be buggy under Panfrost */
592 const char *proc
= util_get_process_name();
593 const char *blacklist
[] = {
598 for (unsigned i
= 0; i
< ARRAY_SIZE(blacklist
); ++i
) {
599 if ((strcmp(blacklist
[i
], proc
) == 0))
603 /* Create the screen */
604 struct panfrost_screen
*screen
= rzalloc(NULL
, struct panfrost_screen
);
610 screen
->ro
= renderonly_dup(ro
);
612 fprintf(stderr
, "Failed to dup renderonly object\n");
620 screen
->gpu_id
= panfrost_drm_query_gpu_version(screen
);
621 screen
->require_sfbd
= screen
->gpu_id
< 0x0750; /* T760 is the first to support MFBD */
622 screen
->kernel_version
= drmGetVersion(fd
);
624 /* Check if we're loading against a supported GPU model. */
626 switch (screen
->gpu_id
) {
627 case 0x750: /* T760 */
628 case 0x820: /* T820 */
629 case 0x860: /* T860 */
632 /* Fail to load against untested models */
633 debug_printf("panfrost: Unsupported model %X",
638 util_dynarray_init(&screen
->transient_bo
, screen
);
640 for (unsigned i
= 0; i
< ARRAY_SIZE(screen
->bo_cache
); ++i
)
641 list_inithead(&screen
->bo_cache
[i
]);
643 if (pan_debug
& PAN_DBG_TRACE
)
644 pandecode_initialize();
646 screen
->base
.destroy
= panfrost_destroy_screen
;
648 screen
->base
.get_name
= panfrost_get_name
;
649 screen
->base
.get_vendor
= panfrost_get_vendor
;
650 screen
->base
.get_device_vendor
= panfrost_get_device_vendor
;
651 screen
->base
.get_param
= panfrost_get_param
;
652 screen
->base
.get_shader_param
= panfrost_get_shader_param
;
653 screen
->base
.get_compute_param
= panfrost_get_compute_param
;
654 screen
->base
.get_paramf
= panfrost_get_paramf
;
655 screen
->base
.get_timestamp
= panfrost_get_timestamp
;
656 screen
->base
.is_format_supported
= panfrost_is_format_supported
;
657 screen
->base
.context_create
= panfrost_create_context
;
658 screen
->base
.flush_frontbuffer
= panfrost_flush_frontbuffer
;
659 screen
->base
.get_compiler_options
= panfrost_screen_get_compiler_options
;
660 screen
->base
.fence_reference
= panfrost_fence_reference
;
661 screen
->base
.fence_finish
= panfrost_fence_finish
;
662 screen
->base
.set_damage_region
= panfrost_resource_set_damage_region
;
664 screen
->last_fragment_flushed
= true;
665 screen
->last_job
= NULL
;
667 panfrost_resource_screen_init(screen
);
669 return &screen
->base
;