src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "bifrost/bifrost_compile.h"
  56 #include "panfrost-quirks.h"
  57
  58 static const struct debug_named_value debug_options[] = {
  59         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  60         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  61         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  62         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  63         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  64         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  65         {"gles3",     PAN_DBG_GLES3,    "Enable experimental GLES3 implementation"},
  66         {"fp16",     PAN_DBG_FP16,     "Enable buggy experimental (don't use!) fp16"},
  67         {"bifrost",   PAN_DBG_BIFROST, "Enable experimental Mali G31 and G52 support"},
  68         {"gl3",       PAN_DBG_GL3,      "Enable experimental GL 3.x implementation, up to 3.3"},
  69         DEBUG_NAMED_VALUE_END
  70 };
  71
  72 static const char *
  73 panfrost_get_name(struct pipe_screen *screen)
  74 {
  75         return panfrost_model_name(pan_device(screen)->gpu_id);
  76 }
  77
  78 static const char *
  79 panfrost_get_vendor(struct pipe_screen *screen)
  80 {
  81         return "Panfrost";
  82 }
  83
  84 static const char *
  85 panfrost_get_device_vendor(struct pipe_screen *screen)
  86 {
  87         return "Arm";
  88 }
  89
  90 static int
  91 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  92 {
  93         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  94         struct panfrost_device *dev = pan_device(screen);
  95         bool is_deqp = dev->debug & PAN_DBG_DEQP;
  96
  97         /* Our GL 3.x implementation is WIP */
  98         bool is_gl3 = dev->debug & PAN_DBG_GL3;
  99         is_gl3 |= is_deqp;
 100
 101         /* Same with GLES 3 */
 102         bool is_gles3 = dev->debug & PAN_DBG_GLES3;
 103         is_gles3 |= is_gl3;
 104
 105         switch (param) {
 106         case PIPE_CAP_NPOT_TEXTURES:
 107         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 108         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 109         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 110         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 111         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 112         case PIPE_CAP_POINT_SPRITE:
 113         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 114         case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
 115                 return 1;
 116
 117         case PIPE_CAP_MAX_RENDER_TARGETS:
 118         case PIPE_CAP_FBFETCH:
 119         case PIPE_CAP_FBFETCH_COHERENT:
 120                 return is_gles3 ? 4 : 1;
 121
 122         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 123                 return 1;
 124
 125         case PIPE_CAP_SAMPLE_SHADING:
 126                 /* WIP */
 127                 return is_gl3 ? 1 : 0;
 128
 129         /* Throttling frames breaks pipelining */
 130         case PIPE_CAP_THROTTLE:
 131                 return 0;
 132
 133         case PIPE_CAP_OCCLUSION_QUERY:
 134                 return 1;
 135         case PIPE_CAP_QUERY_TIME_ELAPSED:
 136         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 137         case PIPE_CAP_QUERY_SO_OVERFLOW:
 138                 return 0;
 139
 140         case PIPE_CAP_TEXTURE_SWIZZLE:
 141                 return 1;
 142
 143         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 144         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 145                 return 1;
 146
 147         case PIPE_CAP_TGSI_INSTANCEID:
 148         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 149         case PIPE_CAP_PRIMITIVE_RESTART:
 150         case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
 151                 return 1;
 152
 153         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 154                 return is_gles3 ? 4 : 0;
 155         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 156         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 157                 return is_gles3 ? 64 : 0;
 158         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 159                 return 1;
 160
 161         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 162                 return 256;
 163
 164         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 165         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 166                 return is_gl3 ? 330 : (is_gles3 ? 140 : 120);
 167         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 168                 return is_gles3 ? 300 : 120;
 169
 170         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 171                 return 16;
 172
 173         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 174                 return is_gles3;
 175
 176         /* For faking GLES 3.1 for dEQP-GLES31 */
 177         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 178         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 179         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 180         case PIPE_CAP_CUBE_MAP_ARRAY:
 181                 return is_deqp;
 182
 183         /* For faking compute shaders */
 184         case PIPE_CAP_COMPUTE:
 185                 return is_deqp;
 186
 187         case PIPE_CAP_QUERY_TIMESTAMP:
 188         case PIPE_CAP_CONDITIONAL_RENDER:
 189                 return is_gl3;
 190
 191         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 192                 return 4096;
 193         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 194         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 195                 return 13;
 196
 197         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 198         case PIPE_CAP_INDEP_BLEND_ENABLE:
 199         case PIPE_CAP_INDEP_BLEND_FUNC:
 200                 return 1;
 201
 202         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 203                 /* Hardware is natively upper left */
 204                 return 0;
 205
 206         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 207         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 208         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 209         case PIPE_CAP_GENERATE_MIPMAP:
 210                 return 1;
 211
 212         /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
 213         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 214         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 215         case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
 216                 return dev->quirks & IS_BIFROST;
 217
 218         /* I really don't want to set this CAP but let's not swim against the
 219          * tide.. */
 220         case PIPE_CAP_TGSI_TEXCOORD:
 221                 return 1;
 222
 223         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 224         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 225                 return 1;
 226
 227         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 228                 return 0xffff;
 229
 230         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 231                 return 1;
 232
 233         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 234                 return 65536;
 235
 236         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 237                 return 0;
 238
 239         case PIPE_CAP_ENDIANNESS:
 240                 return PIPE_ENDIAN_NATIVE;
 241
 242         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 243                 return 1;
 244
 245         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 246                 return -8;
 247
 248         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 249                 return 7;
 250
 251         case PIPE_CAP_VENDOR_ID:
 252         case PIPE_CAP_DEVICE_ID:
 253                 return 0xFFFFFFFF;
 254
 255         case PIPE_CAP_ACCELERATED:
 256         case PIPE_CAP_UMA:
 257         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 258         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 259         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 260         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 261                 return 1;
 262
 263         case PIPE_CAP_VIDEO_MEMORY: {
 264                 uint64_t system_memory;
 265
 266                 if (!os_get_total_physical_memory(&system_memory))
 267                         return 0;
 268
 269                 return (int)(system_memory >> 20);
 270         }
 271
 272         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 273                 return 1;
 274
 275         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 276                 return 4;
 277
 278         case PIPE_CAP_MAX_VARYINGS:
 279                 return 16;
 280
 281         case PIPE_CAP_ALPHA_TEST:
 282         case PIPE_CAP_FLATSHADE:
 283         case PIPE_CAP_TWO_SIDED_COLOR:
 284         case PIPE_CAP_CLIP_PLANES:
 285                 return 0;
 286
 287         case PIPE_CAP_PACKED_STREAM_OUTPUT:
 288                 return 0;
 289
 290         case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
 291         case PIPE_CAP_PSIZ_CLAMPED:
 292                 return 1;
 293
 294         default:
 295                 return u_pipe_screen_get_param_defaults(screen, param);
 296         }
 297 }
 298
 299 static int
 300 panfrost_get_shader_param(struct pipe_screen *screen,
 301                           enum pipe_shader_type shader,
 302                           enum pipe_shader_cap param)
 303 {
 304         struct panfrost_device *dev = pan_device(screen);
 305         bool is_deqp = dev->debug & PAN_DBG_DEQP;
 306         bool is_fp16 = dev->debug & PAN_DBG_FP16;
 307
 308         if (shader != PIPE_SHADER_VERTEX &&
 309             shader != PIPE_SHADER_FRAGMENT &&
 310             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 311                 return 0;
 312
 313         /* this is probably not totally correct.. but it's a start: */
 314         switch (param) {
 315         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 316         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 317         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 318         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 319                 return 16384;
 320
 321         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 322                 return 1024;
 323
 324         case PIPE_SHADER_CAP_MAX_INPUTS:
 325                 return 16;
 326
 327         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 328                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
 329
 330         case PIPE_SHADER_CAP_MAX_TEMPS:
 331                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 332
 333         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 334                 return 16 * 1024 * sizeof(float);
 335
 336         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 337                 return PAN_MAX_CONST_BUFFERS;
 338
 339         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 340                 return 0;
 341
 342         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 343                 return 1;
 344         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 345                 return 0;
 346
 347         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 348                 return 0;
 349
 350         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 351                 return 1;
 352
 353         case PIPE_SHADER_CAP_SUBROUTINES:
 354                 return 0;
 355
 356         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 357                 return 0;
 358
 359         case PIPE_SHADER_CAP_INTEGERS:
 360                 return 1;
 361
 362         case PIPE_SHADER_CAP_FP16:
 363                 return !(dev->quirks & MIDGARD_BROKEN_FP16) || is_fp16;
 364
 365         case PIPE_SHADER_CAP_FP16_DERIVATIVES:
 366         case PIPE_SHADER_CAP_INT16:
 367         case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS:
 368         case PIPE_SHADER_CAP_INT64_ATOMICS:
 369         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 370         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 371         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 372         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 373         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 374                 return 0;
 375
 376         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 377         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 378                 return 16; /* XXX: How many? */
 379
 380         case PIPE_SHADER_CAP_PREFERRED_IR:
 381                 return PIPE_SHADER_IR_NIR;
 382
 383         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 384                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 385
 386         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 387                 return 32;
 388
 389         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 390         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 391                 return is_deqp ? 8 : 0;
 392         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 393         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 394                 return 0;
 395
 396         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 397         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 398                 return 0;
 399
 400         default:
 401                 /* Other params are unknown */
 402                 return 0;
 403         }
 404
 405         return 0;
 406 }
 407
 408 static float
 409 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 410 {
 411         switch (param) {
 412         case PIPE_CAPF_MAX_LINE_WIDTH:
 413
 414         /* fall-through */
 415         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 416                 return 255.0; /* arbitrary */
 417
 418         case PIPE_CAPF_MAX_POINT_WIDTH:
 419
 420         /* fall-through */
 421         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 422                 return 1024.0;
 423
 424         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 425                 return 16.0;
 426
 427         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 428                 return 16.0; /* arbitrary */
 429
 430         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 431         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 432         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 433                 return 0.0f;
 434
 435         default:
 436                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 437                 return 0.0;
 438         }
 439 }
 440
 441 /**
 442  * Query format support for creating a texture, drawing surface, etc.
 443  * \param format  the format to test
 444  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 445  */
 446 static bool
 447 panfrost_is_format_supported( struct pipe_screen *screen,
 448                               enum pipe_format format,
 449                               enum pipe_texture_target target,
 450                               unsigned sample_count,
 451                               unsigned storage_sample_count,
 452                               unsigned bind)
 453 {
 454         struct panfrost_device *dev = pan_device(screen);
 455         const struct util_format_description *format_desc;
 456
 457         assert(target == PIPE_BUFFER ||
 458                target == PIPE_TEXTURE_1D ||
 459                target == PIPE_TEXTURE_1D_ARRAY ||
 460                target == PIPE_TEXTURE_2D ||
 461                target == PIPE_TEXTURE_2D_ARRAY ||
 462                target == PIPE_TEXTURE_RECT ||
 463                target == PIPE_TEXTURE_3D ||
 464                target == PIPE_TEXTURE_CUBE ||
 465                target == PIPE_TEXTURE_CUBE_ARRAY);
 466
 467         format_desc = util_format_description(format);
 468
 469         if (!format_desc)
 470                 return false;
 471
 472         /* MSAA 4x supported, but no more. Technically some revisions of the
 473          * hardware can go up to 16x but we don't support higher modes yet.
 474          * MSAA 2x is notably not supported and gets rounded up to MSAA 4x. */
 475
 476         if (!(sample_count == 0 || sample_count == 1 || sample_count == 4))
 477                 return false;
 478
 479         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 480                 return false;
 481
 482         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 483          * more alpha than they ask for */
 484
 485         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 486         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 487
 488         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 489                 return false;
 490
 491         if (dev->debug & (PAN_DBG_GL3 | PAN_DBG_DEQP)) {
 492                 if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC)
 493                         return true;
 494         }
 495
 496         /* Check we support the format with the given bind */
 497
 498         unsigned relevant_bind = bind &
 499                 ( PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET
 500                 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_SAMPLER_VIEW);
 501
 502         struct panfrost_format fmt = panfrost_pipe_format_table[format];
 503
 504         /* Also check that compressed texture formats are supported on this
 505          * particular chip. They may not be depending on system integration
 506          * differences. */
 507
 508         if (!panfrost_supports_compressed_format(dev, fmt.hw))
 509                 return false;
 510
 511         return fmt.hw && ((relevant_bind & ~fmt.bind) == 0);
 512 }
 513
 514 static int
 515 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 516                 enum pipe_compute_cap param, void *ret)
 517 {
 518         struct panfrost_device *dev = pan_device(pscreen);
 519         const char * const ir = "panfrost";
 520
 521         if (!(dev->debug & PAN_DBG_DEQP))
 522                 return 0;
 523
 524 #define RET(x) do {                  \
 525    if (ret)                          \
 526       memcpy(ret, x, sizeof(x));     \
 527    return sizeof(x);                 \
 528 } while (0)
 529
 530         switch (param) {
 531         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 532                 RET((uint32_t []){ 64 });
 533
 534         case PIPE_COMPUTE_CAP_IR_TARGET:
 535                 if (ret)
 536                         sprintf(ret, "%s", ir);
 537                 return strlen(ir) * sizeof(char);
 538
 539         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 540                 RET((uint64_t []) { 3 });
 541
 542         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 543                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 544
 545         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 546                 RET(((uint64_t []) { 1024, 1024, 64 }));
 547
 548         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 549                 RET((uint64_t []) { 1024 });
 550
 551         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 552                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 553
 554         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 555                 RET((uint64_t []) { 32768 });
 556
 557         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 558         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 559                 RET((uint64_t []) { 4096 });
 560
 561         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 562                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 563
 564         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 565                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 566
 567         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 568                 RET((uint32_t []) { 9999 });  // TODO
 569
 570         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 571                 RET((uint32_t []) { 1 }); // TODO
 572
 573         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 574                 RET((uint32_t []) { 32 });  // TODO
 575
 576         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 577                 RET((uint64_t []) { 1024 }); // TODO
 578         }
 579
 580         return 0;
 581 }
 582
 583 static void
 584 panfrost_destroy_screen(struct pipe_screen *pscreen)
 585 {
 586         panfrost_close_device(pan_device(pscreen));
 587         ralloc_free(pscreen);
 588 }
 589
 590 static uint64_t
 591 panfrost_get_timestamp(struct pipe_screen *_screen)
 592 {
 593         return os_time_get_nano();
 594 }
 595
 596 static void
 597 panfrost_fence_reference(struct pipe_screen *pscreen,
 598                          struct pipe_fence_handle **ptr,
 599                          struct pipe_fence_handle *fence)
 600 {
 601         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 602         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 603         struct panfrost_fence *old = *p;
 604
 605         if (pipe_reference(&(*p)->reference, &f->reference)) {
 606                 util_dynarray_foreach(&old->syncfds, int, fd)
 607                         close(*fd);
 608                 util_dynarray_fini(&old->syncfds);
 609                 free(old);
 610         }
 611         *p = f;
 612 }
 613
 614 static bool
 615 panfrost_fence_finish(struct pipe_screen *pscreen,
 616                       struct pipe_context *ctx,
 617                       struct pipe_fence_handle *fence,
 618                       uint64_t timeout)
 619 {
 620         struct panfrost_device *dev = pan_device(pscreen);
 621         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 622         struct util_dynarray syncobjs;
 623         int ret;
 624
 625         /* All fences were already signaled */
 626         if (!util_dynarray_num_elements(&f->syncfds, int))
 627                 return true;
 628
 629         util_dynarray_init(&syncobjs, NULL);
 630         util_dynarray_foreach(&f->syncfds, int, fd) {
 631                 uint32_t syncobj;
 632
 633                 ret = drmSyncobjCreate(dev->fd, 0, &syncobj);
 634                 assert(!ret);
 635
 636                 ret = drmSyncobjImportSyncFile(dev->fd, syncobj, *fd);
 637                 assert(!ret);
 638                 util_dynarray_append(&syncobjs, uint32_t, syncobj);
 639         }
 640
 641         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 642         if (abs_timeout == OS_TIMEOUT_INFINITE)
 643                 abs_timeout = INT64_MAX;
 644
 645         ret = drmSyncobjWait(dev->fd, util_dynarray_begin(&syncobjs),
 646                              util_dynarray_num_elements(&syncobjs, uint32_t),
 647                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 648                              NULL);
 649
 650         util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
 651                 drmSyncobjDestroy(dev->fd, *syncobj);
 652
 653         return ret >= 0;
 654 }
 655
 656 struct panfrost_fence *
 657 panfrost_fence_create(struct panfrost_context *ctx,
 658                       struct util_dynarray *fences)
 659 {
 660         struct panfrost_device *device = pan_device(ctx->base.screen);
 661         struct panfrost_fence *f = calloc(1, sizeof(*f));
 662         if (!f)
 663                 return NULL;
 664
 665         util_dynarray_init(&f->syncfds, NULL);
 666
 667         /* Export fences from all pending batches. */
 668         util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
 669                 int fd = -1;
 670
 671                 /* The fence is already signaled, no need to export it. */
 672                 if ((*fence)->signaled)
 673                         continue;
 674
 675                 drmSyncobjExportSyncFile(device->fd, (*fence)->syncobj, &fd);
 676                 if (fd == -1)
 677                         fprintf(stderr, "export failed: %m\n");
 678
 679                 assert(fd != -1);
 680                 util_dynarray_append(&f->syncfds, int, fd);
 681         }
 682
 683         pipe_reference_init(&f->reference, 1);
 684
 685         return f;
 686 }
 687
 688 static const void *
 689 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 690                                      enum pipe_shader_ir ir,
 691                                      enum pipe_shader_type shader)
 692 {
 693         if (pan_device(pscreen)->quirks & IS_BIFROST)
 694                 return &bifrost_nir_options;
 695         else
 696                 return &midgard_nir_options;
 697 }
 698
 699 struct pipe_screen *
 700 panfrost_create_screen(int fd, struct renderonly *ro)
 701 {
 702         /* Blacklist apps known to be buggy under Panfrost */
 703         const char *proc = util_get_process_name();
 704         const char *blacklist[] = {
 705                 "chromium",
 706                 "chrome",
 707         };
 708
 709         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 710                 if ((strcmp(blacklist[i], proc) == 0))
 711                         return NULL;
 712         }
 713
 714         /* Create the screen */
 715         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 716
 717         if (!screen)
 718                 return NULL;
 719
 720         struct panfrost_device *dev = pan_device(&screen->base);
 721         panfrost_open_device(screen, fd, dev);
 722
 723         dev->debug = debug_get_flags_option("PAN_MESA_DEBUG", debug_options, 0);
 724
 725         if (ro) {
 726                 dev->ro = renderonly_dup(ro);
 727                 if (!dev->ro) {
 728                         if (dev->debug & PAN_DBG_MSGS)
 729                                 fprintf(stderr, "Failed to dup renderonly object\n");
 730
 731                         free(screen);
 732                         return NULL;
 733                 }
 734         }
 735
 736         /* Check if we're loading against a supported GPU model. */
 737
 738         switch (dev->gpu_id) {
 739         case 0x720: /* T720 */
 740         case 0x750: /* T760 */
 741         case 0x820: /* T820 */
 742         case 0x860: /* T860 */
 743                 break;
 744         case 0x7093: /* G31 */
 745         case 0x7212: /* G52 */
 746                 if (dev->debug & PAN_DBG_BIFROST)
 747                         break;
 748
 749                 /* fallthrough */
 750         default:
 751                 /* Fail to load against untested models */
 752                 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
 753                 panfrost_destroy_screen(&(screen->base));
 754                 return NULL;
 755         }
 756
 757         if (dev->debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 758                 pandecode_initialize(!(dev->debug & PAN_DBG_TRACE));
 759
 760         screen->base.destroy = panfrost_destroy_screen;
 761
 762         screen->base.get_name = panfrost_get_name;
 763         screen->base.get_vendor = panfrost_get_vendor;
 764         screen->base.get_device_vendor = panfrost_get_device_vendor;
 765         screen->base.get_param = panfrost_get_param;
 766         screen->base.get_shader_param = panfrost_get_shader_param;
 767         screen->base.get_compute_param = panfrost_get_compute_param;
 768         screen->base.get_paramf = panfrost_get_paramf;
 769         screen->base.get_timestamp = panfrost_get_timestamp;
 770         screen->base.is_format_supported = panfrost_is_format_supported;
 771         screen->base.context_create = panfrost_create_context;
 772         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 773         screen->base.fence_reference = panfrost_fence_reference;
 774         screen->base.fence_finish = panfrost_fence_finish;
 775         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 776
 777         panfrost_resource_screen_init(&screen->base);
 778
 779         return &screen->base;
 780 }