2 * Copyright (C) 2008 VMware, Inc.
3 * Copyright (C) 2014 Broadcom
4 * Copyright (C) 2018 Alyssa Rosenzweig
5 * Copyright (C) 2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #include "util/u_debug.h"
29 #include "util/u_memory.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_video.h"
33 #include "util/u_screen.h"
34 #include "util/os_time.h"
35 #include "pipe/p_defines.h"
36 #include "pipe/p_screen.h"
37 #include "draw/draw_context.h"
42 #include "drm-uapi/drm_fourcc.h"
44 #include "pan_screen.h"
45 #include "pan_resource.h"
46 #include "pan_public.h"
48 #include "pandecode/decode.h"
50 #include "pan_context.h"
51 #include "midgard/midgard_compile.h"
53 static const struct debug_named_value debug_options
[] = {
54 {"msgs", PAN_DBG_MSGS
, "Print debug messages"},
55 {"trace", PAN_DBG_TRACE
, "Trace the command stream"},
56 {"deqp", PAN_DBG_DEQP
, "Hacks for dEQP"},
57 {"afbc", PAN_DBG_AFBC
, "Enable non-conformant AFBC impl"},
61 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug
, "PAN_MESA_DEBUG", debug_options
, 0)
66 panfrost_get_name(struct pipe_screen
*screen
)
72 panfrost_get_vendor(struct pipe_screen
*screen
)
78 panfrost_get_device_vendor(struct pipe_screen
*screen
)
84 panfrost_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
86 /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
87 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
90 case PIPE_CAP_NPOT_TEXTURES
:
91 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
92 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
93 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
94 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
95 case PIPE_CAP_POINT_SPRITE
:
98 case PIPE_CAP_MAX_RENDER_TARGETS
:
99 return is_deqp
? 4 : 1;
102 case PIPE_CAP_OCCLUSION_QUERY
:
104 case PIPE_CAP_QUERY_TIME_ELAPSED
:
105 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
106 case PIPE_CAP_QUERY_TIMESTAMP
:
107 case PIPE_CAP_QUERY_SO_OVERFLOW
:
110 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
111 case PIPE_CAP_TEXTURE_SWIZZLE
:
114 case PIPE_CAP_TGSI_INSTANCEID
:
115 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
116 return is_deqp
? 1 : 0;
118 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
119 return is_deqp
? 4 : 0;
120 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
121 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
122 return is_deqp
? 64 : 0;
124 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
125 return is_deqp
? 256 : 0; /* for GL3 */
127 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
128 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
129 return is_deqp
? 140 : 120;
130 case PIPE_CAP_ESSL_FEATURE_LEVEL
:
131 return is_deqp
? 300 : 120;
133 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
134 return is_deqp
? 16 : 0;
136 case PIPE_CAP_CUBE_MAP_ARRAY
:
139 /* For faking GLES 3.1 for dEQP-GLES31 */
140 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
141 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS
:
142 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS
:
143 case PIPE_CAP_IMAGE_LOAD_FORMATTED
:
146 /* TODO: Where does this req come from in practice? */
147 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
150 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
152 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
153 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
156 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
157 case PIPE_CAP_INDEP_BLEND_ENABLE
:
158 case PIPE_CAP_INDEP_BLEND_FUNC
:
161 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
162 /* Hardware is natively upper left */
165 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
166 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
167 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
168 case PIPE_CAP_GENERATE_MIPMAP
:
171 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
172 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
175 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET
:
178 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
181 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
184 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
187 case PIPE_CAP_ENDIANNESS
:
188 return PIPE_ENDIAN_NATIVE
;
190 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
193 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
196 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
199 case PIPE_CAP_VENDOR_ID
:
200 case PIPE_CAP_DEVICE_ID
:
203 case PIPE_CAP_ACCELERATED
:
205 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
206 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
207 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
208 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
211 case PIPE_CAP_VIDEO_MEMORY
: {
212 uint64_t system_memory
;
214 if (!os_get_total_physical_memory(&system_memory
))
217 return (int)(system_memory
>> 20);
220 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
223 case PIPE_CAP_MAX_VARYINGS
:
227 return u_pipe_screen_get_param_defaults(screen
, param
);
232 panfrost_get_shader_param(struct pipe_screen
*screen
,
233 enum pipe_shader_type shader
,
234 enum pipe_shader_cap param
)
236 if (shader
!= PIPE_SHADER_VERTEX
&&
237 shader
!= PIPE_SHADER_FRAGMENT
) {
241 bool is_deqp
= pan_debug
& PAN_DBG_DEQP
;
243 /* this is probably not totally correct.. but it's a start: */
245 case PIPE_SHADER_CAP_SCALAR_ISA
:
248 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
250 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
251 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
252 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
255 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
258 case PIPE_SHADER_CAP_MAX_INPUTS
:
261 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
262 return shader
== PIPE_SHADER_FRAGMENT
? 4 : 8;
264 case PIPE_SHADER_CAP_MAX_TEMPS
:
265 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
267 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
268 return 16 * 1024 * sizeof(float);
270 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
271 return PAN_MAX_CONST_BUFFERS
;
273 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
276 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
278 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
281 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
284 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
287 case PIPE_SHADER_CAP_SUBROUTINES
:
290 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
293 case PIPE_SHADER_CAP_INTEGERS
:
296 case PIPE_SHADER_CAP_INT64_ATOMICS
:
297 case PIPE_SHADER_CAP_FP16
:
298 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
299 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
300 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
301 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
302 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
305 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
306 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
307 return 16; /* XXX: How many? */
309 case PIPE_SHADER_CAP_PREFERRED_IR
:
310 return PIPE_SHADER_IR_NIR
;
312 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
315 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
318 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
319 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
321 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
322 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
325 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
326 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
330 fprintf(stderr
, "unknown shader param %d\n", param
);
338 panfrost_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
341 case PIPE_CAPF_MAX_LINE_WIDTH
:
344 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
345 return 255.0; /* arbitrary */
347 case PIPE_CAPF_MAX_POINT_WIDTH
:
350 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
353 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
356 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
357 return 16.0; /* arbitrary */
359 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
360 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
361 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
365 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
371 * Query format support for creating a texture, drawing surface, etc.
372 * \param format the format to test
373 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
376 panfrost_is_format_supported( struct pipe_screen
*screen
,
377 enum pipe_format format
,
378 enum pipe_texture_target target
,
379 unsigned sample_count
,
380 unsigned storage_sample_count
,
383 const struct util_format_description
*format_desc
;
385 assert(target
== PIPE_BUFFER
||
386 target
== PIPE_TEXTURE_1D
||
387 target
== PIPE_TEXTURE_1D_ARRAY
||
388 target
== PIPE_TEXTURE_2D
||
389 target
== PIPE_TEXTURE_2D_ARRAY
||
390 target
== PIPE_TEXTURE_RECT
||
391 target
== PIPE_TEXTURE_3D
||
392 target
== PIPE_TEXTURE_CUBE
||
393 target
== PIPE_TEXTURE_CUBE_ARRAY
);
395 format_desc
= util_format_description(format
);
400 if (sample_count
> 1)
403 /* Format wishlist */
404 if (format
== PIPE_FORMAT_X8Z24_UNORM
)
407 if (format
== PIPE_FORMAT_A1B5G5R5_UNORM
|| format
== PIPE_FORMAT_X1B5G5R5_UNORM
)
411 if (format
== PIPE_FORMAT_B5G5R5A1_UNORM
)
414 /* Don't confuse poorly written apps (workaround dEQP bug) that expect
415 * more alpha than they ask for */
417 bool scanout
= bind
& (PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
| PIPE_BIND_DISPLAY_TARGET
);
418 bool renderable
= bind
& PIPE_BIND_RENDER_TARGET
;
420 if (scanout
&& renderable
&& !util_format_is_rgba8_variant(format_desc
))
423 if (format_desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
&&
424 format_desc
->layout
!= UTIL_FORMAT_LAYOUT_OTHER
) {
425 /* Compressed formats not yet hooked up. */
429 /* Internally, formats that are depth/stencil renderable are limited.
431 * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
432 * rendering perspective. That is, we render to Z24S8 (which we can
433 * AFBC compress), ignore the different when texturing (who cares?),
434 * and then in the off-chance there's a CPU read we blit back to
437 * ...alternatively, we can make the state tracker deal with that. */
439 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
441 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
442 case PIPE_FORMAT_Z24X8_UNORM
:
443 case PIPE_FORMAT_Z32_UNORM
:
444 case PIPE_FORMAT_Z32_FLOAT
:
445 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
458 panfrost_destroy_screen(struct pipe_screen
*pscreen
)
460 struct panfrost_screen
*screen
= pan_screen(pscreen
);
461 panfrost_bo_cache_evict_all(screen
);
466 panfrost_flush_frontbuffer(struct pipe_screen
*_screen
,
467 struct pipe_resource
*resource
,
468 unsigned level
, unsigned layer
,
469 void *context_private
,
470 struct pipe_box
*sub_box
)
472 /* TODO: Display target integration */
476 panfrost_get_timestamp(struct pipe_screen
*_screen
)
478 return os_time_get_nano();
482 panfrost_fence_reference(struct pipe_screen
*pscreen
,
483 struct pipe_fence_handle
**ptr
,
484 struct pipe_fence_handle
*fence
)
486 panfrost_drm_fence_reference(pscreen
, ptr
, fence
);
490 panfrost_fence_finish(struct pipe_screen
*pscreen
,
491 struct pipe_context
*ctx
,
492 struct pipe_fence_handle
*fence
,
495 return panfrost_drm_fence_finish(pscreen
, ctx
, fence
, timeout
);
499 panfrost_screen_get_compiler_options(struct pipe_screen
*pscreen
,
500 enum pipe_shader_ir ir
,
501 enum pipe_shader_type shader
)
503 return &midgard_nir_options
;
507 panfrost_create_screen(int fd
, struct renderonly
*ro
)
509 struct panfrost_screen
*screen
= rzalloc(NULL
, struct panfrost_screen
);
511 pan_debug
= debug_get_option_pan_debug();
517 screen
->ro
= renderonly_dup(ro
);
519 fprintf(stderr
, "Failed to dup renderonly object\n");
527 screen
->gpu_id
= panfrost_drm_query_gpu_version(screen
);
528 screen
->require_sfbd
= screen
->gpu_id
< 0x0750; /* T760 is the first to support MFBD */
530 /* Check if we're loading against a supported GPU model. */
532 switch (screen
->gpu_id
) {
533 case 0x750: /* T760 */
534 case 0x820: /* T820 */
535 case 0x860: /* T860 */
538 /* Fail to load against untested models */
539 debug_printf("panfrost: Unsupported model %X",
544 util_dynarray_init(&screen
->transient_bo
, screen
);
546 for (unsigned i
= 0; i
< ARRAY_SIZE(screen
->bo_cache
); ++i
)
547 list_inithead(&screen
->bo_cache
[i
]);
549 if (pan_debug
& PAN_DBG_TRACE
)
550 pandecode_initialize();
552 screen
->base
.destroy
= panfrost_destroy_screen
;
554 screen
->base
.get_name
= panfrost_get_name
;
555 screen
->base
.get_vendor
= panfrost_get_vendor
;
556 screen
->base
.get_device_vendor
= panfrost_get_device_vendor
;
557 screen
->base
.get_param
= panfrost_get_param
;
558 screen
->base
.get_shader_param
= panfrost_get_shader_param
;
559 screen
->base
.get_paramf
= panfrost_get_paramf
;
560 screen
->base
.get_timestamp
= panfrost_get_timestamp
;
561 screen
->base
.is_format_supported
= panfrost_is_format_supported
;
562 screen
->base
.context_create
= panfrost_create_context
;
563 screen
->base
.flush_frontbuffer
= panfrost_flush_frontbuffer
;
564 screen
->base
.get_compiler_options
= panfrost_screen_get_compiler_options
;
565 screen
->base
.fence_reference
= panfrost_fence_reference
;
566 screen
->base
.fence_finish
= panfrost_fence_finish
;
568 screen
->last_fragment_flushed
= true;
569 screen
->last_job
= NULL
;
571 panfrost_resource_screen_init(screen
);
573 return &screen
->base
;