src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "panfrost-quirks.h"
  56
  57 static const struct debug_named_value debug_options[] = {
  58         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  59         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  60         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  61         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  62         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  63         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  64         {"gles3",     PAN_DBG_GLES3,    "Enable experimental GLES3 implementation"},
  65         DEBUG_NAMED_VALUE_END
  66 };
  67
  68 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  69
  70 int pan_debug = 0;
  71
  72 static const char *
  73 panfrost_get_name(struct pipe_screen *screen)
  74 {
  75         return panfrost_model_name(pan_screen(screen)->gpu_id);
  76 }
  77
  78 static const char *
  79 panfrost_get_vendor(struct pipe_screen *screen)
  80 {
  81         return "Panfrost";
  82 }
  83
  84 static const char *
  85 panfrost_get_device_vendor(struct pipe_screen *screen)
  86 {
  87         return "Arm";
  88 }
  89
  90 static int
  91 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  92 {
  93         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  94         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  95
  96         /* Our GLES3 implementation is WIP */
  97         bool is_gles3 = pan_debug & PAN_DBG_GLES3;
  98         is_gles3 |= is_deqp;
  99
 100         switch (param) {
 101         case PIPE_CAP_NPOT_TEXTURES:
 102         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 103         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 104         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 105         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 106         case PIPE_CAP_POINT_SPRITE:
 107                 return 1;
 108
 109         case PIPE_CAP_MAX_RENDER_TARGETS:
 110                 return is_gles3 ? 4 : 1;
 111
 112         /* Throttling frames breaks pipelining */
 113         case PIPE_CAP_THROTTLE:
 114                 return 0;
 115
 116         case PIPE_CAP_OCCLUSION_QUERY:
 117                 return 1;
 118         case PIPE_CAP_QUERY_TIME_ELAPSED:
 119         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 120         case PIPE_CAP_QUERY_TIMESTAMP:
 121         case PIPE_CAP_QUERY_SO_OVERFLOW:
 122                 return 0;
 123
 124         case PIPE_CAP_TEXTURE_SWIZZLE:
 125                 return 1;
 126
 127         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 128         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 129                 return 1;
 130
 131         case PIPE_CAP_TGSI_INSTANCEID:
 132         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 133         case PIPE_CAP_PRIMITIVE_RESTART:
 134                 return 1;
 135
 136         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 137                 return is_gles3 ? 4 : 0;
 138         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 139         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 140                 return is_gles3 ? 64 : 0;
 141         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 142                 return 1;
 143
 144         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 145                 return 256;
 146
 147         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 148         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 149                 return is_gles3 ? 140 : 120;
 150         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 151                 return is_gles3 ? 300 : 120;
 152
 153         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 154                 return 16;
 155
 156                 return is_deqp;
 157
 158         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 159                 return is_gles3;
 160
 161         /* For faking GLES 3.1 for dEQP-GLES31 */
 162         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 163         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 164         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 165         case PIPE_CAP_CUBE_MAP_ARRAY:
 166                 return is_deqp;
 167
 168         /* For faking compute shaders */
 169         case PIPE_CAP_COMPUTE:
 170                 return is_deqp;
 171
 172         /* TODO: Where does this req come from in practice? */
 173         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 174                 return 1;
 175
 176         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 177                 return 4096;
 178         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 179         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 180                 return 13;
 181
 182         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 183         case PIPE_CAP_INDEP_BLEND_ENABLE:
 184         case PIPE_CAP_INDEP_BLEND_FUNC:
 185                 return 1;
 186
 187         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 188                 /* Hardware is natively upper left */
 189                 return 0;
 190
 191         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 192         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 193         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 194         case PIPE_CAP_GENERATE_MIPMAP:
 195                 return 1;
 196
 197         /* We would prefer varyings */
 198         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 199         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 200                 return 0;
 201
 202         /* I really don't want to set this CAP but let's not swim against the
 203          * tide.. */
 204         case PIPE_CAP_TGSI_TEXCOORD:
 205                 return 1;
 206
 207         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 208         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 209                 return 1;
 210
 211         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 212                 return 0xffff;
 213
 214         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 215                 return 1;
 216
 217         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 218                 return 65536;
 219
 220         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 221                 return 0;
 222
 223         case PIPE_CAP_ENDIANNESS:
 224                 return PIPE_ENDIAN_NATIVE;
 225
 226         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 227                 return 1;
 228
 229         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 230                 return -8;
 231
 232         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 233                 return 7;
 234
 235         case PIPE_CAP_VENDOR_ID:
 236         case PIPE_CAP_DEVICE_ID:
 237                 return 0xFFFFFFFF;
 238
 239         case PIPE_CAP_ACCELERATED:
 240         case PIPE_CAP_UMA:
 241         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 242         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 243         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 244         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 245                 return 1;
 246
 247         case PIPE_CAP_VIDEO_MEMORY: {
 248                 uint64_t system_memory;
 249
 250                 if (!os_get_total_physical_memory(&system_memory))
 251                         return 0;
 252
 253                 return (int)(system_memory >> 20);
 254         }
 255
 256         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 257                 return 1;
 258
 259         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 260                 return 4;
 261
 262         case PIPE_CAP_MAX_VARYINGS:
 263                 return 16;
 264
 265         case PIPE_CAP_ALPHA_TEST:
 266         case PIPE_CAP_FLATSHADE:
 267         case PIPE_CAP_TWO_SIDED_COLOR:
 268         case PIPE_CAP_CLIP_PLANES:
 269                 return 0;
 270
 271         default:
 272                 return u_pipe_screen_get_param_defaults(screen, param);
 273         }
 274 }
 275
 276 static int
 277 panfrost_get_shader_param(struct pipe_screen *screen,
 278                           enum pipe_shader_type shader,
 279                           enum pipe_shader_cap param)
 280 {
 281         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 282
 283         if (shader != PIPE_SHADER_VERTEX &&
 284             shader != PIPE_SHADER_FRAGMENT &&
 285             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 286                 return 0;
 287
 288         /* this is probably not totally correct.. but it's a start: */
 289         switch (param) {
 290         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 291         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 292         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 293         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 294                 return 16384;
 295
 296         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 297                 return 1024;
 298
 299         case PIPE_SHADER_CAP_MAX_INPUTS:
 300                 return 16;
 301
 302         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 303                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
 304
 305         case PIPE_SHADER_CAP_MAX_TEMPS:
 306                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 307
 308         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 309                 return 16 * 1024 * sizeof(float);
 310
 311         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 312                 return PAN_MAX_CONST_BUFFERS;
 313
 314         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 315                 return 0;
 316
 317         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 318                 return 1;
 319         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 320                 return 0;
 321
 322         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 323                 return 0;
 324
 325         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 326                 return 1;
 327
 328         case PIPE_SHADER_CAP_SUBROUTINES:
 329                 return 0;
 330
 331         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 332                 return 0;
 333
 334         case PIPE_SHADER_CAP_INTEGERS:
 335                 return 1;
 336
 337         case PIPE_SHADER_CAP_INT64_ATOMICS:
 338         case PIPE_SHADER_CAP_FP16:
 339         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 340         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 341         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 342         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 343         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 344                 return 0;
 345
 346         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 347         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 348                 return 16; /* XXX: How many? */
 349
 350         case PIPE_SHADER_CAP_PREFERRED_IR:
 351                 return PIPE_SHADER_IR_NIR;
 352
 353         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 354                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 355
 356         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 357                 return 32;
 358
 359         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 360         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 361                 return is_deqp ? 8 : 0;
 362         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 363         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 364                 return 0;
 365
 366         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 367         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 368                 return 0;
 369
 370         default:
 371                 DBG("unknown shader param %d\n", param);
 372                 return 0;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static float
 379 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 380 {
 381         switch (param) {
 382         case PIPE_CAPF_MAX_LINE_WIDTH:
 383
 384         /* fall-through */
 385         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 386                 return 255.0; /* arbitrary */
 387
 388         case PIPE_CAPF_MAX_POINT_WIDTH:
 389
 390         /* fall-through */
 391         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 392                 return 1024.0;
 393
 394         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 395                 return 16.0;
 396
 397         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 398                 return 16.0; /* arbitrary */
 399
 400         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 401         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 402         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 403                 return 0.0f;
 404
 405         default:
 406                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 407                 return 0.0;
 408         }
 409 }
 410
 411 /**
 412  * Query format support for creating a texture, drawing surface, etc.
 413  * \param format  the format to test
 414  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 415  */
 416 static bool
 417 panfrost_is_format_supported( struct pipe_screen *screen,
 418                               enum pipe_format format,
 419                               enum pipe_texture_target target,
 420                               unsigned sample_count,
 421                               unsigned storage_sample_count,
 422                               unsigned bind)
 423 {
 424         const struct util_format_description *format_desc;
 425
 426         assert(target == PIPE_BUFFER ||
 427                target == PIPE_TEXTURE_1D ||
 428                target == PIPE_TEXTURE_1D_ARRAY ||
 429                target == PIPE_TEXTURE_2D ||
 430                target == PIPE_TEXTURE_2D_ARRAY ||
 431                target == PIPE_TEXTURE_RECT ||
 432                target == PIPE_TEXTURE_3D ||
 433                target == PIPE_TEXTURE_CUBE ||
 434                target == PIPE_TEXTURE_CUBE_ARRAY);
 435
 436         format_desc = util_format_description(format);
 437
 438         if (!format_desc)
 439                 return false;
 440
 441         /* MSAA 4x supported, but no more. Technically some revisions of the
 442          * hardware can go up to 16x but we don't support higher modes yet. */
 443
 444         if (sample_count > 1 && !(pan_debug & PAN_DBG_DEQP))
 445                 return false;
 446
 447         if (sample_count > 4)
 448                 return false;
 449
 450         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 451                 return false;
 452
 453         /* Format wishlist */
 454         if (format == PIPE_FORMAT_X8Z24_UNORM)
 455                 return false;
 456
 457         if (format == PIPE_FORMAT_A1B5G5R5_UNORM || format == PIPE_FORMAT_X1B5G5R5_UNORM)
 458                 return false;
 459
 460         /* TODO */
 461         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 462                 return FALSE;
 463
 464         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 465          * more alpha than they ask for */
 466
 467         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 468         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 469
 470         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 471                 return false;
 472
 473         switch (format_desc->layout) {
 474                 case UTIL_FORMAT_LAYOUT_PLAIN:
 475                 case UTIL_FORMAT_LAYOUT_OTHER:
 476                         break;
 477                 case UTIL_FORMAT_LAYOUT_ETC:
 478                 case UTIL_FORMAT_LAYOUT_ASTC:
 479                         return true;
 480                 default:
 481                         return false;
 482         }
 483
 484         /* Internally, formats that are depth/stencil renderable are limited.
 485          *
 486          * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
 487          * rendering perspective. That is, we render to Z24S8 (which we can
 488          * AFBC compress), ignore the different when texturing (who cares?),
 489          * and then in the off-chance there's a CPU read we blit back to
 490          * staging.
 491          *
 492          * ...alternatively, we can make the state tracker deal with that. */
 493
 494         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 495                 switch (format) {
 496                         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 497                         case PIPE_FORMAT_Z24X8_UNORM:
 498                         case PIPE_FORMAT_Z32_UNORM:
 499                         case PIPE_FORMAT_Z32_FLOAT:
 500                         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 501                                 return true;
 502
 503                         default:
 504                                 return false;
 505                 }
 506         }
 507
 508         return true;
 509 }
 510
 511 static int
 512 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 513                 enum pipe_compute_cap param, void *ret)
 514 {
 515         const char * const ir = "panfrost";
 516
 517         if (!(pan_debug & PAN_DBG_DEQP))
 518                 return 0;
 519
 520 #define RET(x) do {                  \
 521    if (ret)                          \
 522       memcpy(ret, x, sizeof(x));     \
 523    return sizeof(x);                 \
 524 } while (0)
 525
 526         switch (param) {
 527         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 528                 RET((uint32_t []){ 64 });
 529
 530         case PIPE_COMPUTE_CAP_IR_TARGET:
 531                 if (ret)
 532                         sprintf(ret, "%s", ir);
 533                 return strlen(ir) * sizeof(char);
 534
 535         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 536                 RET((uint64_t []) { 3 });
 537
 538         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 539                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 540
 541         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 542                 RET(((uint64_t []) { 1024, 1024, 64 }));
 543
 544         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 545                 RET((uint64_t []) { 1024 });
 546
 547         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 548                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 549
 550         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 551                 RET((uint64_t []) { 32768 });
 552
 553         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 554         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 555                 RET((uint64_t []) { 4096 });
 556
 557         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 558                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 559
 560         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 561                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 562
 563         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 564                 RET((uint32_t []) { 9999 });  // TODO
 565
 566         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 567                 RET((uint32_t []) { 1 }); // TODO
 568
 569         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 570                 RET((uint32_t []) { 32 });  // TODO
 571
 572         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 573                 RET((uint64_t []) { 1024 }); // TODO
 574         }
 575
 576         return 0;
 577 }
 578
 579 static void
 580 panfrost_destroy_screen(struct pipe_screen *pscreen)
 581 {
 582         struct panfrost_screen *screen = pan_screen(pscreen);
 583         panfrost_bo_cache_evict_all(screen);
 584         pthread_mutex_destroy(&screen->bo_cache.lock);
 585         pthread_mutex_destroy(&screen->active_bos_lock);
 586         drmFreeVersion(screen->kernel_version);
 587         ralloc_free(screen);
 588 }
 589
 590 static uint64_t
 591 panfrost_get_timestamp(struct pipe_screen *_screen)
 592 {
 593         return os_time_get_nano();
 594 }
 595
 596 static void
 597 panfrost_fence_reference(struct pipe_screen *pscreen,
 598                          struct pipe_fence_handle **ptr,
 599                          struct pipe_fence_handle *fence)
 600 {
 601         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 602         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 603         struct panfrost_fence *old = *p;
 604
 605         if (pipe_reference(&(*p)->reference, &f->reference)) {
 606                 util_dynarray_foreach(&old->syncfds, int, fd)
 607                         close(*fd);
 608                 util_dynarray_fini(&old->syncfds);
 609                 free(old);
 610         }
 611         *p = f;
 612 }
 613
 614 static bool
 615 panfrost_fence_finish(struct pipe_screen *pscreen,
 616                       struct pipe_context *ctx,
 617                       struct pipe_fence_handle *fence,
 618                       uint64_t timeout)
 619 {
 620         struct panfrost_screen *screen = pan_screen(pscreen);
 621         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 622         struct util_dynarray syncobjs;
 623         int ret;
 624
 625         /* All fences were already signaled */
 626         if (!util_dynarray_num_elements(&f->syncfds, int))
 627                 return true;
 628
 629         util_dynarray_init(&syncobjs, NULL);
 630         util_dynarray_foreach(&f->syncfds, int, fd) {
 631                 uint32_t syncobj;
 632
 633                 ret = drmSyncobjCreate(screen->fd, 0, &syncobj);
 634                 assert(!ret);
 635
 636                 ret = drmSyncobjImportSyncFile(screen->fd, syncobj, *fd);
 637                 assert(!ret);
 638                 util_dynarray_append(&syncobjs, uint32_t, syncobj);
 639         }
 640
 641         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 642         if (abs_timeout == OS_TIMEOUT_INFINITE)
 643                 abs_timeout = INT64_MAX;
 644
 645         ret = drmSyncobjWait(screen->fd, util_dynarray_begin(&syncobjs),
 646                              util_dynarray_num_elements(&syncobjs, uint32_t),
 647                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 648                              NULL);
 649
 650         util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
 651                 drmSyncobjDestroy(screen->fd, *syncobj);
 652
 653         return ret >= 0;
 654 }
 655
 656 struct panfrost_fence *
 657 panfrost_fence_create(struct panfrost_context *ctx,
 658                       struct util_dynarray *fences)
 659 {
 660         struct panfrost_screen *screen = pan_screen(ctx->base.screen);
 661         struct panfrost_fence *f = calloc(1, sizeof(*f));
 662         if (!f)
 663                 return NULL;
 664
 665         util_dynarray_init(&f->syncfds, NULL);
 666
 667         /* Export fences from all pending batches. */
 668         util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
 669                 int fd = -1;
 670
 671                 /* The fence is already signaled, no need to export it. */
 672                 if ((*fence)->signaled)
 673                         continue;
 674
 675                 drmSyncobjExportSyncFile(screen->fd, (*fence)->syncobj, &fd);
 676                 if (fd == -1)
 677                         fprintf(stderr, "export failed: %m\n");
 678
 679                 assert(fd != -1);
 680                 util_dynarray_append(&f->syncfds, int, fd);
 681         }
 682
 683         pipe_reference_init(&f->reference, 1);
 684
 685         return f;
 686 }
 687
 688 static const void *
 689 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 690                                      enum pipe_shader_ir ir,
 691                                      enum pipe_shader_type shader)
 692 {
 693         return &midgard_nir_options;
 694 }
 695
 696 static uint32_t
 697 panfrost_active_bos_hash(const void *key)
 698 {
 699         const struct panfrost_bo *bo = key;
 700
 701         return _mesa_hash_data(&bo->gem_handle, sizeof(bo->gem_handle));
 702 }
 703
 704 static bool
 705 panfrost_active_bos_cmp(const void *keya, const void *keyb)
 706 {
 707         const struct panfrost_bo *a = keya, *b = keyb;
 708
 709         return a->gem_handle == b->gem_handle;
 710 }
 711
 712 struct pipe_screen *
 713 panfrost_create_screen(int fd, struct renderonly *ro)
 714 {
 715         pan_debug = debug_get_option_pan_debug();
 716
 717         /* Blacklist apps known to be buggy under Panfrost */
 718         const char *proc = util_get_process_name();
 719         const char *blacklist[] = {
 720                 "chromium",
 721                 "chrome",
 722         };
 723
 724         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 725                 if ((strcmp(blacklist[i], proc) == 0))
 726                         return NULL;
 727         }
 728
 729         /* Create the screen */
 730         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 731
 732         if (!screen)
 733                 return NULL;
 734
 735         if (ro) {
 736                 screen->ro = renderonly_dup(ro);
 737                 if (!screen->ro) {
 738                         DBG("Failed to dup renderonly object\n");
 739                         free(screen);
 740                         return NULL;
 741                 }
 742         }
 743
 744         screen->fd = fd;
 745
 746         screen->gpu_id = panfrost_query_gpu_version(screen->fd);
 747         screen->core_count = panfrost_query_core_count(screen->fd);
 748         screen->thread_tls_alloc = panfrost_query_thread_tls_alloc(screen->fd);
 749         screen->quirks = panfrost_get_quirks(screen->gpu_id);
 750         screen->kernel_version = drmGetVersion(fd);
 751
 752         /* Check if we're loading against a supported GPU model. */
 753
 754         switch (screen->gpu_id) {
 755         case 0x720: /* T720 */
 756         case 0x750: /* T760 */
 757         case 0x820: /* T820 */
 758         case 0x860: /* T860 */
 759                 break;
 760         default:
 761                 /* Fail to load against untested models */
 762                 debug_printf("panfrost: Unsupported model %X", screen->gpu_id);
 763                 return NULL;
 764         }
 765
 766         pthread_mutex_init(&screen->active_bos_lock, NULL);
 767         screen->active_bos = _mesa_set_create(screen, panfrost_active_bos_hash,
 768                                               panfrost_active_bos_cmp);
 769
 770         pthread_mutex_init(&screen->bo_cache.lock, NULL);
 771         list_inithead(&screen->bo_cache.lru);
 772         for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache.buckets); ++i)
 773                 list_inithead(&screen->bo_cache.buckets[i]);
 774
 775         if (pan_debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 776                 pandecode_initialize(!(pan_debug & PAN_DBG_TRACE));
 777
 778         screen->base.destroy = panfrost_destroy_screen;
 779
 780         screen->base.get_name = panfrost_get_name;
 781         screen->base.get_vendor = panfrost_get_vendor;
 782         screen->base.get_device_vendor = panfrost_get_device_vendor;
 783         screen->base.get_param = panfrost_get_param;
 784         screen->base.get_shader_param = panfrost_get_shader_param;
 785         screen->base.get_compute_param = panfrost_get_compute_param;
 786         screen->base.get_paramf = panfrost_get_paramf;
 787         screen->base.get_timestamp = panfrost_get_timestamp;
 788         screen->base.is_format_supported = panfrost_is_format_supported;
 789         screen->base.context_create = panfrost_create_context;
 790         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 791         screen->base.fence_reference = panfrost_fence_reference;
 792         screen->base.fence_finish = panfrost_fence_finish;
 793         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 794
 795         panfrost_resource_screen_init(screen);
 796
 797         return &screen->base;
 798 }