src/gallium/drivers/panfrost/pan_screen.c

   1 /*
   2  * Copyright (C) 2008 VMware, Inc.
   3  * Copyright (C) 2014 Broadcom
   4  * Copyright (C) 2018 Alyssa Rosenzweig
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  25  * SOFTWARE.
  26  *
  27  */
  28
  29 #include "util/u_debug.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32 #include "util/format/u_format_s3tc.h"
  33 #include "util/u_video.h"
  34 #include "util/u_screen.h"
  35 #include "util/os_time.h"
  36 #include "util/u_process.h"
  37 #include "pipe/p_defines.h"
  38 #include "pipe/p_screen.h"
  39 #include "draw/draw_context.h"
  40
  41 #include <fcntl.h>
  42
  43 #include "drm-uapi/drm_fourcc.h"
  44 #include "drm-uapi/panfrost_drm.h"
  45
  46 #include "pan_bo.h"
  47 #include "pan_screen.h"
  48 #include "pan_resource.h"
  49 #include "pan_public.h"
  50 #include "pan_util.h"
  51 #include "pandecode/decode.h"
  52
  53 #include "pan_context.h"
  54 #include "midgard/midgard_compile.h"
  55 #include "panfrost-quirks.h"
  56
  57 static const struct debug_named_value debug_options[] = {
  58         {"msgs",      PAN_DBG_MSGS,     "Print debug messages"},
  59         {"trace",     PAN_DBG_TRACE,    "Trace the command stream"},
  60         {"deqp",      PAN_DBG_DEQP,     "Hacks for dEQP"},
  61         {"afbc",      PAN_DBG_AFBC,     "Enable non-conformant AFBC impl"},
  62         {"sync",      PAN_DBG_SYNC,     "Wait for each job's completion and check for any GPU fault"},
  63         {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
  64         DEBUG_NAMED_VALUE_END
  65 };
  66
  67 DEBUG_GET_ONCE_FLAGS_OPTION(pan_debug, "PAN_MESA_DEBUG", debug_options, 0)
  68
  69 int pan_debug = 0;
  70
  71 static const char *
  72 panfrost_get_name(struct pipe_screen *screen)
  73 {
  74         return panfrost_model_name(pan_screen(screen)->gpu_id);
  75 }
  76
  77 static const char *
  78 panfrost_get_vendor(struct pipe_screen *screen)
  79 {
  80         return "Panfrost";
  81 }
  82
  83 static const char *
  84 panfrost_get_device_vendor(struct pipe_screen *screen)
  85 {
  86         return "Arm";
  87 }
  88
  89 static int
  90 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
  91 {
  92         /* We expose in-dev stuff for dEQP that we don't want apps to use yet */
  93         bool is_deqp = pan_debug & PAN_DBG_DEQP;
  94
  95         switch (param) {
  96         case PIPE_CAP_NPOT_TEXTURES:
  97         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
  98         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
  99         case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
 100         case PIPE_CAP_VERTEX_SHADER_SATURATE:
 101         case PIPE_CAP_POINT_SPRITE:
 102                 return 1;
 103
 104         case PIPE_CAP_MAX_RENDER_TARGETS:
 105                 return is_deqp ? 4 : 1;
 106
 107         /* Throttling frames breaks pipelining */
 108         case PIPE_CAP_THROTTLE:
 109                 return 0;
 110
 111         case PIPE_CAP_OCCLUSION_QUERY:
 112                 return 1;
 113         case PIPE_CAP_QUERY_TIME_ELAPSED:
 114         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 115         case PIPE_CAP_QUERY_TIMESTAMP:
 116         case PIPE_CAP_QUERY_SO_OVERFLOW:
 117                 return 0;
 118
 119         case PIPE_CAP_TEXTURE_SWIZZLE:
 120                 return 1;
 121
 122         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 123         case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
 124                 return 1;
 125
 126         case PIPE_CAP_TGSI_INSTANCEID:
 127         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 128                 return 1;
 129
 130         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 131                 return is_deqp ? 4 : 0;
 132         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 133         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 134                 return is_deqp ? 64 : 0;
 135         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 136                 return 1;
 137
 138         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 139                 return 256;
 140
 141         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 142         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 143                 return is_deqp ? 140 : 120;
 144         case PIPE_CAP_ESSL_FEATURE_LEVEL:
 145                 return is_deqp ? 300 : 120;
 146
 147         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 148                 return 16;
 149
 150         case PIPE_CAP_CUBE_MAP_ARRAY:
 151                 return is_deqp;
 152
 153         /* For faking GLES 3.1 for dEQP-GLES31 */
 154         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 155         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
 156         case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
 157         case PIPE_CAP_IMAGE_LOAD_FORMATTED:
 158                 return is_deqp;
 159
 160         /* For faking compute shaders */
 161         case PIPE_CAP_COMPUTE:
 162                 return is_deqp;
 163
 164         /* TODO: Where does this req come from in practice? */
 165         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 166                 return 1;
 167
 168         case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
 169                 return 4096;
 170         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 171         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 172                 return 13;
 173
 174         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 175         case PIPE_CAP_INDEP_BLEND_ENABLE:
 176         case PIPE_CAP_INDEP_BLEND_FUNC:
 177                 return 1;
 178
 179         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 180                 /* Hardware is natively upper left */
 181                 return 0;
 182
 183         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 184         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 185         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 186         case PIPE_CAP_GENERATE_MIPMAP:
 187                 return 1;
 188
 189         /* We would prefer varyings */
 190         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 191         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 192                 return 0;
 193
 194         /* I really don't want to set this CAP but let's not swim against the
 195          * tide.. */
 196         case PIPE_CAP_TGSI_TEXCOORD:
 197                 return 1;
 198
 199         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 200         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 201                 return 1;
 202
 203         case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
 204                 return 0xffff;
 205
 206         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 207                 return 1;
 208
 209         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 210                 return 65536;
 211
 212         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 213                 return 0;
 214
 215         case PIPE_CAP_ENDIANNESS:
 216                 return PIPE_ENDIAN_NATIVE;
 217
 218         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 219                 return 1;
 220
 221         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 222                 return -8;
 223
 224         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 225                 return 7;
 226
 227         case PIPE_CAP_VENDOR_ID:
 228         case PIPE_CAP_DEVICE_ID:
 229                 return 0xFFFFFFFF;
 230
 231         case PIPE_CAP_ACCELERATED:
 232         case PIPE_CAP_UMA:
 233         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 234         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 235         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 236         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 237                 return 1;
 238
 239         case PIPE_CAP_VIDEO_MEMORY: {
 240                 uint64_t system_memory;
 241
 242                 if (!os_get_total_physical_memory(&system_memory))
 243                         return 0;
 244
 245                 return (int)(system_memory >> 20);
 246         }
 247
 248         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 249                 return 1;
 250
 251         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 252                 return 4;
 253
 254         case PIPE_CAP_MAX_VARYINGS:
 255                 return 16;
 256
 257         case PIPE_CAP_ALPHA_TEST:
 258         case PIPE_CAP_FLATSHADE:
 259         case PIPE_CAP_TWO_SIDED_COLOR:
 260         case PIPE_CAP_CLIP_PLANES:
 261                 return 0;
 262
 263         default:
 264                 return u_pipe_screen_get_param_defaults(screen, param);
 265         }
 266 }
 267
 268 static int
 269 panfrost_get_shader_param(struct pipe_screen *screen,
 270                           enum pipe_shader_type shader,
 271                           enum pipe_shader_cap param)
 272 {
 273         bool is_deqp = pan_debug & PAN_DBG_DEQP;
 274
 275         if (shader != PIPE_SHADER_VERTEX &&
 276             shader != PIPE_SHADER_FRAGMENT &&
 277             !(shader == PIPE_SHADER_COMPUTE && is_deqp))
 278                 return 0;
 279
 280         /* this is probably not totally correct.. but it's a start: */
 281         switch (param) {
 282         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 283         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 284         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 285         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 286                 return 16384;
 287
 288         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 289                 return 1024;
 290
 291         case PIPE_SHADER_CAP_MAX_INPUTS:
 292                 return 16;
 293
 294         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 295                 return shader == PIPE_SHADER_FRAGMENT ? 4 : 16;
 296
 297         case PIPE_SHADER_CAP_MAX_TEMPS:
 298                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 299
 300         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 301                 return 16 * 1024 * sizeof(float);
 302
 303         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 304                 return PAN_MAX_CONST_BUFFERS;
 305
 306         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 307                 return 0;
 308
 309         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 310                 return 1;
 311         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 312                 return 0;
 313
 314         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 315                 return 0;
 316
 317         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 318                 return 1;
 319
 320         case PIPE_SHADER_CAP_SUBROUTINES:
 321                 return 0;
 322
 323         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 324                 return 0;
 325
 326         case PIPE_SHADER_CAP_INTEGERS:
 327                 return 1;
 328
 329         case PIPE_SHADER_CAP_INT64_ATOMICS:
 330         case PIPE_SHADER_CAP_FP16:
 331         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 332         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 333         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 334         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 335         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 336                 return 0;
 337
 338         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 339         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 340                 return 16; /* XXX: How many? */
 341
 342         case PIPE_SHADER_CAP_PREFERRED_IR:
 343                 return PIPE_SHADER_IR_NIR;
 344
 345         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 346                 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
 347
 348         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 349                 return 32;
 350
 351         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 352         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 353                 return is_deqp ? 4 : 0;
 354         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 355         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 356                 return 0;
 357
 358         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 359         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 360                 return 0;
 361
 362         default:
 363                 DBG("unknown shader param %d\n", param);
 364                 return 0;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static float
 371 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 372 {
 373         switch (param) {
 374         case PIPE_CAPF_MAX_LINE_WIDTH:
 375
 376         /* fall-through */
 377         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 378                 return 255.0; /* arbitrary */
 379
 380         case PIPE_CAPF_MAX_POINT_WIDTH:
 381
 382         /* fall-through */
 383         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 384                 return 1024.0;
 385
 386         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 387                 return 16.0;
 388
 389         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 390                 return 16.0; /* arbitrary */
 391
 392         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 393         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 394         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 395                 return 0.0f;
 396
 397         default:
 398                 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 399                 return 0.0;
 400         }
 401 }
 402
 403 /**
 404  * Query format support for creating a texture, drawing surface, etc.
 405  * \param format  the format to test
 406  * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
 407  */
 408 static bool
 409 panfrost_is_format_supported( struct pipe_screen *screen,
 410                               enum pipe_format format,
 411                               enum pipe_texture_target target,
 412                               unsigned sample_count,
 413                               unsigned storage_sample_count,
 414                               unsigned bind)
 415 {
 416         const struct util_format_description *format_desc;
 417
 418         assert(target == PIPE_BUFFER ||
 419                target == PIPE_TEXTURE_1D ||
 420                target == PIPE_TEXTURE_1D_ARRAY ||
 421                target == PIPE_TEXTURE_2D ||
 422                target == PIPE_TEXTURE_2D_ARRAY ||
 423                target == PIPE_TEXTURE_RECT ||
 424                target == PIPE_TEXTURE_3D ||
 425                target == PIPE_TEXTURE_CUBE ||
 426                target == PIPE_TEXTURE_CUBE_ARRAY);
 427
 428         format_desc = util_format_description(format);
 429
 430         if (!format_desc)
 431                 return false;
 432
 433         /* MSAA 4x supported, but no more. Technically some revisions of the
 434          * hardware can go up to 16x but we don't support higher modes yet. */
 435
 436         if (sample_count > 1 && !(pan_debug & PAN_DBG_DEQP))
 437                 return false;
 438
 439         if (sample_count > 4)
 440                 return false;
 441
 442         if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
 443                 return false;
 444
 445         /* Format wishlist */
 446         if (format == PIPE_FORMAT_X8Z24_UNORM)
 447                 return false;
 448
 449         if (format == PIPE_FORMAT_A1B5G5R5_UNORM || format == PIPE_FORMAT_X1B5G5R5_UNORM)
 450                 return false;
 451
 452         /* TODO */
 453         if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
 454                 return FALSE;
 455
 456         /* Don't confuse poorly written apps (workaround dEQP bug) that expect
 457          * more alpha than they ask for */
 458
 459         bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | PIPE_BIND_DISPLAY_TARGET);
 460         bool renderable = bind & PIPE_BIND_RENDER_TARGET;
 461
 462         if (scanout && renderable && !util_format_is_rgba8_variant(format_desc))
 463                 return false;
 464
 465         switch (format_desc->layout) {
 466                 case UTIL_FORMAT_LAYOUT_PLAIN:
 467                 case UTIL_FORMAT_LAYOUT_OTHER:
 468                         break;
 469                 case UTIL_FORMAT_LAYOUT_ETC:
 470                 case UTIL_FORMAT_LAYOUT_ASTC:
 471                         return true;
 472                 default:
 473                         return false;
 474         }
 475
 476         /* Internally, formats that are depth/stencil renderable are limited.
 477          *
 478          * In particular: Z16, Z24, Z24S8, S8 are all identical from the GPU
 479          * rendering perspective. That is, we render to Z24S8 (which we can
 480          * AFBC compress), ignore the different when texturing (who cares?),
 481          * and then in the off-chance there's a CPU read we blit back to
 482          * staging.
 483          *
 484          * ...alternatively, we can make the state tracker deal with that. */
 485
 486         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 487                 switch (format) {
 488                         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 489                         case PIPE_FORMAT_Z24X8_UNORM:
 490                         case PIPE_FORMAT_Z32_UNORM:
 491                         case PIPE_FORMAT_Z32_FLOAT:
 492                         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 493                                 return true;
 494
 495                         default:
 496                                 return false;
 497                 }
 498         }
 499
 500         return true;
 501 }
 502
 503 static int
 504 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 505                 enum pipe_compute_cap param, void *ret)
 506 {
 507         const char * const ir = "panfrost";
 508
 509         if (!(pan_debug & PAN_DBG_DEQP))
 510                 return 0;
 511
 512 #define RET(x) do {                  \
 513    if (ret)                          \
 514       memcpy(ret, x, sizeof(x));     \
 515    return sizeof(x);                 \
 516 } while (0)
 517
 518         switch (param) {
 519         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 520                 RET((uint32_t []){ 64 });
 521
 522         case PIPE_COMPUTE_CAP_IR_TARGET:
 523                 if (ret)
 524                         sprintf(ret, "%s", ir);
 525                 return strlen(ir) * sizeof(char);
 526
 527         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 528                 RET((uint64_t []) { 3 });
 529
 530         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 531                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 532
 533         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 534                 RET(((uint64_t []) { 1024, 1024, 64 }));
 535
 536         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 537                 RET((uint64_t []) { 1024 });
 538
 539         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 540                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 541
 542         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 543                 RET((uint64_t []) { 32768 });
 544
 545         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 546         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 547                 RET((uint64_t []) { 4096 });
 548
 549         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 550                 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
 551
 552         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 553                 RET((uint32_t []) { 800 /* MHz -- TODO */ });
 554
 555         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 556                 RET((uint32_t []) { 9999 });  // TODO
 557
 558         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 559                 RET((uint32_t []) { 1 }); // TODO
 560
 561         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 562                 RET((uint32_t []) { 32 });  // TODO
 563
 564         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 565                 RET((uint64_t []) { 1024 }); // TODO
 566         }
 567
 568         return 0;
 569 }
 570
 571 static void
 572 panfrost_destroy_screen(struct pipe_screen *pscreen)
 573 {
 574         struct panfrost_screen *screen = pan_screen(pscreen);
 575         panfrost_bo_cache_evict_all(screen);
 576         pthread_mutex_destroy(&screen->bo_cache.lock);
 577         pthread_mutex_destroy(&screen->active_bos_lock);
 578         drmFreeVersion(screen->kernel_version);
 579         ralloc_free(screen);
 580 }
 581
 582 static void
 583 panfrost_flush_frontbuffer(struct pipe_screen *_screen,
 584                            struct pipe_resource *resource,
 585                            unsigned level, unsigned layer,
 586                            void *context_private,
 587                            struct pipe_box *sub_box)
 588 {
 589         /* TODO: Display target integration */
 590 }
 591
 592 static uint64_t
 593 panfrost_get_timestamp(struct pipe_screen *_screen)
 594 {
 595         return os_time_get_nano();
 596 }
 597
 598 static void
 599 panfrost_fence_reference(struct pipe_screen *pscreen,
 600                          struct pipe_fence_handle **ptr,
 601                          struct pipe_fence_handle *fence)
 602 {
 603         struct panfrost_fence **p = (struct panfrost_fence **)ptr;
 604         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 605         struct panfrost_fence *old = *p;
 606
 607         if (pipe_reference(&(*p)->reference, &f->reference)) {
 608                 util_dynarray_foreach(&old->syncfds, int, fd)
 609                         close(*fd);
 610                 util_dynarray_fini(&old->syncfds);
 611                 free(old);
 612         }
 613         *p = f;
 614 }
 615
 616 static bool
 617 panfrost_fence_finish(struct pipe_screen *pscreen,
 618                       struct pipe_context *ctx,
 619                       struct pipe_fence_handle *fence,
 620                       uint64_t timeout)
 621 {
 622         struct panfrost_screen *screen = pan_screen(pscreen);
 623         struct panfrost_fence *f = (struct panfrost_fence *)fence;
 624         struct util_dynarray syncobjs;
 625         int ret;
 626
 627         /* All fences were already signaled */
 628         if (!util_dynarray_num_elements(&f->syncfds, int))
 629                 return true;
 630
 631         util_dynarray_init(&syncobjs, NULL);
 632         util_dynarray_foreach(&f->syncfds, int, fd) {
 633                 uint32_t syncobj;
 634
 635                 ret = drmSyncobjCreate(screen->fd, 0, &syncobj);
 636                 assert(!ret);
 637
 638                 ret = drmSyncobjImportSyncFile(screen->fd, syncobj, *fd);
 639                 assert(!ret);
 640                 util_dynarray_append(&syncobjs, uint32_t, syncobj);
 641         }
 642
 643         uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
 644         if (abs_timeout == OS_TIMEOUT_INFINITE)
 645                 abs_timeout = INT64_MAX;
 646
 647         ret = drmSyncobjWait(screen->fd, util_dynarray_begin(&syncobjs),
 648                              util_dynarray_num_elements(&syncobjs, uint32_t),
 649                              abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
 650                              NULL);
 651
 652         util_dynarray_foreach(&syncobjs, uint32_t, syncobj)
 653                 drmSyncobjDestroy(screen->fd, *syncobj);
 654
 655         return ret >= 0;
 656 }
 657
 658 struct panfrost_fence *
 659 panfrost_fence_create(struct panfrost_context *ctx,
 660                       struct util_dynarray *fences)
 661 {
 662         struct panfrost_screen *screen = pan_screen(ctx->base.screen);
 663         struct panfrost_fence *f = calloc(1, sizeof(*f));
 664         if (!f)
 665                 return NULL;
 666
 667         util_dynarray_init(&f->syncfds, NULL);
 668
 669         /* Export fences from all pending batches. */
 670         util_dynarray_foreach(fences, struct panfrost_batch_fence *, fence) {
 671                 int fd = -1;
 672
 673                 /* The fence is already signaled, no need to export it. */
 674                 if ((*fence)->signaled)
 675                         continue;
 676
 677                 drmSyncobjExportSyncFile(screen->fd, (*fence)->syncobj, &fd);
 678                 if (fd == -1)
 679                         fprintf(stderr, "export failed: %m\n");
 680
 681                 assert(fd != -1);
 682                 util_dynarray_append(&f->syncfds, int, fd);
 683         }
 684
 685         pipe_reference_init(&f->reference, 1);
 686
 687         return f;
 688 }
 689
 690 static const void *
 691 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
 692                                      enum pipe_shader_ir ir,
 693                                      enum pipe_shader_type shader)
 694 {
 695         return &midgard_nir_options;
 696 }
 697
 698 static uint32_t
 699 panfrost_active_bos_hash(const void *key)
 700 {
 701         const struct panfrost_bo *bo = key;
 702
 703         return _mesa_hash_data(&bo->gem_handle, sizeof(bo->gem_handle));
 704 }
 705
 706 static bool
 707 panfrost_active_bos_cmp(const void *keya, const void *keyb)
 708 {
 709         const struct panfrost_bo *a = keya, *b = keyb;
 710
 711         return a->gem_handle == b->gem_handle;
 712 }
 713
 714 struct pipe_screen *
 715 panfrost_create_screen(int fd, struct renderonly *ro)
 716 {
 717         pan_debug = debug_get_option_pan_debug();
 718
 719         /* Blacklist apps known to be buggy under Panfrost */
 720         const char *proc = util_get_process_name();
 721         const char *blacklist[] = {
 722                 "chromium",
 723                 "chrome",
 724         };
 725
 726         for (unsigned i = 0; i < ARRAY_SIZE(blacklist); ++i) {
 727                 if ((strcmp(blacklist[i], proc) == 0))
 728                         return NULL;
 729         }
 730
 731         /* Create the screen */
 732         struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
 733
 734         if (!screen)
 735                 return NULL;
 736
 737         if (ro) {
 738                 screen->ro = renderonly_dup(ro);
 739                 if (!screen->ro) {
 740                         DBG("Failed to dup renderonly object\n");
 741                         free(screen);
 742                         return NULL;
 743                 }
 744         }
 745
 746         screen->fd = fd;
 747
 748         screen->gpu_id = panfrost_query_gpu_version(screen->fd);
 749         screen->core_count = panfrost_query_core_count(screen->fd);
 750         screen->thread_tls_alloc = panfrost_query_thread_tls_alloc(screen->fd);
 751         screen->quirks = panfrost_get_quirks(screen->gpu_id);
 752         screen->kernel_version = drmGetVersion(fd);
 753
 754         /* Check if we're loading against a supported GPU model. */
 755
 756         switch (screen->gpu_id) {
 757         case 0x720: /* T720 */
 758         case 0x750: /* T760 */
 759         case 0x820: /* T820 */
 760         case 0x860: /* T860 */
 761                 break;
 762         default:
 763                 /* Fail to load against untested models */
 764                 debug_printf("panfrost: Unsupported model %X", screen->gpu_id);
 765                 return NULL;
 766         }
 767
 768         pthread_mutex_init(&screen->active_bos_lock, NULL);
 769         screen->active_bos = _mesa_set_create(screen, panfrost_active_bos_hash,
 770                                               panfrost_active_bos_cmp);
 771
 772         pthread_mutex_init(&screen->bo_cache.lock, NULL);
 773         list_inithead(&screen->bo_cache.lru);
 774         for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache.buckets); ++i)
 775                 list_inithead(&screen->bo_cache.buckets[i]);
 776
 777         if (pan_debug & (PAN_DBG_TRACE | PAN_DBG_SYNC))
 778                 pandecode_initialize();
 779
 780         screen->base.destroy = panfrost_destroy_screen;
 781
 782         screen->base.get_name = panfrost_get_name;
 783         screen->base.get_vendor = panfrost_get_vendor;
 784         screen->base.get_device_vendor = panfrost_get_device_vendor;
 785         screen->base.get_param = panfrost_get_param;
 786         screen->base.get_shader_param = panfrost_get_shader_param;
 787         screen->base.get_compute_param = panfrost_get_compute_param;
 788         screen->base.get_paramf = panfrost_get_paramf;
 789         screen->base.get_timestamp = panfrost_get_timestamp;
 790         screen->base.is_format_supported = panfrost_is_format_supported;
 791         screen->base.context_create = panfrost_create_context;
 792         screen->base.flush_frontbuffer = panfrost_flush_frontbuffer;
 793         screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
 794         screen->base.fence_reference = panfrost_fence_reference;
 795         screen->base.fence_finish = panfrost_fence_finish;
 796         screen->base.set_damage_region = panfrost_resource_set_damage_region;
 797
 798         panfrost_resource_screen_init(screen);
 799
 800         return &screen->base;
 801 }