Merge branch 'mesa_7_7_branch'
[mesa.git] / src / gallium / drivers / r300 / r300_chipset.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "r300_chipset.h"
24
25 #include "util/u_debug.h"
26
27 /* r300_chipset: A file all to itself for deducing the various properties of
28 * Radeons. */
29
30 /* Parse a PCI ID and fill an r300_capabilities struct with information. */
31 void r300_parse_chipset(struct r300_capabilities* caps)
32 {
33 /* Reasonable defaults */
34 caps->num_vert_fpus = 4;
35 caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;
36 caps->is_r400 = FALSE;
37 caps->is_r500 = FALSE;
38 caps->high_second_pipe = FALSE;
39
40
41 /* Note: These are not ordered by PCI ID. I leave that task to GCC,
42 * which will perform the ordering while collating jump tables. Instead,
43 * I've tried to group them according to capabilities and age. */
44 switch (caps->pci_id) {
45 case 0x4144:
46 caps->family = CHIP_FAMILY_R300;
47 caps->high_second_pipe = TRUE;
48 break;
49
50 case 0x4145:
51 case 0x4146:
52 case 0x4147:
53 case 0x4E44:
54 case 0x4E45:
55 case 0x4E46:
56 case 0x4E47:
57 caps->family = CHIP_FAMILY_R300;
58 caps->high_second_pipe = TRUE;
59 break;
60
61 case 0x4150:
62 case 0x4151:
63 case 0x4152:
64 case 0x4153:
65 case 0x4154:
66 case 0x4155:
67 case 0x4156:
68 case 0x4E50:
69 case 0x4E51:
70 case 0x4E52:
71 case 0x4E53:
72 case 0x4E54:
73 case 0x4E56:
74 caps->family = CHIP_FAMILY_RV350;
75 caps->high_second_pipe = TRUE;
76 break;
77
78 case 0x4148:
79 case 0x4149:
80 case 0x414A:
81 case 0x414B:
82 case 0x4E48:
83 case 0x4E49:
84 case 0x4E4B:
85 caps->family = CHIP_FAMILY_R350;
86 caps->high_second_pipe = TRUE;
87 break;
88
89 case 0x4E4A:
90 caps->family = CHIP_FAMILY_R360;
91 caps->high_second_pipe = TRUE;
92 break;
93
94 case 0x5460:
95 case 0x5462:
96 case 0x5464:
97 case 0x5B60:
98 case 0x5B62:
99 case 0x5B63:
100 case 0x5B64:
101 case 0x5B65:
102 caps->family = CHIP_FAMILY_RV370;
103 caps->high_second_pipe = TRUE;
104 break;
105
106 case 0x3150:
107 case 0x3152:
108 case 0x3154:
109 case 0x3E50:
110 case 0x3E54:
111 caps->family = CHIP_FAMILY_RV380;
112 caps->high_second_pipe = TRUE;
113 break;
114
115 case 0x4A48:
116 case 0x4A49:
117 case 0x4A4A:
118 case 0x4A4B:
119 case 0x4A4C:
120 case 0x4A4D:
121 case 0x4A4E:
122 case 0x4A4F:
123 case 0x4A50:
124 case 0x4A54:
125 caps->family = CHIP_FAMILY_R420;
126 caps->num_vert_fpus = 6;
127 caps->is_r400 = TRUE;
128 break;
129
130 case 0x5548:
131 case 0x5549:
132 case 0x554A:
133 case 0x554B:
134 case 0x5550:
135 case 0x5551:
136 case 0x5552:
137 case 0x5554:
138 case 0x5D57:
139 caps->family = CHIP_FAMILY_R423;
140 caps->num_vert_fpus = 6;
141 caps->is_r400 = TRUE;
142 break;
143
144 case 0x554C:
145 case 0x554D:
146 case 0x554E:
147 case 0x554F:
148 case 0x5D48:
149 case 0x5D49:
150 case 0x5D4A:
151 caps->family = CHIP_FAMILY_R430;
152 caps->num_vert_fpus = 6;
153 caps->is_r400 = TRUE;
154 break;
155
156 case 0x5D4C:
157 case 0x5D4D:
158 case 0x5D4E:
159 case 0x5D4F:
160 case 0x5D50:
161 case 0x5D52:
162 caps->family = CHIP_FAMILY_R480;
163 caps->num_vert_fpus = 6;
164 caps->is_r400 = TRUE;
165 break;
166
167 case 0x4B48:
168 case 0x4B49:
169 case 0x4B4A:
170 case 0x4B4B:
171 case 0x4B4C:
172 caps->family = CHIP_FAMILY_R481;
173 caps->num_vert_fpus = 6;
174 caps->is_r400 = TRUE;
175 break;
176
177 case 0x5E4C:
178 case 0x5E4F:
179 case 0x564A:
180 case 0x564B:
181 case 0x564F:
182 case 0x5652:
183 case 0x5653:
184 case 0x5657:
185 case 0x5E48:
186 case 0x5E4A:
187 case 0x5E4B:
188 case 0x5E4D:
189 caps->family = CHIP_FAMILY_RV410;
190 caps->num_vert_fpus = 6;
191 caps->is_r400 = TRUE;
192 break;
193
194 case 0x5954:
195 case 0x5955:
196 caps->family = CHIP_FAMILY_RS480;
197 caps->has_tcl = FALSE;
198 break;
199
200 case 0x5974:
201 case 0x5975:
202 caps->family = CHIP_FAMILY_RS482;
203 caps->has_tcl = FALSE;
204 break;
205
206 case 0x5A41:
207 case 0x5A42:
208 caps->family = CHIP_FAMILY_RS400;
209 caps->has_tcl = FALSE;
210 break;
211
212 case 0x5A61:
213 case 0x5A62:
214 caps->family = CHIP_FAMILY_RC410;
215 caps->has_tcl = FALSE;
216 break;
217
218 case 0x791E:
219 case 0x791F:
220 caps->family = CHIP_FAMILY_RS690;
221 caps->has_tcl = FALSE;
222 caps->is_r400 = TRUE;
223 break;
224
225 case 0x793F:
226 case 0x7941:
227 case 0x7942:
228 caps->family = CHIP_FAMILY_RS600;
229 caps->has_tcl = FALSE;
230 caps->is_r400 = TRUE;
231 break;
232
233 case 0x796C:
234 case 0x796D:
235 case 0x796E:
236 case 0x796F:
237 caps->family = CHIP_FAMILY_RS740;
238 caps->has_tcl = FALSE;
239 caps->is_r400 = TRUE;
240 break;
241
242 case 0x7100:
243 case 0x7101:
244 case 0x7102:
245 case 0x7103:
246 case 0x7104:
247 case 0x7105:
248 case 0x7106:
249 case 0x7108:
250 case 0x7109:
251 case 0x710A:
252 case 0x710B:
253 case 0x710C:
254 case 0x710E:
255 case 0x710F:
256 caps->family = CHIP_FAMILY_R520;
257 caps->num_vert_fpus = 8;
258 caps->is_r500 = TRUE;
259 break;
260
261 case 0x7140:
262 case 0x7141:
263 case 0x7142:
264 case 0x7143:
265 case 0x7144:
266 case 0x7145:
267 case 0x7146:
268 case 0x7147:
269 case 0x7149:
270 case 0x714A:
271 case 0x714B:
272 case 0x714C:
273 case 0x714D:
274 case 0x714E:
275 case 0x714F:
276 case 0x7151:
277 case 0x7152:
278 case 0x7153:
279 case 0x715E:
280 case 0x715F:
281 case 0x7180:
282 case 0x7181:
283 case 0x7183:
284 case 0x7186:
285 case 0x7187:
286 case 0x7188:
287 case 0x718A:
288 case 0x718B:
289 case 0x718C:
290 case 0x718D:
291 case 0x718F:
292 case 0x7193:
293 case 0x7196:
294 case 0x719B:
295 case 0x719F:
296 case 0x7200:
297 case 0x7210:
298 case 0x7211:
299 caps->family = CHIP_FAMILY_RV515;
300 caps->num_vert_fpus = 2;
301 caps->is_r500 = TRUE;
302 break;
303
304 case 0x71C0:
305 case 0x71C1:
306 case 0x71C2:
307 case 0x71C3:
308 case 0x71C4:
309 case 0x71C5:
310 case 0x71C6:
311 case 0x71C7:
312 case 0x71CD:
313 case 0x71CE:
314 case 0x71D2:
315 case 0x71D4:
316 case 0x71D5:
317 case 0x71D6:
318 case 0x71DA:
319 case 0x71DE:
320 caps->family = CHIP_FAMILY_RV530;
321 caps->num_vert_fpus = 5;
322 caps->is_r500 = TRUE;
323 break;
324
325 case 0x7240:
326 case 0x7243:
327 case 0x7244:
328 case 0x7245:
329 case 0x7246:
330 case 0x7247:
331 case 0x7248:
332 case 0x7249:
333 case 0x724A:
334 case 0x724B:
335 case 0x724C:
336 case 0x724D:
337 case 0x724E:
338 case 0x724F:
339 case 0x7284:
340 caps->family = CHIP_FAMILY_R580;
341 caps->num_vert_fpus = 8;
342 caps->is_r500 = TRUE;
343 break;
344
345 case 0x7280:
346 caps->family = CHIP_FAMILY_RV570;
347 caps->num_vert_fpus = 5;
348 caps->is_r500 = TRUE;
349 break;
350
351 case 0x7281:
352 case 0x7283:
353 case 0x7287:
354 case 0x7288:
355 case 0x7289:
356 case 0x728B:
357 case 0x728C:
358 case 0x7290:
359 case 0x7291:
360 case 0x7293:
361 case 0x7297:
362 caps->family = CHIP_FAMILY_RV560;
363 caps->num_vert_fpus = 5;
364 caps->is_r500 = TRUE;
365 break;
366
367 default:
368 debug_printf("r300: Warning: Unknown chipset 0x%x\n",
369 caps->pci_id);
370 break;
371 }
372 }