Merge commit 'origin/7.8'
[mesa.git] / src / gallium / drivers / r300 / r300_chipset.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 #include "r300_chipset.h"
24
25 #include "util/u_debug.h"
26
27 #include <stdio.h>
28
29 /* r300_chipset: A file all to itself for deducing the various properties of
30 * Radeons. */
31
32 /* Parse a PCI ID and fill an r300_capabilities struct with information. */
33 void r300_parse_chipset(struct r300_capabilities* caps)
34 {
35 /* Reasonable defaults */
36 caps->num_vert_fpus = 4;
37 caps->num_tex_units = 16;
38 caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;
39 caps->is_r400 = FALSE;
40 caps->is_r500 = FALSE;
41 caps->high_second_pipe = FALSE;
42
43 /* Note: These are not ordered by PCI ID. I leave that task to GCC,
44 * which will perform the ordering while collating jump tables. Instead,
45 * I've tried to group them according to capabilities and age. */
46 switch (caps->pci_id) {
47 case 0x4144:
48 caps->family = CHIP_FAMILY_R300;
49 caps->high_second_pipe = TRUE;
50 break;
51
52 case 0x4145:
53 case 0x4146:
54 case 0x4147:
55 case 0x4E44:
56 case 0x4E45:
57 case 0x4E46:
58 case 0x4E47:
59 caps->family = CHIP_FAMILY_R300;
60 caps->high_second_pipe = TRUE;
61 break;
62
63 case 0x4150:
64 case 0x4151:
65 case 0x4152:
66 case 0x4153:
67 case 0x4154:
68 case 0x4155:
69 case 0x4156:
70 case 0x4E50:
71 case 0x4E51:
72 case 0x4E52:
73 case 0x4E53:
74 case 0x4E54:
75 case 0x4E56:
76 caps->family = CHIP_FAMILY_RV350;
77 caps->high_second_pipe = TRUE;
78 break;
79
80 case 0x4148:
81 case 0x4149:
82 case 0x414A:
83 case 0x414B:
84 case 0x4E48:
85 case 0x4E49:
86 case 0x4E4B:
87 caps->family = CHIP_FAMILY_R350;
88 caps->high_second_pipe = TRUE;
89 break;
90
91 case 0x4E4A:
92 caps->family = CHIP_FAMILY_R360;
93 caps->high_second_pipe = TRUE;
94 break;
95
96 case 0x5460:
97 case 0x5462:
98 case 0x5464:
99 case 0x5B60:
100 case 0x5B62:
101 case 0x5B63:
102 case 0x5B64:
103 case 0x5B65:
104 caps->family = CHIP_FAMILY_RV370;
105 caps->high_second_pipe = TRUE;
106 break;
107
108 case 0x3150:
109 case 0x3152:
110 case 0x3154:
111 case 0x3E50:
112 case 0x3E54:
113 caps->family = CHIP_FAMILY_RV380;
114 caps->high_second_pipe = TRUE;
115 break;
116
117 case 0x4A48:
118 case 0x4A49:
119 case 0x4A4A:
120 case 0x4A4B:
121 case 0x4A4C:
122 case 0x4A4D:
123 case 0x4A4E:
124 case 0x4A4F:
125 case 0x4A50:
126 case 0x4A54:
127 caps->family = CHIP_FAMILY_R420;
128 caps->num_vert_fpus = 6;
129 caps->is_r400 = TRUE;
130 break;
131
132 case 0x5548:
133 case 0x5549:
134 case 0x554A:
135 case 0x554B:
136 case 0x5550:
137 case 0x5551:
138 case 0x5552:
139 case 0x5554:
140 case 0x5D57:
141 caps->family = CHIP_FAMILY_R423;
142 caps->num_vert_fpus = 6;
143 caps->is_r400 = TRUE;
144 break;
145
146 case 0x554C:
147 case 0x554D:
148 case 0x554E:
149 case 0x554F:
150 case 0x5D48:
151 case 0x5D49:
152 case 0x5D4A:
153 caps->family = CHIP_FAMILY_R430;
154 caps->num_vert_fpus = 6;
155 caps->is_r400 = TRUE;
156 break;
157
158 case 0x5D4C:
159 case 0x5D4D:
160 case 0x5D4E:
161 case 0x5D4F:
162 case 0x5D50:
163 case 0x5D52:
164 caps->family = CHIP_FAMILY_R480;
165 caps->num_vert_fpus = 6;
166 caps->is_r400 = TRUE;
167 break;
168
169 case 0x4B48:
170 case 0x4B49:
171 case 0x4B4A:
172 case 0x4B4B:
173 case 0x4B4C:
174 caps->family = CHIP_FAMILY_R481;
175 caps->num_vert_fpus = 6;
176 caps->is_r400 = TRUE;
177 break;
178
179 case 0x5E4C:
180 case 0x5E4F:
181 case 0x564A:
182 case 0x564B:
183 case 0x564F:
184 case 0x5652:
185 case 0x5653:
186 case 0x5657:
187 case 0x5E48:
188 case 0x5E4A:
189 case 0x5E4B:
190 case 0x5E4D:
191 caps->family = CHIP_FAMILY_RV410;
192 caps->num_vert_fpus = 6;
193 caps->is_r400 = TRUE;
194 break;
195
196 case 0x5954:
197 case 0x5955:
198 caps->family = CHIP_FAMILY_RS480;
199 caps->has_tcl = FALSE;
200 break;
201
202 case 0x5974:
203 case 0x5975:
204 caps->family = CHIP_FAMILY_RS482;
205 caps->has_tcl = FALSE;
206 break;
207
208 case 0x5A41:
209 case 0x5A42:
210 caps->family = CHIP_FAMILY_RS400;
211 caps->has_tcl = FALSE;
212 break;
213
214 case 0x5A61:
215 case 0x5A62:
216 caps->family = CHIP_FAMILY_RC410;
217 caps->has_tcl = FALSE;
218 break;
219
220 case 0x791E:
221 case 0x791F:
222 caps->family = CHIP_FAMILY_RS690;
223 caps->has_tcl = FALSE;
224 caps->is_r400 = TRUE;
225 break;
226
227 case 0x793F:
228 case 0x7941:
229 case 0x7942:
230 caps->family = CHIP_FAMILY_RS600;
231 caps->has_tcl = FALSE;
232 caps->is_r400 = TRUE;
233 break;
234
235 case 0x796C:
236 case 0x796D:
237 case 0x796E:
238 case 0x796F:
239 caps->family = CHIP_FAMILY_RS740;
240 caps->has_tcl = FALSE;
241 caps->is_r400 = TRUE;
242 break;
243
244 case 0x7100:
245 case 0x7101:
246 case 0x7102:
247 case 0x7103:
248 case 0x7104:
249 case 0x7105:
250 case 0x7106:
251 case 0x7108:
252 case 0x7109:
253 case 0x710A:
254 case 0x710B:
255 case 0x710C:
256 case 0x710E:
257 case 0x710F:
258 caps->family = CHIP_FAMILY_R520;
259 caps->num_vert_fpus = 8;
260 caps->is_r500 = TRUE;
261 break;
262
263 case 0x7140:
264 case 0x7141:
265 case 0x7142:
266 case 0x7143:
267 case 0x7144:
268 case 0x7145:
269 case 0x7146:
270 case 0x7147:
271 case 0x7149:
272 case 0x714A:
273 case 0x714B:
274 case 0x714C:
275 case 0x714D:
276 case 0x714E:
277 case 0x714F:
278 case 0x7151:
279 case 0x7152:
280 case 0x7153:
281 case 0x715E:
282 case 0x715F:
283 case 0x7180:
284 case 0x7181:
285 case 0x7183:
286 case 0x7186:
287 case 0x7187:
288 case 0x7188:
289 case 0x718A:
290 case 0x718B:
291 case 0x718C:
292 case 0x718D:
293 case 0x718F:
294 case 0x7193:
295 case 0x7196:
296 case 0x719B:
297 case 0x719F:
298 case 0x7200:
299 case 0x7210:
300 case 0x7211:
301 caps->family = CHIP_FAMILY_RV515;
302 caps->num_vert_fpus = 2;
303 caps->is_r500 = TRUE;
304 break;
305
306 case 0x71C0:
307 case 0x71C1:
308 case 0x71C2:
309 case 0x71C3:
310 case 0x71C4:
311 case 0x71C5:
312 case 0x71C6:
313 case 0x71C7:
314 case 0x71CD:
315 case 0x71CE:
316 case 0x71D2:
317 case 0x71D4:
318 case 0x71D5:
319 case 0x71D6:
320 case 0x71DA:
321 case 0x71DE:
322 caps->family = CHIP_FAMILY_RV530;
323 caps->num_vert_fpus = 5;
324 caps->is_r500 = TRUE;
325 break;
326
327 case 0x7240:
328 case 0x7243:
329 case 0x7244:
330 case 0x7245:
331 case 0x7246:
332 case 0x7247:
333 case 0x7248:
334 case 0x7249:
335 case 0x724A:
336 case 0x724B:
337 case 0x724C:
338 case 0x724D:
339 case 0x724E:
340 case 0x724F:
341 case 0x7284:
342 caps->family = CHIP_FAMILY_R580;
343 caps->num_vert_fpus = 8;
344 caps->is_r500 = TRUE;
345 break;
346
347 case 0x7280:
348 caps->family = CHIP_FAMILY_RV570;
349 caps->num_vert_fpus = 5;
350 caps->is_r500 = TRUE;
351 break;
352
353 case 0x7281:
354 case 0x7283:
355 case 0x7287:
356 case 0x7288:
357 case 0x7289:
358 case 0x728B:
359 case 0x728C:
360 case 0x7290:
361 case 0x7291:
362 case 0x7293:
363 case 0x7297:
364 caps->family = CHIP_FAMILY_RV560;
365 caps->num_vert_fpus = 5;
366 caps->is_r500 = TRUE;
367 break;
368
369 default:
370 fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\n",
371 caps->pci_id);
372 }
373 }