Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / gallium / drivers / r300 / r300_emit.c
1 /*
2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
3 * Copyright 2009 Marek Olšák <maraeo@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24 /* r300_emit: Functions for emitting state. */
25
26 #include "util/u_format.h"
27 #include "util/u_math.h"
28 #include "util/u_mm.h"
29 #include "util/u_simple_list.h"
30
31 #include "r300_context.h"
32 #include "r300_cs.h"
33 #include "r300_emit.h"
34 #include "r300_fs.h"
35 #include "r300_screen.h"
36 #include "r300_screen_buffer.h"
37 #include "r300_vs.h"
38
39 void r300_emit_blend_state(struct r300_context* r300,
40 unsigned size, void* state)
41 {
42 struct r300_blend_state* blend = (struct r300_blend_state*)state;
43 struct pipe_framebuffer_state* fb =
44 (struct pipe_framebuffer_state*)r300->fb_state.state;
45 CS_LOCALS(r300);
46
47 if (fb->nr_cbufs) {
48 WRITE_CS_TABLE(blend->cb, size);
49 } else {
50 WRITE_CS_TABLE(blend->cb_no_readwrite, size);
51 }
52 }
53
54 void r300_emit_blend_color_state(struct r300_context* r300,
55 unsigned size, void* state)
56 {
57 struct r300_blend_color_state* bc = (struct r300_blend_color_state*)state;
58 CS_LOCALS(r300);
59
60 WRITE_CS_TABLE(bc->cb, size);
61 }
62
63 void r300_emit_clip_state(struct r300_context* r300,
64 unsigned size, void* state)
65 {
66 struct r300_clip_state* clip = (struct r300_clip_state*)state;
67 CS_LOCALS(r300);
68
69 WRITE_CS_TABLE(clip->cb, size);
70 }
71
72 void r300_emit_dsa_state(struct r300_context* r300, unsigned size, void* state)
73 {
74 struct r300_dsa_state* dsa = (struct r300_dsa_state*)state;
75 struct pipe_framebuffer_state* fb =
76 (struct pipe_framebuffer_state*)r300->fb_state.state;
77 CS_LOCALS(r300);
78
79 if (fb->zsbuf) {
80 WRITE_CS_TABLE(&dsa->cb_begin, size);
81 } else {
82 WRITE_CS_TABLE(dsa->cb_no_readwrite, size);
83 }
84 }
85
86 static const float * get_rc_constant_state(
87 struct r300_context * r300,
88 struct rc_constant * constant)
89 {
90 struct r300_textures_state* texstate = r300->textures_state.state;
91 static float vec[4] = { 0.0, 0.0, 0.0, 1.0 };
92 struct r300_texture *tex;
93
94 assert(constant->Type == RC_CONSTANT_STATE);
95
96 switch (constant->u.State[0]) {
97 /* Factor for converting rectangle coords to
98 * normalized coords. Should only show up on non-r500. */
99 case RC_STATE_R300_TEXRECT_FACTOR:
100 tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
101 vec[0] = 1.0 / tex->desc.width0;
102 vec[1] = 1.0 / tex->desc.height0;
103 break;
104
105 case RC_STATE_R300_TEXSCALE_FACTOR:
106 tex = r300_texture(texstate->sampler_views[constant->u.State[1]]->base.texture);
107 /* Add a small number to the texture size to work around rounding errors in hw. */
108 vec[0] = tex->desc.b.b.width0 / (tex->desc.width0 + 0.001f);
109 vec[1] = tex->desc.b.b.height0 / (tex->desc.height0 + 0.001f);
110 vec[2] = tex->desc.b.b.depth0 / (tex->desc.depth0 + 0.001f);
111 break;
112
113 case RC_STATE_R300_VIEWPORT_SCALE:
114 vec[0] = r300->viewport.scale[0];
115 vec[1] = r300->viewport.scale[1];
116 vec[2] = r300->viewport.scale[2];
117 break;
118
119 case RC_STATE_R300_VIEWPORT_OFFSET:
120 vec[0] = r300->viewport.translate[0];
121 vec[1] = r300->viewport.translate[1];
122 vec[2] = r300->viewport.translate[2];
123 break;
124
125 default:
126 fprintf(stderr, "r300: Implementation error: "
127 "Unknown RC_CONSTANT type %d\n", constant->u.State[0]);
128 }
129
130 /* This should either be (0, 0, 0, 1), which should be a relatively safe
131 * RGBA or STRQ value, or it could be one of the RC_CONSTANT_STATE
132 * state factors. */
133 return vec;
134 }
135
136 /* Convert a normal single-precision float into the 7.16 format
137 * used by the R300 fragment shader.
138 */
139 uint32_t pack_float24(float f)
140 {
141 union {
142 float fl;
143 uint32_t u;
144 } u;
145 float mantissa;
146 int exponent;
147 uint32_t float24 = 0;
148
149 if (f == 0.0)
150 return 0;
151
152 u.fl = f;
153
154 mantissa = frexpf(f, &exponent);
155
156 /* Handle -ve */
157 if (mantissa < 0) {
158 float24 |= (1 << 23);
159 mantissa = mantissa * -1.0;
160 }
161 /* Handle exponent, bias of 63 */
162 exponent += 62;
163 float24 |= (exponent << 16);
164 /* Kill 7 LSB of mantissa */
165 float24 |= (u.u & 0x7FFFFF) >> 7;
166
167 return float24;
168 }
169
170 void r300_emit_fs(struct r300_context* r300, unsigned size, void *state)
171 {
172 struct r300_fragment_shader *fs = r300_fs(r300);
173 CS_LOCALS(r300);
174
175 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
176 }
177
178 void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
179 {
180 struct r300_fragment_shader *fs = r300_fs(r300);
181 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
182 unsigned count = fs->shader->externals_count;
183 unsigned i, j;
184 CS_LOCALS(r300);
185
186 if (count == 0)
187 return;
188
189 BEGIN_CS(size);
190 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
191 if (buf->remap_table){
192 for (i = 0; i < count; i++) {
193 float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
194 for (j = 0; j < 4; j++)
195 OUT_CS(pack_float24(data[j]));
196 }
197 } else {
198 for (i = 0; i < count; i++)
199 for (j = 0; j < 4; j++)
200 OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
201 }
202
203 END_CS;
204 }
205
206 void r300_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
207 {
208 struct r300_fragment_shader *fs = r300_fs(r300);
209 struct rc_constant_list *constants = &fs->shader->code.constants;
210 unsigned i;
211 unsigned count = fs->shader->rc_state_count;
212 unsigned first = fs->shader->externals_count;
213 unsigned end = constants->Count;
214 unsigned j;
215 CS_LOCALS(r300);
216
217 if (count == 0)
218 return;
219
220 BEGIN_CS(size);
221 for(i = first; i < end; ++i) {
222 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
223 const float *data =
224 get_rc_constant_state(r300, &constants->Constants[i]);
225
226 OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X + i * 16, 4);
227 for (j = 0; j < 4; j++)
228 OUT_CS(pack_float24(data[j]));
229 }
230 }
231 END_CS;
232 }
233
234 void r500_emit_fs(struct r300_context* r300, unsigned size, void *state)
235 {
236 struct r300_fragment_shader *fs = r300_fs(r300);
237 CS_LOCALS(r300);
238
239 WRITE_CS_TABLE(fs->shader->cb_code, fs->shader->cb_code_size);
240 }
241
242 void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *state)
243 {
244 struct r300_fragment_shader *fs = r300_fs(r300);
245 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
246 unsigned count = fs->shader->externals_count;
247 CS_LOCALS(r300);
248
249 if (count == 0)
250 return;
251
252 BEGIN_CS(size);
253 OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
254 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
255 if (buf->remap_table){
256 for (unsigned i = 0; i < count; i++) {
257 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
258 OUT_CS_TABLE(data, 4);
259 }
260 } else {
261 OUT_CS_TABLE(buf->ptr, count * 4);
262 }
263 END_CS;
264 }
265
266 void r500_emit_fs_rc_constant_state(struct r300_context* r300, unsigned size, void *state)
267 {
268 struct r300_fragment_shader *fs = r300_fs(r300);
269 struct rc_constant_list *constants = &fs->shader->code.constants;
270 unsigned i;
271 unsigned count = fs->shader->rc_state_count;
272 unsigned first = fs->shader->externals_count;
273 unsigned end = constants->Count;
274 CS_LOCALS(r300);
275
276 if (count == 0)
277 return;
278
279 BEGIN_CS(size);
280 for(i = first; i < end; ++i) {
281 if (constants->Constants[i].Type == RC_CONSTANT_STATE) {
282 const float *data =
283 get_rc_constant_state(r300, &constants->Constants[i]);
284
285 OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
286 R500_GA_US_VECTOR_INDEX_TYPE_CONST |
287 (i & R500_GA_US_VECTOR_INDEX_MASK));
288 OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, 4);
289 OUT_CS_TABLE(data, 4);
290 }
291 }
292 END_CS;
293 }
294
295 void r300_emit_gpu_flush(struct r300_context *r300, unsigned size, void *state)
296 {
297 struct r300_gpu_flush *gpuflush = (struct r300_gpu_flush*)state;
298 struct pipe_framebuffer_state* fb =
299 (struct pipe_framebuffer_state*)r300->fb_state.state;
300 uint32_t height = fb->height;
301 uint32_t width = fb->width;
302 CS_LOCALS(r300);
303
304 if (r300->cbzb_clear) {
305 struct r300_surface *surf = r300_surface(fb->cbufs[0]);
306
307 height = surf->cbzb_height;
308 width = surf->cbzb_width;
309 }
310
311 DBG(r300, DBG_SCISSOR,
312 "r300: Scissor width: %i, height: %i, CBZB clear: %s\n",
313 width, height, r300->cbzb_clear ? "YES" : "NO");
314
315 BEGIN_CS(size);
316
317 /* Set up scissors.
318 * By writing to the SC registers, SC & US assert idle. */
319 OUT_CS_REG_SEQ(R300_SC_SCISSORS_TL, 2);
320 if (r300->screen->caps.is_r500) {
321 OUT_CS(0);
322 OUT_CS(((width - 1) << R300_SCISSORS_X_SHIFT) |
323 ((height - 1) << R300_SCISSORS_Y_SHIFT));
324 } else {
325 OUT_CS((1440 << R300_SCISSORS_X_SHIFT) |
326 (1440 << R300_SCISSORS_Y_SHIFT));
327 OUT_CS(((width + 1440-1) << R300_SCISSORS_X_SHIFT) |
328 ((height + 1440-1) << R300_SCISSORS_Y_SHIFT));
329 }
330
331 /* Flush CB & ZB caches and wait until the 3D engine is idle and clean. */
332 OUT_CS_TABLE(gpuflush->cb_flush_clean, 6);
333 END_CS;
334 }
335
336 void r300_emit_aa_state(struct r300_context *r300, unsigned size, void *state)
337 {
338 struct r300_aa_state *aa = (struct r300_aa_state*)state;
339 CS_LOCALS(r300);
340
341 BEGIN_CS(size);
342 OUT_CS_REG(R300_GB_AA_CONFIG, aa->aa_config);
343
344 if (aa->dest) {
345 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_OFFSET, 1);
346 OUT_CS_RELOC(aa->dest->buffer, aa->dest->offset, 0, aa->dest->domain);
347
348 OUT_CS_REG_SEQ(R300_RB3D_AARESOLVE_PITCH, 1);
349 OUT_CS_RELOC(aa->dest->buffer, aa->dest->pitch, 0, aa->dest->domain);
350 }
351
352 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, aa->aaresolve_ctl);
353 END_CS;
354 }
355
356 void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
357 {
358 struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
359 struct r300_surface* surf;
360 unsigned i;
361 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ);
362 CS_LOCALS(r300);
363
364 BEGIN_CS(size);
365
366 /* NUM_MULTIWRITES replicates COLOR[0] to all colorbuffers, which is not
367 * what we usually want. */
368 if (r300->screen->caps.is_r500) {
369 OUT_CS_REG(R300_RB3D_CCTL,
370 R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE);
371 } else {
372 OUT_CS_REG(R300_RB3D_CCTL, 0);
373 }
374
375 /* Set up colorbuffers. */
376 for (i = 0; i < fb->nr_cbufs; i++) {
377 surf = r300_surface(fb->cbufs[i]);
378
379 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1);
380 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain);
381
382 OUT_CS_REG_SEQ(R300_RB3D_COLORPITCH0 + (4 * i), 1);
383 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain);
384 }
385
386 /* Set up the ZB part of the CBZB clear. */
387 if (r300->cbzb_clear) {
388 surf = r300_surface(fb->cbufs[0]);
389
390 OUT_CS_REG(R300_ZB_FORMAT, surf->cbzb_format);
391
392 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
393 OUT_CS_RELOC(surf->buffer, surf->cbzb_midpoint_offset, 0, surf->domain);
394
395 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
396 OUT_CS_RELOC(surf->buffer, surf->cbzb_pitch, 0, surf->domain);
397
398 DBG(r300, DBG_CBZB,
399 "CBZB clearing cbuf %08x %08x\n", surf->cbzb_format,
400 surf->cbzb_pitch);
401 }
402 /* Set up a zbuffer. */
403 else if (fb->zsbuf) {
404 surf = r300_surface(fb->zsbuf);
405
406 OUT_CS_REG(R300_ZB_FORMAT, surf->format);
407
408 OUT_CS_REG_SEQ(R300_ZB_DEPTHOFFSET, 1);
409 OUT_CS_RELOC(surf->buffer, surf->offset, 0, surf->domain);
410
411 OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
412 OUT_CS_RELOC(surf->buffer, surf->pitch, 0, surf->domain);
413
414 if (can_hyperz) {
415 uint32_t surf_pitch;
416 struct r300_texture *tex;
417 int level = surf->base.level;
418 tex = r300_texture(surf->base.texture);
419
420 surf_pitch = surf->pitch & R300_DEPTHPITCH_MASK;
421 /* HiZ RAM. */
422 if (r300->screen->caps.hiz_ram) {
423 if (tex->hiz_mem[level]) {
424 OUT_CS_REG(R300_ZB_HIZ_OFFSET, tex->hiz_mem[level]->ofs << 2);
425 OUT_CS_REG(R300_ZB_HIZ_PITCH, surf_pitch);
426 } else {
427 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
428 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0);
429 }
430 }
431 /* Z Mask RAM. (compressed zbuffer) */
432 if (tex->zmask_mem[level]) {
433 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, tex->zmask_mem[level]->ofs << 2);
434 OUT_CS_REG(R300_ZB_ZMASK_PITCH, surf_pitch);
435 } else {
436 OUT_CS_REG(R300_ZB_ZMASK_OFFSET, 0);
437 OUT_CS_REG(R300_ZB_ZMASK_PITCH, 0);
438 }
439 }
440 }
441
442 END_CS;
443 }
444
445 void r300_emit_hyperz_state(struct r300_context *r300,
446 unsigned size, void *state)
447 {
448 struct r300_hyperz_state *z = state;
449 CS_LOCALS(r300);
450 if (z->flush)
451 WRITE_CS_TABLE(&z->cb_flush_begin, size);
452 else
453 WRITE_CS_TABLE(&z->cb_begin, size - 2);
454 }
455
456 void r300_emit_hyperz_end(struct r300_context *r300)
457 {
458 struct r300_hyperz_state z =
459 *(struct r300_hyperz_state*)r300->hyperz_state.state;
460
461 z.flush = 1;
462 z.zb_bw_cntl = 0;
463 z.zb_depthclearvalue = 0;
464 z.sc_hyperz = R300_SC_HYPERZ_ADJ_2;
465 z.gb_z_peq_config = 0;
466
467 r300_emit_hyperz_state(r300, r300->hyperz_state.size, &z);
468 }
469
470 void r300_emit_fb_state_pipelined(struct r300_context *r300,
471 unsigned size, void *state)
472 {
473 struct pipe_framebuffer_state* fb =
474 (struct pipe_framebuffer_state*)r300->fb_state.state;
475 unsigned i;
476 CS_LOCALS(r300);
477
478 BEGIN_CS(size);
479
480 /* Colorbuffer format in the US block.
481 * (must be written after unpipelined regs) */
482 OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
483 for (i = 0; i < fb->nr_cbufs; i++) {
484 OUT_CS(r300_surface(fb->cbufs[i])->format);
485 }
486 for (; i < 4; i++) {
487 OUT_CS(R300_US_OUT_FMT_UNUSED);
488 }
489
490 /* Multisampling. Depends on framebuffer sample count.
491 * These are pipelined regs and as such cannot be moved
492 * to the AA state. */
493 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) {
494 unsigned mspos0 = 0x66666666;
495 unsigned mspos1 = 0x6666666;
496
497 if (fb->nr_cbufs && fb->cbufs[0]->texture->nr_samples > 1) {
498 /* Subsample placement. These may not be optimal. */
499 switch (fb->cbufs[0]->texture->nr_samples) {
500 case 2:
501 mspos0 = 0x33996633;
502 mspos1 = 0x6666663;
503 break;
504 case 3:
505 mspos0 = 0x33936933;
506 mspos1 = 0x6666663;
507 break;
508 case 4:
509 mspos0 = 0x33939933;
510 mspos1 = 0x3966663;
511 break;
512 case 6:
513 mspos0 = 0x22a2aa22;
514 mspos1 = 0x2a65672;
515 break;
516 default:
517 debug_printf("r300: Bad number of multisamples!\n");
518 }
519 }
520
521 OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2);
522 OUT_CS(mspos0);
523 OUT_CS(mspos1);
524 }
525 END_CS;
526 }
527
528 void r300_emit_query_start(struct r300_context *r300, unsigned size, void*state)
529 {
530 struct r300_query *query = r300->query_current;
531 CS_LOCALS(r300);
532
533 if (!query)
534 return;
535
536 BEGIN_CS(size);
537 if (r300->screen->caps.family == CHIP_FAMILY_RV530) {
538 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
539 } else {
540 OUT_CS_REG(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
541 }
542 OUT_CS_REG(R300_ZB_ZPASS_DATA, 0);
543 END_CS;
544 query->begin_emitted = TRUE;
545 query->flushed = FALSE;
546 }
547
548 static void r300_emit_query_end_frag_pipes(struct r300_context *r300,
549 struct r300_query *query)
550 {
551 struct r300_capabilities* caps = &r300->screen->caps;
552 struct r300_winsys_buffer *buf = r300->query_current->buffer;
553 CS_LOCALS(r300);
554
555 assert(caps->num_frag_pipes);
556
557 BEGIN_CS(6 * caps->num_frag_pipes + 2);
558 /* I'm not so sure I like this switch, but it's hard to be elegant
559 * when there's so many special cases...
560 *
561 * So here's the basic idea. For each pipe, enable writes to it only,
562 * then put out the relocation for ZPASS_ADDR, taking into account a
563 * 4-byte offset for each pipe. RV380 and older are special; they have
564 * only two pipes, and the second pipe's enable is on bit 3, not bit 1,
565 * so there's a chipset cap for that. */
566 switch (caps->num_frag_pipes) {
567 case 4:
568 /* pipe 3 only */
569 OUT_CS_REG(R300_SU_REG_DEST, 1 << 3);
570 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
571 OUT_CS_RELOC(buf, (query->num_results + 3) * 4,
572 0, query->domain);
573 case 3:
574 /* pipe 2 only */
575 OUT_CS_REG(R300_SU_REG_DEST, 1 << 2);
576 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
577 OUT_CS_RELOC(buf, (query->num_results + 2) * 4,
578 0, query->domain);
579 case 2:
580 /* pipe 1 only */
581 /* As mentioned above, accomodate RV380 and older. */
582 OUT_CS_REG(R300_SU_REG_DEST,
583 1 << (caps->high_second_pipe ? 3 : 1));
584 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
585 OUT_CS_RELOC(buf, (query->num_results + 1) * 4,
586 0, query->domain);
587 case 1:
588 /* pipe 0 only */
589 OUT_CS_REG(R300_SU_REG_DEST, 1 << 0);
590 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
591 OUT_CS_RELOC(buf, (query->num_results + 0) * 4,
592 0, query->domain);
593 break;
594 default:
595 fprintf(stderr, "r300: Implementation error: Chipset reports %d"
596 " pixel pipes!\n", caps->num_frag_pipes);
597 abort();
598 }
599
600 /* And, finally, reset it to normal... */
601 OUT_CS_REG(R300_SU_REG_DEST, 0xF);
602 END_CS;
603 }
604
605 static void rv530_emit_query_end_single_z(struct r300_context *r300,
606 struct r300_query *query)
607 {
608 struct r300_winsys_buffer *buf = r300->query_current->buffer;
609 CS_LOCALS(r300);
610
611 BEGIN_CS(8);
612 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
613 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
614 OUT_CS_RELOC(buf, query->num_results * 4, 0, query->domain);
615 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
616 END_CS;
617 }
618
619 static void rv530_emit_query_end_double_z(struct r300_context *r300,
620 struct r300_query *query)
621 {
622 struct r300_winsys_buffer *buf = r300->query_current->buffer;
623 CS_LOCALS(r300);
624
625 BEGIN_CS(14);
626 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
627 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
628 OUT_CS_RELOC(buf, (query->num_results + 0) * 4, 0, query->domain);
629 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
630 OUT_CS_REG_SEQ(R300_ZB_ZPASS_ADDR, 1);
631 OUT_CS_RELOC(buf, (query->num_results + 1) * 4, 0, query->domain);
632 OUT_CS_REG(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
633 END_CS;
634 }
635
636 void r300_emit_query_end(struct r300_context* r300)
637 {
638 struct r300_capabilities *caps = &r300->screen->caps;
639 struct r300_query *query = r300->query_current;
640
641 if (!query)
642 return;
643
644 if (query->begin_emitted == FALSE)
645 return;
646
647 if (caps->family == CHIP_FAMILY_RV530) {
648 if (caps->num_z_pipes == 2)
649 rv530_emit_query_end_double_z(r300, query);
650 else
651 rv530_emit_query_end_single_z(r300, query);
652 } else
653 r300_emit_query_end_frag_pipes(r300, query);
654
655 query->begin_emitted = FALSE;
656 query->num_results += query->num_pipes;
657
658 /* XXX grab all the results and reset the counter. */
659 if (query->num_results >= query->buffer_size / 4 - 4) {
660 query->num_results = (query->buffer_size / 4) / 2;
661 fprintf(stderr, "r300: Rewinding OQBO...\n");
662 }
663 }
664
665 void r300_emit_invariant_state(struct r300_context *r300,
666 unsigned size, void *state)
667 {
668 CS_LOCALS(r300);
669 WRITE_CS_TABLE(state, size);
670 }
671
672 void r300_emit_rs_state(struct r300_context* r300, unsigned size, void* state)
673 {
674 struct r300_rs_state* rs = state;
675 CS_LOCALS(r300);
676
677 BEGIN_CS(size);
678 OUT_CS_TABLE(rs->cb_main, RS_STATE_MAIN_SIZE);
679 if (rs->polygon_offset_enable) {
680 if (r300->zbuffer_bpp == 16) {
681 OUT_CS_TABLE(rs->cb_poly_offset_zb16, 5);
682 } else {
683 OUT_CS_TABLE(rs->cb_poly_offset_zb24, 5);
684 }
685 }
686 END_CS;
687 }
688
689 void r300_emit_rs_block_state(struct r300_context* r300,
690 unsigned size, void* state)
691 {
692 struct r300_rs_block* rs = (struct r300_rs_block*)state;
693 unsigned i;
694 /* It's the same for both INST and IP tables */
695 unsigned count = (rs->inst_count & R300_RS_INST_COUNT_MASK) + 1;
696 CS_LOCALS(r300);
697
698 if (DBG_ON(r300, DBG_RS_BLOCK)) {
699 r500_dump_rs_block(rs);
700
701 fprintf(stderr, "r300: RS emit:\n");
702
703 for (i = 0; i < count; i++)
704 fprintf(stderr, " : ip %d: 0x%08x\n", i, rs->ip[i]);
705
706 for (i = 0; i < count; i++)
707 fprintf(stderr, " : inst %d: 0x%08x\n", i, rs->inst[i]);
708
709 fprintf(stderr, " : count: 0x%08x inst_count: 0x%08x\n",
710 rs->count, rs->inst_count);
711 }
712
713 BEGIN_CS(size);
714 OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2);
715 OUT_CS(rs->vap_vtx_state_cntl);
716 OUT_CS(rs->vap_vsm_vtx_assm);
717 OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
718 OUT_CS(rs->vap_out_vtx_fmt[0]);
719 OUT_CS(rs->vap_out_vtx_fmt[1]);
720 OUT_CS_REG_SEQ(R300_GB_ENABLE, 1);
721 OUT_CS(rs->gb_enable);
722
723 if (r300->screen->caps.is_r500) {
724 OUT_CS_REG_SEQ(R500_RS_IP_0, count);
725 } else {
726 OUT_CS_REG_SEQ(R300_RS_IP_0, count);
727 }
728 OUT_CS_TABLE(rs->ip, count);
729
730 OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
731 OUT_CS(rs->count);
732 OUT_CS(rs->inst_count);
733
734 if (r300->screen->caps.is_r500) {
735 OUT_CS_REG_SEQ(R500_RS_INST_0, count);
736 } else {
737 OUT_CS_REG_SEQ(R300_RS_INST_0, count);
738 }
739 OUT_CS_TABLE(rs->inst, count);
740 END_CS;
741 }
742
743 void r300_emit_scissor_state(struct r300_context* r300,
744 unsigned size, void* state)
745 {
746 struct pipe_scissor_state* scissor = (struct pipe_scissor_state*)state;
747 CS_LOCALS(r300);
748
749 BEGIN_CS(size);
750 OUT_CS_REG_SEQ(R300_SC_CLIPRECT_TL_0, 2);
751 if (r300->screen->caps.is_r500) {
752 OUT_CS((scissor->minx << R300_CLIPRECT_X_SHIFT) |
753 (scissor->miny << R300_CLIPRECT_Y_SHIFT));
754 OUT_CS(((scissor->maxx - 1) << R300_CLIPRECT_X_SHIFT) |
755 ((scissor->maxy - 1) << R300_CLIPRECT_Y_SHIFT));
756 } else {
757 OUT_CS(((scissor->minx + 1440) << R300_CLIPRECT_X_SHIFT) |
758 ((scissor->miny + 1440) << R300_CLIPRECT_Y_SHIFT));
759 OUT_CS(((scissor->maxx + 1440-1) << R300_CLIPRECT_X_SHIFT) |
760 ((scissor->maxy + 1440-1) << R300_CLIPRECT_Y_SHIFT));
761 }
762 END_CS;
763 }
764
765 void r300_emit_textures_state(struct r300_context *r300,
766 unsigned size, void *state)
767 {
768 struct r300_textures_state *allstate = (struct r300_textures_state*)state;
769 struct r300_texture_sampler_state *texstate;
770 struct r300_texture *tex;
771 unsigned i;
772 CS_LOCALS(r300);
773
774 BEGIN_CS(size);
775 OUT_CS_REG(R300_TX_ENABLE, allstate->tx_enable);
776
777 for (i = 0; i < allstate->count; i++) {
778 if ((1 << i) & allstate->tx_enable) {
779 texstate = &allstate->regs[i];
780 tex = r300_texture(allstate->sampler_views[i]->base.texture);
781
782 OUT_CS_REG(R300_TX_FILTER0_0 + (i * 4), texstate->filter0);
783 OUT_CS_REG(R300_TX_FILTER1_0 + (i * 4), texstate->filter1);
784 OUT_CS_REG(R300_TX_BORDER_COLOR_0 + (i * 4),
785 texstate->border_color);
786
787 OUT_CS_REG(R300_TX_FORMAT0_0 + (i * 4), texstate->format.format0);
788 OUT_CS_REG(R300_TX_FORMAT1_0 + (i * 4), texstate->format.format1);
789 OUT_CS_REG(R300_TX_FORMAT2_0 + (i * 4), texstate->format.format2);
790
791 OUT_CS_REG_SEQ(R300_TX_OFFSET_0 + (i * 4), 1);
792 OUT_CS_TEX_RELOC(tex, texstate->format.tile_config, tex->domain,
793 0);
794 }
795 }
796 END_CS;
797 }
798
799 void r300_emit_aos(struct r300_context* r300, int offset, boolean indexed)
800 {
801 struct pipe_vertex_buffer *vb1, *vb2, *vbuf = r300->vertex_buffer;
802 struct pipe_vertex_element *velem = r300->velems->velem;
803 struct r300_buffer *buf;
804 int i;
805 unsigned *hw_format_size = r300->velems->hw_format_size;
806 unsigned size1, size2, aos_count = r300->velems->count;
807 unsigned packet_size = (aos_count * 3 + 1) / 2;
808 CS_LOCALS(r300);
809
810 BEGIN_CS(2 + packet_size + aos_count * 2);
811 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, packet_size);
812 OUT_CS(aos_count | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
813
814 for (i = 0; i < aos_count - 1; i += 2) {
815 vb1 = &vbuf[velem[i].vertex_buffer_index];
816 vb2 = &vbuf[velem[i+1].vertex_buffer_index];
817 size1 = hw_format_size[i];
818 size2 = hw_format_size[i+1];
819
820 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride) |
821 R300_VBPNTR_SIZE1(size2) | R300_VBPNTR_STRIDE1(vb2->stride));
822 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
823 OUT_CS(vb2->buffer_offset + velem[i+1].src_offset + offset * vb2->stride);
824 }
825
826 if (aos_count & 1) {
827 vb1 = &vbuf[velem[i].vertex_buffer_index];
828 size1 = hw_format_size[i];
829
830 OUT_CS(R300_VBPNTR_SIZE0(size1) | R300_VBPNTR_STRIDE0(vb1->stride));
831 OUT_CS(vb1->buffer_offset + velem[i].src_offset + offset * vb1->stride);
832 }
833
834 for (i = 0; i < aos_count; i++) {
835 buf = r300_buffer(vbuf[velem[i].vertex_buffer_index].buffer);
836 OUT_CS_BUF_RELOC_NO_OFFSET(&buf->b.b, buf->domain, 0);
837 }
838 END_CS;
839 }
840
841 void r300_emit_aos_swtcl(struct r300_context *r300, boolean indexed)
842 {
843 CS_LOCALS(r300);
844
845 DBG(r300, DBG_SWTCL, "r300: Preparing vertex buffer %p for render, "
846 "vertex size %d\n", r300->vbo,
847 r300->vertex_info.size);
848 /* Set the pointer to our vertex buffer. The emitted values are this:
849 * PACKET3 [3D_LOAD_VBPNTR]
850 * COUNT [1]
851 * FORMAT [size | stride << 8]
852 * OFFSET [offset into BO]
853 * VBPNTR [relocated BO]
854 */
855 BEGIN_CS(7);
856 OUT_CS_PKT3(R300_PACKET3_3D_LOAD_VBPNTR, 3);
857 OUT_CS(1 | (!indexed ? R300_VC_FORCE_PREFETCH : 0));
858 OUT_CS(r300->vertex_info.size |
859 (r300->vertex_info.size << 8));
860 OUT_CS(r300->draw_vbo_offset);
861 OUT_CS_BUF_RELOC(r300->vbo, 0, r300_buffer(r300->vbo)->domain, 0);
862 END_CS;
863 }
864
865 void r300_emit_vertex_stream_state(struct r300_context* r300,
866 unsigned size, void* state)
867 {
868 struct r300_vertex_stream_state *streams =
869 (struct r300_vertex_stream_state*)state;
870 unsigned i;
871 CS_LOCALS(r300);
872
873 if (DBG_ON(r300, DBG_PSC)) {
874 fprintf(stderr, "r300: PSC emit:\n");
875
876 for (i = 0; i < streams->count; i++) {
877 fprintf(stderr, " : prog_stream_cntl%d: 0x%08x\n", i,
878 streams->vap_prog_stream_cntl[i]);
879 }
880
881 for (i = 0; i < streams->count; i++) {
882 fprintf(stderr, " : prog_stream_cntl_ext%d: 0x%08x\n", i,
883 streams->vap_prog_stream_cntl_ext[i]);
884 }
885 }
886
887 BEGIN_CS(size);
888 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, streams->count);
889 OUT_CS_TABLE(streams->vap_prog_stream_cntl, streams->count);
890 OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_EXT_0, streams->count);
891 OUT_CS_TABLE(streams->vap_prog_stream_cntl_ext, streams->count);
892 END_CS;
893 }
894
895 void r300_emit_pvs_flush(struct r300_context* r300, unsigned size, void* state)
896 {
897 CS_LOCALS(r300);
898
899 BEGIN_CS(size);
900 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
901 END_CS;
902 }
903
904 void r300_emit_vap_invariant_state(struct r300_context *r300,
905 unsigned size, void *state)
906 {
907 CS_LOCALS(r300);
908 WRITE_CS_TABLE(state, size);
909 }
910
911 void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
912 {
913 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)state;
914 struct r300_vertex_program_code* code = &vs->code;
915 struct r300_screen* r300screen = r300->screen;
916 unsigned instruction_count = code->length / 4;
917 unsigned i;
918
919 unsigned vtx_mem_size = r300screen->caps.is_r500 ? 128 : 72;
920 unsigned input_count = MAX2(util_bitcount(code->InputsRead), 1);
921 unsigned output_count = MAX2(util_bitcount(code->OutputsWritten), 1);
922 unsigned temp_count = MAX2(code->num_temporaries, 1);
923
924 unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
925 vtx_mem_size / output_count, 10);
926 unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
927
928 unsigned imm_first = vs->externals_count;
929 unsigned imm_end = vs->code.constants.Count;
930 unsigned imm_count = vs->immediates_count;
931
932 CS_LOCALS(r300);
933
934 BEGIN_CS(size);
935
936 /* R300_VAP_PVS_CODE_CNTL_0
937 * R300_VAP_PVS_CONST_CNTL
938 * R300_VAP_PVS_CODE_CNTL_1
939 * See the r5xx docs for instructions on how to use these. */
940 OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
941 OUT_CS(R300_PVS_FIRST_INST(0) |
942 R300_PVS_XYZW_VALID_INST(instruction_count - 1) |
943 R300_PVS_LAST_INST(instruction_count - 1));
944 OUT_CS(R300_PVS_MAX_CONST_ADDR(code->constants.Count - 1));
945 OUT_CS(instruction_count - 1);
946
947 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
948 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, code->length);
949 OUT_CS_TABLE(code->body.d, code->length);
950
951 OUT_CS_REG(R300_VAP_CNTL, R300_PVS_NUM_SLOTS(pvs_num_slots) |
952 R300_PVS_NUM_CNTLRS(pvs_num_controllers) |
953 R300_PVS_NUM_FPUS(r300screen->caps.num_vert_fpus) |
954 R300_PVS_VF_MAX_VTX_NUM(12) |
955 (r300screen->caps.is_r500 ? R500_TCL_STATE_OPTIMIZATION : 0));
956
957 /* Emit immediates. */
958 if (imm_count) {
959 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
960 (r300->screen->caps.is_r500 ?
961 R500_PVS_CONST_START : R300_PVS_CONST_START) +
962 imm_first);
963 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, imm_count * 4);
964 for (i = imm_first; i < imm_end; i++) {
965 const float *data = vs->code.constants.Constants[i].u.Immediate;
966 OUT_CS_TABLE(data, 4);
967 }
968 }
969
970 /* Emit flow control instructions. */
971 if (code->num_fc_ops) {
972
973 OUT_CS_REG(R300_VAP_PVS_FLOW_CNTL_OPC, code->fc_ops);
974 if (r300screen->caps.is_r500) {
975 OUT_CS_REG_SEQ(R500_VAP_PVS_FLOW_CNTL_ADDRS_LW_0, code->num_fc_ops * 2);
976 OUT_CS_TABLE(code->fc_op_addrs.r500, code->num_fc_ops * 2);
977 } else {
978 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_ADDRS_0, code->num_fc_ops);
979 OUT_CS_TABLE(code->fc_op_addrs.r300, code->num_fc_ops);
980 }
981 OUT_CS_REG_SEQ(R300_VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, code->num_fc_ops);
982 OUT_CS_TABLE(code->fc_loop_index, code->num_fc_ops);
983 }
984
985 END_CS;
986 }
987
988 void r300_emit_vs_constants(struct r300_context* r300,
989 unsigned size, void *state)
990 {
991 unsigned count =
992 ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
993 struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
994 unsigned i;
995 CS_LOCALS(r300);
996
997 if (!count)
998 return;
999
1000 BEGIN_CS(size);
1001 OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG,
1002 (r300->screen->caps.is_r500 ?
1003 R500_PVS_CONST_START : R300_PVS_CONST_START));
1004 OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
1005 if (buf->remap_table){
1006 for (i = 0; i < count; i++) {
1007 uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
1008 OUT_CS_TABLE(data, 4);
1009 }
1010 } else {
1011 OUT_CS_TABLE(buf->ptr, count * 4);
1012 }
1013 END_CS;
1014 }
1015
1016 void r300_emit_viewport_state(struct r300_context* r300,
1017 unsigned size, void* state)
1018 {
1019 struct r300_viewport_state* viewport = (struct r300_viewport_state*)state;
1020 CS_LOCALS(r300);
1021
1022 BEGIN_CS(size);
1023 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
1024 OUT_CS_TABLE(&viewport->xscale, 6);
1025 OUT_CS_REG(R300_VAP_VTE_CNTL, viewport->vte_control);
1026 END_CS;
1027 }
1028
1029 static void r300_emit_hiz_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1030 {
1031 CS_LOCALS(r300);
1032 BEGIN_CS(4);
1033 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_HIZ, 2);
1034 OUT_CS(start);
1035 OUT_CS(count);
1036 OUT_CS(val);
1037 END_CS;
1038 }
1039
1040 static void r300_emit_zmask_line_clear(struct r300_context *r300, int start, uint16_t count, uint32_t val)
1041 {
1042 CS_LOCALS(r300);
1043 BEGIN_CS(4);
1044 OUT_CS_PKT3(R300_PACKET3_3D_CLEAR_ZMASK, 2);
1045 OUT_CS(start);
1046 OUT_CS(count);
1047 OUT_CS(val);
1048 END_CS;
1049 }
1050
1051 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
1052
1053 void r300_emit_hiz_clear(struct r300_context *r300, unsigned size, void *state)
1054 {
1055 struct pipe_framebuffer_state *fb =
1056 (struct pipe_framebuffer_state*)r300->fb_state.state;
1057 struct r300_hyperz_state *z =
1058 (struct r300_hyperz_state*)r300->hyperz_state.state;
1059 struct r300_screen* r300screen = r300->screen;
1060 uint32_t stride, offset = 0, height, offset_shift;
1061 struct r300_texture* tex;
1062 int i;
1063
1064 tex = r300_texture(fb->zsbuf->texture);
1065
1066 offset = tex->hiz_mem[fb->zsbuf->level]->ofs;
1067 stride = tex->desc.stride_in_pixels[fb->zsbuf->level];
1068
1069 /* convert from pixels to 4x4 blocks */
1070 stride = ALIGN_DIVUP(stride, 4);
1071
1072 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1073 /* there are 4 blocks per dwords */
1074 stride = ALIGN_DIVUP(stride, 4);
1075
1076 height = ALIGN_DIVUP(fb->zsbuf->height, 4);
1077
1078 offset_shift = 2;
1079 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1080
1081 for (i = 0; i < height; i++) {
1082 offset = i * stride;
1083 offset <<= offset_shift;
1084 r300_emit_hiz_line_clear(r300, offset, stride, 0xffffffff);
1085 }
1086 z->current_func = -1;
1087
1088 /* Mark the current zbuffer's hiz ram as in use. */
1089 tex->hiz_in_use[fb->zsbuf->level] = TRUE;
1090 }
1091
1092 void r300_emit_zmask_clear(struct r300_context *r300, unsigned size, void *state)
1093 {
1094 struct pipe_framebuffer_state *fb =
1095 (struct pipe_framebuffer_state*)r300->fb_state.state;
1096 struct r300_screen* r300screen = r300->screen;
1097 uint32_t stride, offset = 0;
1098 struct r300_texture* tex;
1099 uint32_t i, height;
1100 int mult, offset_shift;
1101
1102 tex = r300_texture(fb->zsbuf->texture);
1103 stride = tex->desc.stride_in_pixels[fb->zsbuf->level];
1104
1105 offset = tex->zmask_mem[fb->zsbuf->level]->ofs;
1106
1107 if (r300->z_compression == RV350_Z_COMPRESS_88)
1108 mult = 8;
1109 else
1110 mult = 4;
1111
1112 height = ALIGN_DIVUP(fb->zsbuf->height, mult);
1113
1114 offset_shift = 4;
1115 offset_shift += (r300screen->caps.num_frag_pipes / 2);
1116 stride = ALIGN_DIVUP(stride, r300screen->caps.num_frag_pipes);
1117
1118 /* okay have width in pixels - divide by block width */
1119 stride = ALIGN_DIVUP(stride, mult);
1120 /* have width in blocks - divide by number of fragment pipes screen width */
1121 /* 16 blocks per dword */
1122 stride = ALIGN_DIVUP(stride, 16);
1123
1124 for (i = 0; i < height; i++) {
1125 offset = i * stride;
1126 offset <<= offset_shift;
1127 r300_emit_zmask_line_clear(r300, offset, stride, 0x0);//0xffffffff);
1128 }
1129
1130 /* Mark the current zbuffer's zmask as in use. */
1131 tex->zmask_in_use[fb->zsbuf->level] = TRUE;
1132 }
1133
1134 void r300_emit_ztop_state(struct r300_context* r300,
1135 unsigned size, void* state)
1136 {
1137 struct r300_ztop_state* ztop = (struct r300_ztop_state*)state;
1138 CS_LOCALS(r300);
1139
1140 BEGIN_CS(size);
1141 OUT_CS_REG(R300_ZB_ZTOP, ztop->z_buffer_top);
1142 END_CS;
1143 }
1144
1145 void r300_emit_texture_cache_inval(struct r300_context* r300, unsigned size, void* state)
1146 {
1147 CS_LOCALS(r300);
1148
1149 BEGIN_CS(size);
1150 OUT_CS_REG(R300_TX_INVALTAGS, 0);
1151 END_CS;
1152 }
1153
1154 boolean r300_emit_buffer_validate(struct r300_context *r300,
1155 boolean do_validate_vertex_buffers,
1156 struct pipe_resource *index_buffer)
1157 {
1158 struct pipe_framebuffer_state* fb =
1159 (struct pipe_framebuffer_state*)r300->fb_state.state;
1160 struct r300_textures_state *texstate =
1161 (struct r300_textures_state*)r300->textures_state.state;
1162 struct r300_texture* tex;
1163 struct pipe_vertex_buffer *vbuf = r300->vertex_buffer;
1164 struct pipe_vertex_element *velem = r300->velems->velem;
1165 struct pipe_resource *pbuf;
1166 unsigned i;
1167
1168 /* upload buffers first */
1169 if (r300->screen->caps.has_tcl && r300->any_user_vbs) {
1170 r300_upload_user_buffers(r300);
1171 r300->any_user_vbs = false;
1172 }
1173
1174 /* Clean out BOs. */
1175 r300->rws->cs_reset_buffers(r300->cs);
1176
1177 /* Color buffers... */
1178 for (i = 0; i < fb->nr_cbufs; i++) {
1179 tex = r300_texture(fb->cbufs[i]->texture);
1180 assert(tex && tex->buffer && "cbuf is marked, but NULL!");
1181 r300->rws->cs_add_buffer(r300->cs, tex->buffer, 0,
1182 r300_surface(fb->cbufs[i])->domain);
1183 }
1184 /* ...depth buffer... */
1185 if (fb->zsbuf) {
1186 tex = r300_texture(fb->zsbuf->texture);
1187 assert(tex && tex->buffer && "zsbuf is marked, but NULL!");
1188 r300->rws->cs_add_buffer(r300->cs, tex->buffer, 0,
1189 r300_surface(fb->zsbuf)->domain);
1190 }
1191 /* ...textures... */
1192 for (i = 0; i < texstate->count; i++) {
1193 if (!(texstate->tx_enable & (1 << i))) {
1194 continue;
1195 }
1196
1197 tex = r300_texture(texstate->sampler_views[i]->base.texture);
1198 r300->rws->cs_add_buffer(r300->cs, tex->buffer, tex->domain, 0);
1199 }
1200 /* ...occlusion query buffer... */
1201 if (r300->query_current)
1202 r300->rws->cs_add_buffer(r300->cs, r300->query_current->buffer,
1203 0, r300->query_current->domain);
1204 /* ...vertex buffer for SWTCL path... */
1205 if (r300->vbo)
1206 r300->rws->cs_add_buffer(r300->cs, r300_buffer(r300->vbo)->buf,
1207 r300_buffer(r300->vbo)->domain, 0);
1208 /* ...vertex buffers for HWTCL path... */
1209 if (do_validate_vertex_buffers) {
1210 for (i = 0; i < r300->velems->count; i++) {
1211 pbuf = vbuf[velem[i].vertex_buffer_index].buffer;
1212
1213 r300->rws->cs_add_buffer(r300->cs, r300_buffer(pbuf)->buf,
1214 r300_buffer(pbuf)->domain, 0);
1215 }
1216 }
1217 /* ...and index buffer for HWTCL path. */
1218 if (index_buffer)
1219 r300->rws->cs_add_buffer(r300->cs, r300_buffer(index_buffer)->buf,
1220 r300_buffer(index_buffer)->domain, 0);
1221
1222 if (!r300->rws->cs_validate(r300->cs)) {
1223 return FALSE;
1224 }
1225
1226 return TRUE;
1227 }
1228
1229 unsigned r300_get_num_dirty_dwords(struct r300_context *r300)
1230 {
1231 struct r300_atom* atom;
1232 unsigned dwords = 0;
1233
1234 foreach(atom, &r300->atom_list) {
1235 if (atom->dirty) {
1236 dwords += atom->size;
1237 }
1238 }
1239
1240 /* let's reserve some more, just in case */
1241 dwords += 32;
1242
1243 return dwords;
1244 }
1245
1246 unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
1247 {
1248 unsigned dwords = 0;
1249
1250 /* Emitted in flush. */
1251 dwords += 26; /* emit_query_end */
1252 dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
1253 if (r500_index_bias_supported(r300))
1254 dwords += 2;
1255
1256 return dwords;
1257 }
1258
1259 /* Emit all dirty state. */
1260 void r300_emit_dirty_state(struct r300_context* r300)
1261 {
1262 struct r300_atom* atom;
1263
1264 foreach(atom, &r300->atom_list) {
1265 if (atom->dirty) {
1266 atom->emit(r300, atom->size, atom->state);
1267 if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
1268 atom->counter++;
1269 }
1270 atom->dirty = FALSE;
1271 }
1272 }
1273
1274 r300->dirty_hw++;
1275 }