Merge branch '7.8'
[mesa.git] / src / gallium / drivers / r300 / r300_render.c
1 /*
2 * Copyright 2009 Corbin Simpson <MostAwesomeDude@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE. */
22
23 /* r300_render: Vertex and index buffer primitive emission. Contains both
24 * HW TCL fastpath rendering, and SW TCL Draw-assisted rendering. */
25
26 #include "draw/draw_context.h"
27 #include "draw/draw_vbuf.h"
28
29 #include "util/u_inlines.h"
30
31 #include "util/u_format.h"
32 #include "util/u_memory.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35
36 #include "r300_cs.h"
37 #include "r300_context.h"
38 #include "r300_screen_buffer.h"
39 #include "r300_emit.h"
40 #include "r300_reg.h"
41 #include "r300_render.h"
42 #include "r300_state_derived.h"
43
44 /* XXX The DRM rejects VAP_ALT_NUM_VERTICES.. */
45 //#define ENABLE_ALT_NUM_VERTS
46
47 uint32_t r300_translate_primitive(unsigned prim)
48 {
49 switch (prim) {
50 case PIPE_PRIM_POINTS:
51 return R300_VAP_VF_CNTL__PRIM_POINTS;
52 case PIPE_PRIM_LINES:
53 return R300_VAP_VF_CNTL__PRIM_LINES;
54 case PIPE_PRIM_LINE_LOOP:
55 return R300_VAP_VF_CNTL__PRIM_LINE_LOOP;
56 case PIPE_PRIM_LINE_STRIP:
57 return R300_VAP_VF_CNTL__PRIM_LINE_STRIP;
58 case PIPE_PRIM_TRIANGLES:
59 return R300_VAP_VF_CNTL__PRIM_TRIANGLES;
60 case PIPE_PRIM_TRIANGLE_STRIP:
61 return R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP;
62 case PIPE_PRIM_TRIANGLE_FAN:
63 return R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN;
64 case PIPE_PRIM_QUADS:
65 return R300_VAP_VF_CNTL__PRIM_QUADS;
66 case PIPE_PRIM_QUAD_STRIP:
67 return R300_VAP_VF_CNTL__PRIM_QUAD_STRIP;
68 case PIPE_PRIM_POLYGON:
69 return R300_VAP_VF_CNTL__PRIM_POLYGON;
70 default:
71 return 0;
72 }
73 }
74
75 static uint32_t r300_provoking_vertex_fixes(struct r300_context *r300,
76 unsigned mode)
77 {
78 struct r300_rs_state* rs = (struct r300_rs_state*)r300->rs_state.state;
79 uint32_t color_control = rs->color_control;
80
81 /* By default (see r300_state.c:r300_create_rs_state) color_control is
82 * initialized to provoking the first vertex.
83 *
84 * Triangle fans must be reduced to the second vertex, not the first, in
85 * Gallium flatshade-first mode, as per the GL spec.
86 * (http://www.opengl.org/registry/specs/ARB/provoking_vertex.txt)
87 *
88 * Quads never provoke correctly in flatshade-first mode. The first
89 * vertex is never considered as provoking, so only the second, third,
90 * and fourth vertices can be selected, and both "third" and "last" modes
91 * select the fourth vertex. This is probably due to D3D lacking quads.
92 *
93 * Similarly, polygons reduce to the first, not the last, vertex, when in
94 * "last" mode, and all other modes start from the second vertex.
95 *
96 * ~ C.
97 */
98
99 if (rs->rs.flatshade_first) {
100 switch (mode) {
101 case PIPE_PRIM_TRIANGLE_FAN:
102 color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND;
103 break;
104 case PIPE_PRIM_QUADS:
105 case PIPE_PRIM_QUAD_STRIP:
106 case PIPE_PRIM_POLYGON:
107 color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST;
108 break;
109 default:
110 color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST;
111 break;
112 }
113 } else {
114 color_control |= R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST;
115 }
116
117 return color_control;
118 }
119
120 /* Check if the requested number of dwords is available in the CS and
121 * if not, flush. Return TRUE if the flush occured. */
122 static boolean r300_reserve_cs_space(struct r300_context *r300,
123 unsigned dwords)
124 {
125 if (!r300->rws->check_cs(r300->rws, dwords)) {
126 r300->context.flush(&r300->context, 0, NULL);
127 return TRUE;
128 }
129 return FALSE;
130 }
131
132 static boolean immd_is_good_idea(struct r300_context *r300,
133 unsigned count)
134 {
135 struct pipe_vertex_element* velem;
136 struct pipe_vertex_buffer* vbuf;
137 boolean checked[PIPE_MAX_ATTRIBS] = {0};
138 unsigned vertex_element_count = r300->velems->count;
139 unsigned i, vbi;
140
141 if (count > 10) {
142 return FALSE;
143 }
144
145 /* We shouldn't map buffers referenced by CS, busy buffers,
146 * and ones placed in VRAM. */
147 /* XXX Check for VRAM buffers. */
148 for (i = 0; i < vertex_element_count; i++) {
149 velem = &r300->velems->velem[i];
150 vbi = velem->vertex_buffer_index;
151
152 if (!checked[vbi]) {
153 vbuf = &r300->vertex_buffer[vbi];
154
155 if (r300_buffer_is_referenced(r300, vbuf->buffer)) {
156 /* It's a very bad idea to map it... */
157 return FALSE;
158 }
159 checked[vbi] = TRUE;
160 }
161 }
162 return TRUE;
163 }
164
165 static void r300_emit_draw_arrays_immediate(struct r300_context *r300,
166 unsigned mode,
167 unsigned start,
168 unsigned count)
169 {
170 struct pipe_vertex_element* velem;
171 struct pipe_vertex_buffer* vbuf;
172 unsigned vertex_element_count = r300->velems->count;
173 unsigned i, v, vbi, dw, elem_offset, dwords;
174
175 /* Size of the vertex, in dwords. */
176 unsigned vertex_size = 0;
177
178 /* Offsets of the attribute, in dwords, from the start of the vertex. */
179 unsigned offset[PIPE_MAX_ATTRIBS];
180
181 /* Size of the vertex element, in dwords. */
182 unsigned size[PIPE_MAX_ATTRIBS];
183
184 /* Stride to the same attrib in the next vertex in the vertex buffer,
185 * in dwords. */
186 unsigned stride[PIPE_MAX_ATTRIBS] = {0};
187
188 /* Mapped vertex buffers. */
189 uint32_t* map[PIPE_MAX_ATTRIBS] = {0};
190
191 CS_LOCALS(r300);
192
193 /* Calculate the vertex size, offsets, strides etc. and map the buffers. */
194 for (i = 0; i < vertex_element_count; i++) {
195 velem = &r300->velems->velem[i];
196 offset[i] = velem->src_offset / 4;
197 size[i] = util_format_get_blocksize(velem->src_format) / 4;
198 vertex_size += size[i];
199 vbi = velem->vertex_buffer_index;
200
201 /* Map the buffer. */
202 if (!map[vbi]) {
203 vbuf = &r300->vertex_buffer[vbi];
204 map[vbi] = (uint32_t*)pipe_buffer_map(r300->context.screen,
205 vbuf->buffer,
206 PIPE_BUFFER_USAGE_CPU_READ);
207 map[vbi] += vbuf->buffer_offset / 4;
208 stride[vbi] = vbuf->stride / 4;
209 }
210 }
211
212 dwords = 9 + count * vertex_size;
213
214 r300_reserve_cs_space(r300, r300_get_num_dirty_dwords(r300) + dwords);
215 r300_emit_buffer_validate(r300, FALSE, NULL);
216 r300_emit_dirty_state(r300);
217
218 BEGIN_CS(dwords);
219 OUT_CS_REG(R300_GA_COLOR_CONTROL,
220 r300_provoking_vertex_fixes(r300, mode));
221 OUT_CS_REG(R300_VAP_VTX_SIZE, vertex_size);
222 OUT_CS_REG_SEQ(R300_VAP_VF_MAX_VTX_INDX, 2);
223 OUT_CS(count - 1);
224 OUT_CS(0);
225 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_IMMD_2, count * vertex_size);
226 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED | (count << 16) |
227 r300_translate_primitive(mode));
228
229 /* Emit vertices. */
230 for (v = 0; v < count; v++) {
231 for (i = 0; i < vertex_element_count; i++) {
232 velem = &r300->velems->velem[i];
233 vbi = velem->vertex_buffer_index;
234 elem_offset = offset[i] + stride[vbi] * (v + start);
235
236 for (dw = 0; dw < size[i]; dw++) {
237 OUT_CS(map[vbi][elem_offset + dw]);
238 }
239 }
240 }
241 END_CS;
242
243 /* Unmap buffers. */
244 for (i = 0; i < vertex_element_count; i++) {
245 vbi = r300->velems->velem[i].vertex_buffer_index;
246
247 if (map[vbi]) {
248 vbuf = &r300->vertex_buffer[vbi];
249 pipe_buffer_unmap(r300->context.screen, vbuf->buffer);
250 map[vbi] = NULL;
251 }
252 }
253 }
254
255 static void r300_emit_draw_arrays(struct r300_context *r300,
256 unsigned mode,
257 unsigned count)
258 {
259 #if defined(ENABLE_ALT_NUM_VERTS)
260 boolean alt_num_verts = count > 65535;
261 #else
262 boolean alt_num_verts = FALSE;
263 #endif
264 CS_LOCALS(r300);
265
266 if (alt_num_verts) {
267 assert(count < (1 << 24));
268 BEGIN_CS(9);
269 OUT_CS_REG(R500_VAP_ALT_NUM_VERTICES, count);
270 } else {
271 BEGIN_CS(7);
272 }
273 OUT_CS_REG(R300_GA_COLOR_CONTROL,
274 r300_provoking_vertex_fixes(r300, mode));
275 OUT_CS_REG_SEQ(R300_VAP_VF_MAX_VTX_INDX, 2);
276 OUT_CS(count - 1);
277 OUT_CS(0);
278 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
279 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (count << 16) |
280 r300_translate_primitive(mode) |
281 (alt_num_verts ? R500_VAP_VF_CNTL__USE_ALT_NUM_VERTS : 0));
282 END_CS;
283 }
284
285 static void r300_emit_draw_elements(struct r300_context *r300,
286 struct pipe_buffer* indexBuffer,
287 unsigned indexSize,
288 unsigned minIndex,
289 unsigned maxIndex,
290 unsigned mode,
291 unsigned start,
292 unsigned count)
293 {
294 uint32_t count_dwords;
295 uint32_t offset_dwords = indexSize * start / sizeof(uint32_t);
296 #if defined(ENABLE_ALT_NUM_VERTS)
297 boolean alt_num_verts = count > 65535;
298 #else
299 boolean alt_num_verts = FALSE;
300 #endif
301 CS_LOCALS(r300);
302
303 assert(count < (1 << 24));
304
305 maxIndex = MIN2(maxIndex, r300->vertex_buffer_max_index);
306
307 DBG(r300, DBG_DRAW, "r300: Indexbuf of %u indices, min %u max %u\n",
308 count, minIndex, maxIndex);
309
310 if (alt_num_verts) {
311 BEGIN_CS(15);
312 OUT_CS_REG(R500_VAP_ALT_NUM_VERTICES, count);
313 } else {
314 BEGIN_CS(13);
315 }
316 OUT_CS_REG(R300_GA_COLOR_CONTROL,
317 r300_provoking_vertex_fixes(r300, mode));
318 OUT_CS_REG_SEQ(R300_VAP_VF_MAX_VTX_INDX, 2);
319 OUT_CS(maxIndex);
320 OUT_CS(minIndex);
321 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_INDX_2, 0);
322 if (indexSize == 4) {
323 count_dwords = count;
324 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (count << 16) |
325 R300_VAP_VF_CNTL__INDEX_SIZE_32bit |
326 r300_translate_primitive(mode) |
327 (alt_num_verts ? R500_VAP_VF_CNTL__USE_ALT_NUM_VERTS : 0));
328 } else {
329 count_dwords = (count + 1) / 2;
330 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (count << 16) |
331 r300_translate_primitive(mode) |
332 (alt_num_verts ? R500_VAP_VF_CNTL__USE_ALT_NUM_VERTS : 0));
333 }
334
335 /* INDX_BUFFER is a truly special packet3.
336 * Unlike most other packet3, where the offset is after the count,
337 * the order is reversed, so the relocation ends up carrying the
338 * size of the indexbuf instead of the offset.
339 */
340 OUT_CS_PKT3(R300_PACKET3_INDX_BUFFER, 2);
341 OUT_CS(R300_INDX_BUFFER_ONE_REG_WR | (R300_VAP_PORT_IDX0 >> 2) |
342 (0 << R300_INDX_BUFFER_SKIP_SHIFT));
343 OUT_CS(offset_dwords << 2);
344 OUT_CS_BUF_RELOC(indexBuffer, count_dwords,
345 RADEON_GEM_DOMAIN_GTT, 0, 0);
346
347 END_CS;
348 }
349
350 static void r300_shorten_ubyte_elts(struct r300_context* r300,
351 struct pipe_buffer** elts,
352 unsigned start,
353 unsigned count)
354 {
355 struct pipe_screen* screen = r300->context.screen;
356 struct pipe_buffer* new_elts;
357 unsigned char *in_map;
358 unsigned short *out_map;
359 unsigned i;
360
361 new_elts = screen->buffer_create(screen, 32,
362 PIPE_BUFFER_USAGE_INDEX |
363 PIPE_BUFFER_USAGE_CPU_WRITE |
364 PIPE_BUFFER_USAGE_GPU_READ,
365 2 * count);
366
367 in_map = pipe_buffer_map(screen, *elts, PIPE_BUFFER_USAGE_CPU_READ);
368 out_map = pipe_buffer_map(screen, new_elts, PIPE_BUFFER_USAGE_CPU_WRITE);
369
370 in_map += start;
371
372 for (i = 0; i < count; i++) {
373 *out_map = (unsigned short)*in_map;
374 in_map++;
375 out_map++;
376 }
377
378 pipe_buffer_unmap(screen, *elts);
379 pipe_buffer_unmap(screen, new_elts);
380
381 *elts = new_elts;
382 }
383
384 static void r300_align_ushort_elts(struct r300_context *r300,
385 struct pipe_buffer **elts,
386 unsigned start, unsigned count)
387 {
388 struct pipe_screen* screen = r300->context.screen;
389 struct pipe_buffer* new_elts;
390 unsigned short *in_map;
391 unsigned short *out_map;
392
393 new_elts = screen->buffer_create(screen, 32,
394 PIPE_BUFFER_USAGE_INDEX |
395 PIPE_BUFFER_USAGE_CPU_WRITE |
396 PIPE_BUFFER_USAGE_GPU_READ,
397 2 * count);
398
399 in_map = pipe_buffer_map(screen, *elts, PIPE_BUFFER_USAGE_CPU_READ);
400 out_map = pipe_buffer_map(screen, new_elts, PIPE_BUFFER_USAGE_CPU_WRITE);
401
402 memcpy(out_map, in_map+start, 2 * count);
403
404 pipe_buffer_unmap(screen, *elts);
405 pipe_buffer_unmap(screen, new_elts);
406
407 *elts = new_elts;
408 }
409
410 /* This is the fast-path drawing & emission for HW TCL. */
411 void r300_draw_range_elements(struct pipe_context* pipe,
412 struct pipe_buffer* indexBuffer,
413 unsigned indexSize,
414 unsigned minIndex,
415 unsigned maxIndex,
416 unsigned mode,
417 unsigned start,
418 unsigned count)
419 {
420 struct r300_context* r300 = r300_context(pipe);
421 struct pipe_buffer* orgIndexBuffer = indexBuffer;
422 #if defined(ENABLE_ALT_NUM_VERTS)
423 boolean alt_num_verts = r300_screen(pipe->screen)->caps->is_r500 &&
424 count > 65536;
425 #else
426 boolean alt_num_verts = FALSE;
427 #endif
428 unsigned short_count;
429
430 if (!u_trim_pipe_prim(mode, &count)) {
431 return;
432 }
433
434 if (indexSize == 1) {
435 r300_shorten_ubyte_elts(r300, &indexBuffer, start, count);
436 indexSize = 2;
437 start = 0;
438 } else if (indexSize == 2 && start % 2 != 0) {
439 r300_align_ushort_elts(r300, &indexBuffer, start, count);
440 start = 0;
441 }
442
443 r300_update_derived_state(r300);
444
445 r300_upload_index_buffer(r300, &indexBuffer, indexSize, start, count);
446
447 /* 128 dwords for emit_aos and emit_draw_elements */
448 r300_reserve_cs_space(r300, r300_get_num_dirty_dwords(r300) + 128);
449 r300_emit_buffer_validate(r300, TRUE, indexBuffer);
450 r300_emit_dirty_state(r300);
451 r300_emit_aos(r300, 0);
452
453 u_upload_flush(r300->upload_vb);
454 u_upload_flush(r300->upload_ib);
455 if (alt_num_verts || count <= 65535) {
456 r300_emit_draw_elements(r300, indexBuffer, indexSize, minIndex,
457 maxIndex, mode, start, count);
458 } else {
459 do {
460 short_count = MIN2(count, 65534);
461 r300_emit_draw_elements(r300, indexBuffer, indexSize, minIndex,
462 maxIndex, mode, start, short_count);
463
464 start += short_count;
465 count -= short_count;
466
467 /* 16 spare dwords are enough for emit_draw_elements. */
468 if (count && r300_reserve_cs_space(r300, 16)) {
469 r300_emit_buffer_validate(r300, TRUE, indexBuffer);
470 r300_emit_dirty_state(r300);
471 r300_emit_aos(r300, 0);
472 }
473 } while (count);
474 }
475
476 if (indexBuffer != orgIndexBuffer) {
477 pipe_buffer_reference( &indexBuffer, NULL );
478 }
479 }
480
481 /* Simple helpers for context setup. Should probably be moved to util. */
482 void r300_draw_elements(struct pipe_context* pipe,
483 struct pipe_buffer* indexBuffer,
484 unsigned indexSize, unsigned mode,
485 unsigned start, unsigned count)
486 {
487 struct r300_context *r300 = r300_context(pipe);
488
489 pipe->draw_range_elements(pipe, indexBuffer, indexSize, 0,
490 r300->vertex_buffer_max_index,
491 mode, start, count);
492 }
493
494 void r300_draw_arrays(struct pipe_context* pipe, unsigned mode,
495 unsigned start, unsigned count)
496 {
497 struct r300_context* r300 = r300_context(pipe);
498 #if defined(ENABLE_ALT_NUM_VERTS)
499 boolean alt_num_verts = r300_screen(pipe->screen)->caps->is_r500 &&
500 count > 65536;
501 #else
502 boolean alt_num_verts = FALSE;
503 #endif
504 unsigned short_count;
505
506 if (!u_trim_pipe_prim(mode, &count)) {
507 return;
508 }
509
510 r300_update_derived_state(r300);
511
512 if (immd_is_good_idea(r300, count)) {
513 r300_emit_draw_arrays_immediate(r300, mode, start, count);
514 } else {
515 /* Make sure there are at least 128 spare dwords in the command buffer.
516 * (most of it being consumed by emit_aos) */
517 r300_reserve_cs_space(r300, r300_get_num_dirty_dwords(r300) + 128);
518 r300_emit_buffer_validate(r300, TRUE, NULL);
519 r300_emit_dirty_state(r300);
520
521 if (alt_num_verts || count <= 65535) {
522 r300_emit_aos(r300, start);
523 r300_emit_draw_arrays(r300, mode, count);
524 } else {
525 do {
526 short_count = MIN2(count, 65535);
527 r300_emit_aos(r300, start);
528 r300_emit_draw_arrays(r300, mode, short_count);
529
530 start += short_count;
531 count -= short_count;
532
533 /* Again, we emit both AOS and draw_arrays so there should be
534 * at least 128 spare dwords. */
535 if (count && r300_reserve_cs_space(r300, 128)) {
536 r300_emit_buffer_validate(r300, TRUE, NULL);
537 r300_emit_dirty_state(r300);
538 }
539 } while (count);
540 }
541 u_upload_flush(r300->upload_vb);
542 }
543 }
544
545 /****************************************************************************
546 * The rest of this file is for SW TCL rendering only. Please be polite and *
547 * keep these functions separated so that they are easier to locate. ~C. *
548 ***************************************************************************/
549
550 /* SW TCL arrays, using Draw. */
551 void r300_swtcl_draw_arrays(struct pipe_context* pipe,
552 unsigned mode,
553 unsigned start,
554 unsigned count)
555 {
556 struct r300_context* r300 = r300_context(pipe);
557 int i;
558
559 if (!u_trim_pipe_prim(mode, &count)) {
560 return;
561 }
562
563 for (i = 0; i < r300->vertex_buffer_count; i++) {
564 void* buf = pipe_buffer_map(pipe->screen,
565 r300->vertex_buffer[i].buffer,
566 PIPE_BUFFER_USAGE_CPU_READ);
567 draw_set_mapped_vertex_buffer(r300->draw, i, buf);
568 }
569
570 draw_set_mapped_element_buffer(r300->draw, 0, NULL);
571
572 draw_set_mapped_constant_buffer(r300->draw,
573 PIPE_SHADER_VERTEX,
574 0,
575 r300->shader_constants[PIPE_SHADER_VERTEX].constants,
576 r300->shader_constants[PIPE_SHADER_VERTEX].count *
577 (sizeof(float) * 4));
578
579 draw_arrays(r300->draw, mode, start, count);
580
581 for (i = 0; i < r300->vertex_buffer_count; i++) {
582 pipe_buffer_unmap(pipe->screen, r300->vertex_buffer[i].buffer);
583 draw_set_mapped_vertex_buffer(r300->draw, i, NULL);
584 }
585 }
586
587 /* SW TCL elements, using Draw. */
588 void r300_swtcl_draw_range_elements(struct pipe_context* pipe,
589 struct pipe_buffer* indexBuffer,
590 unsigned indexSize,
591 unsigned minIndex,
592 unsigned maxIndex,
593 unsigned mode,
594 unsigned start,
595 unsigned count)
596 {
597 struct r300_context* r300 = r300_context(pipe);
598 int i;
599 void* indices;
600
601 if (!u_trim_pipe_prim(mode, &count)) {
602 return;
603 }
604
605 for (i = 0; i < r300->vertex_buffer_count; i++) {
606 void* buf = pipe_buffer_map(pipe->screen,
607 r300->vertex_buffer[i].buffer,
608 PIPE_BUFFER_USAGE_CPU_READ);
609 draw_set_mapped_vertex_buffer(r300->draw, i, buf);
610 }
611
612 indices = pipe_buffer_map(pipe->screen, indexBuffer,
613 PIPE_BUFFER_USAGE_CPU_READ);
614 draw_set_mapped_element_buffer_range(r300->draw, indexSize,
615 minIndex, maxIndex, indices);
616
617 draw_set_mapped_constant_buffer(r300->draw,
618 PIPE_SHADER_VERTEX,
619 0,
620 r300->shader_constants[PIPE_SHADER_VERTEX].constants,
621 r300->shader_constants[PIPE_SHADER_VERTEX].count *
622 (sizeof(float) * 4));
623
624 draw_arrays(r300->draw, mode, start, count);
625
626 for (i = 0; i < r300->vertex_buffer_count; i++) {
627 pipe_buffer_unmap(pipe->screen, r300->vertex_buffer[i].buffer);
628 draw_set_mapped_vertex_buffer(r300->draw, i, NULL);
629 }
630
631 pipe_buffer_unmap(pipe->screen, indexBuffer);
632 draw_set_mapped_element_buffer_range(r300->draw, 0, start,
633 start + count - 1, NULL);
634 }
635
636 /* Object for rendering using Draw. */
637 struct r300_render {
638 /* Parent class */
639 struct vbuf_render base;
640
641 /* Pipe context */
642 struct r300_context* r300;
643
644 /* Vertex information */
645 size_t vertex_size;
646 unsigned prim;
647 unsigned hwprim;
648
649 /* VBO */
650 struct pipe_buffer* vbo;
651 size_t vbo_size;
652 size_t vbo_offset;
653 size_t vbo_max_used;
654 void * vbo_ptr;
655 };
656
657 static INLINE struct r300_render*
658 r300_render(struct vbuf_render* render)
659 {
660 return (struct r300_render*)render;
661 }
662
663 static const struct vertex_info*
664 r300_render_get_vertex_info(struct vbuf_render* render)
665 {
666 struct r300_render* r300render = r300_render(render);
667 struct r300_context* r300 = r300render->r300;
668
669 r300_update_derived_state(r300);
670
671 return &r300->vertex_info;
672 }
673
674 static boolean r300_render_allocate_vertices(struct vbuf_render* render,
675 ushort vertex_size,
676 ushort count)
677 {
678 struct r300_render* r300render = r300_render(render);
679 struct r300_context* r300 = r300render->r300;
680 struct pipe_screen* screen = r300->context.screen;
681 size_t size = (size_t)vertex_size * (size_t)count;
682
683 if (size + r300render->vbo_offset > r300render->vbo_size)
684 {
685 pipe_buffer_reference(&r300->vbo, NULL);
686 r300render->vbo = pipe_buffer_create(screen,
687 64,
688 PIPE_BUFFER_USAGE_VERTEX,
689 R300_MAX_DRAW_VBO_SIZE);
690 r300render->vbo_offset = 0;
691 r300render->vbo_size = R300_MAX_DRAW_VBO_SIZE;
692 }
693
694 r300render->vertex_size = vertex_size;
695 r300->vbo = r300render->vbo;
696 r300->vbo_offset = r300render->vbo_offset;
697
698 return (r300render->vbo) ? TRUE : FALSE;
699 }
700
701 static void* r300_render_map_vertices(struct vbuf_render* render)
702 {
703 struct r300_render* r300render = r300_render(render);
704 struct pipe_screen* screen = r300render->r300->context.screen;
705
706 r300render->vbo_ptr = pipe_buffer_map(screen, r300render->vbo,
707 PIPE_BUFFER_USAGE_CPU_WRITE);
708
709 return ((uint8_t*)r300render->vbo_ptr + r300render->vbo_offset);
710 }
711
712 static void r300_render_unmap_vertices(struct vbuf_render* render,
713 ushort min,
714 ushort max)
715 {
716 struct r300_render* r300render = r300_render(render);
717 struct pipe_screen* screen = r300render->r300->context.screen;
718 CS_LOCALS(r300render->r300);
719 BEGIN_CS(2);
720 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, max);
721 END_CS;
722
723 r300render->vbo_max_used = MAX2(r300render->vbo_max_used,
724 r300render->vertex_size * (max + 1));
725 pipe_buffer_unmap(screen, r300render->vbo);
726 }
727
728 static void r300_render_release_vertices(struct vbuf_render* render)
729 {
730 struct r300_render* r300render = r300_render(render);
731
732 r300render->vbo_offset += r300render->vbo_max_used;
733 r300render->vbo_max_used = 0;
734 }
735
736 static boolean r300_render_set_primitive(struct vbuf_render* render,
737 unsigned prim)
738 {
739 struct r300_render* r300render = r300_render(render);
740
741 r300render->prim = prim;
742 r300render->hwprim = r300_translate_primitive(prim);
743
744 return TRUE;
745 }
746
747 static void r300_render_draw_arrays(struct vbuf_render* render,
748 unsigned start,
749 unsigned count)
750 {
751 struct r300_render* r300render = r300_render(render);
752 struct r300_context* r300 = r300render->r300;
753
754 CS_LOCALS(r300);
755
756 r300_reserve_cs_space(r300, r300_get_num_dirty_dwords(r300) + 2);
757 r300_emit_buffer_validate(r300, FALSE, NULL);
758 r300_emit_dirty_state(r300);
759
760 DBG(r300, DBG_DRAW, "r300: Doing vbuf render, count %d\n", count);
761
762 BEGIN_CS(2);
763 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
764 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (count << 16) |
765 r300render->hwprim);
766 END_CS;
767 }
768
769 static void r300_render_draw(struct vbuf_render* render,
770 const ushort* indices,
771 uint count)
772 {
773 struct r300_render* r300render = r300_render(render);
774 struct r300_context* r300 = r300render->r300;
775 int i;
776 unsigned dwords = 2 + (count+1)/2;
777
778 CS_LOCALS(r300);
779
780 r300_reserve_cs_space(r300, r300_get_num_dirty_dwords(r300) + dwords);
781 r300_emit_buffer_validate(r300, FALSE, NULL);
782 r300_emit_dirty_state(r300);
783
784 BEGIN_CS(dwords);
785 OUT_CS_PKT3(R300_PACKET3_3D_DRAW_INDX_2, (count+1)/2);
786 OUT_CS(R300_VAP_VF_CNTL__PRIM_WALK_INDICES | (count << 16) |
787 r300render->hwprim);
788 for (i = 0; i < count-1; i += 2) {
789 OUT_CS(indices[i+1] << 16 | indices[i]);
790 }
791 if (count % 2) {
792 OUT_CS(indices[count-1]);
793 }
794 END_CS;
795 }
796
797 static void r300_render_destroy(struct vbuf_render* render)
798 {
799 FREE(render);
800 }
801
802 static struct vbuf_render* r300_render_create(struct r300_context* r300)
803 {
804 struct r300_render* r300render = CALLOC_STRUCT(r300_render);
805
806 r300render->r300 = r300;
807
808 /* XXX find real numbers plz */
809 r300render->base.max_vertex_buffer_bytes = 128 * 1024;
810 r300render->base.max_indices = 16 * 1024;
811
812 r300render->base.get_vertex_info = r300_render_get_vertex_info;
813 r300render->base.allocate_vertices = r300_render_allocate_vertices;
814 r300render->base.map_vertices = r300_render_map_vertices;
815 r300render->base.unmap_vertices = r300_render_unmap_vertices;
816 r300render->base.set_primitive = r300_render_set_primitive;
817 r300render->base.draw = r300_render_draw;
818 r300render->base.draw_arrays = r300_render_draw_arrays;
819 r300render->base.release_vertices = r300_render_release_vertices;
820 r300render->base.destroy = r300_render_destroy;
821
822 r300render->vbo = NULL;
823 r300render->vbo_size = 0;
824 r300render->vbo_offset = 0;
825
826 return &r300render->base;
827 }
828
829 struct draw_stage* r300_draw_stage(struct r300_context* r300)
830 {
831 struct vbuf_render* render;
832 struct draw_stage* stage;
833
834 render = r300_render_create(r300);
835
836 if (!render) {
837 return NULL;
838 }
839
840 stage = draw_vbuf_stage(r300->draw, render);
841
842 if (!stage) {
843 render->destroy(render);
844 return NULL;
845 }
846
847 draw_set_render(r300->draw, render);
848
849 return stage;
850 }