src/gallium/drivers/r300/r300_surface.c

   1 /*
   2  * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE. */
  22
  23 #include "r300_surface.h"
  24
  25 /* Provides pipe_context's "surface_fill". Commonly used for clearing
  26  * buffers. */
  27 static void r300_surface_fill(struct pipe_context* pipe,
  28                               struct pipe_surface* dest,
  29                               unsigned x, unsigned y,
  30                               unsigned w, unsigned h,
  31                               unsigned color)
  32 {
  33     struct r300_context* r300 = r300_context(pipe);
  34     CS_LOCALS(r300);
  35     struct r300_capabilities* caps = ((struct r300_screen*)pipe->screen)->caps;
  36     struct r300_texture* tex = (struct r300_texture*)dest->texture;
  37     int i;
  38     float r, g, b, a;
  39     r = (float)((color >> 16) & 0xff) / 255.0f;
  40     g = (float)((color >>  8) & 0xff) / 255.0f;
  41     b = (float)((color >>  0) & 0xff) / 255.0f;
  42     debug_printf("r300: Filling surface %p at (%d,%d),"
  43         " dimensions %dx%d (stride %d), color 0x%x\n",
  44         dest, x, y, w, h, dest->stride, color);
  45
  46     /* Fallback? */
  47     if (0) {
  48         debug_printf("r300: Falling back on surface clear...");
  49         void* map = pipe->screen->surface_map(pipe->screen, dest,
  50             PIPE_BUFFER_USAGE_CPU_WRITE);
  51         pipe_fill_rect(map, &dest->block, &dest->stride, x, y, w, h, color);
  52         pipe->screen->surface_unmap(pipe->screen, dest);
  53         return;
  54     }
  55
  56 BEGIN_CS((caps->is_r500) ? 309 : 280);
  57 R300_PACIFY;
  58 OUT_CS_REG(R300_TX_INVALTAGS, 0x0);
  59 R300_PACIFY;
  60 /* Flush PVS. */
  61 OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
  62
  63 OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA |
  64     R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA |
  65     R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA |
  66     R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT);
  67 /* Vertex size. */
  68 OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8);
  69 /* Max and min vertex index clamp. */
  70 OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF);
  71 OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0);
  72 /* XXX endian */
  73 OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP);
  74 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0);
  75 /* XXX magic number not in r300_reg */
  76 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
  77 OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0);
  78 OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4);
  79 OUT_CS_32F(1.0);
  80 OUT_CS_32F(1.0);
  81 OUT_CS_32F(1.0);
  82 OUT_CS_32F(1.0);
  83 /* XXX is this too long? */
  84 OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xFFFF);
  85 OUT_CS_REG(R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE |
  86     R300_GB_LINE_STUFF_ENABLE | R300_GB_TRIANGLE_STUFF_ENABLE);
  87 /* XXX more magic numbers */
  88 OUT_CS_REG(R300_GB_MSPOS0, 0x66666666);
  89 OUT_CS_REG(R300_GB_MSPOS1, 0x66666666);
  90 /* XXX why doesn't classic Mesa write the number of pipes, too? */
  91 OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16);
  92 OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
  93 OUT_CS_REG(R300_GB_AA_CONFIG, 0x0);
  94 /* XXX point tex stuffing */
  95 OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1);
  96 OUT_CS_32F(0.0);
  97 OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1);
  98 OUT_CS_32F(1.0);
  99 OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 |
 100     (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT));
 101 /* XXX should this be related to the actual point size? */
 102 OUT_CS_REG(R300_GA_POINT_MINMAX, 0x6 |
 103     (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT));
 104 /* XXX this big chunk should be refactored into rs_state */
 105 OUT_CS_REG(R300_GA_LINE_CNTL, 0x00030006);
 106 OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, 0x3BAAAAAB);
 107 OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, 0x00000000);
 108 OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
 109 OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
 110 OUT_CS_REG(R300_GA_ENHANCE, 0x00000002);
 111 OUT_CS_REG(R300_GA_COLOR_CONTROL, 0x0003AAAA);
 112 OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
 113 OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
 114 OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);
 115 OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001);
 116 OUT_CS_REG(R300_GA_OFFSET, 0x00000000);
 117 OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412);
 118 OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000);
 119 OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000);
 120 OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_SCALE, 0x00000000);
 121 OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_OFFSET, 0x00000000);
 122 OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_SCALE, 0x00000000);
 123 OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_OFFSET, 0x00000000);
 124 OUT_CS_REG(R300_SU_POLY_OFFSET_ENABLE, 0x00000000);
 125 OUT_CS_REG(R300_SU_CULL_MODE, 0x00000000);
 126 OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF);
 127 OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000);
 128 OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C);
 129 OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525);
 130 OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF);
 131 OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002);
 132 OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000);
 133 OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000);
 134 OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x00000000);
 135 OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
 136 OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000);
 137 OUT_CS_REG(R300_RB3D_CCTL, 0x00000000);
 138 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 139
 140 /* XXX: Oh the wonderful unknown */
 141 OUT_CS_REG_SEQ(0x4E54, 8);
 142 for (i = 0; i < 8; i++)
 143     OUT_CS(0x00000000);
 144 OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000);
 145 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000);
 146 OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF);
 147 OUT_CS_REG(R300_ZB_FORMAT, 0x00000002);
 148 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003);
 149 OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000);
 150 OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000);
 151 OUT_CS_REG(0x4F30, 0x00000000);
 152 OUT_CS_REG(0x4F34, 0x00000000);
 153 OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000);
 154 OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000);
 155 R300_PACIFY;
 156 if (caps->has_tcl) {
 157     OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
 158         (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
 159         ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) |
 160             R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
 161 } else {
 162     OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0,
 163         (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) |
 164         ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) |
 165             R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT));
 166 }
 167 OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000);
 168 OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688);
 169 OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1);
 170 OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405);
 171 OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F);
 172 OUT_CS_REG(R300_VAP_VTX_SIZE, 0x00000008);
 173 OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA);
 174 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003);
 175 OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000);
 176 OUT_CS_REG(R300_TX_ENABLE, 0x0);
 177 /* XXX viewport setup */
 178 OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6);
 179 OUT_CS_32F(1.0);
 180 OUT_CS_32F((float)x);
 181 OUT_CS_32F(1.0);
 182 OUT_CS_32F((float)y);
 183 OUT_CS_32F(1.0);
 184 OUT_CS_32F(0.0);
 185
 186 if (caps->has_tcl) {
 187     OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE |
 188         R300_PS_UCP_MODE_CLIP_AS_TRIFAN);
 189 }
 190
 191 OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) |
 192     ((w * 6) << R300_POINTSIZE_X_SHIFT));
 193
 194 /* XXX RS block and fp setup */
 195 if (caps->is_r500) {
 196     OUT_CS_REG_SEQ(R500_RS_IP_0, 8);
 197     for (i = 0; i < 8; i++) {
 198         /* I like the operator macros more than the shift macros... */
 199         OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
 200             (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) |
 201             (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
 202             (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT));
 203     }
 204     /* XXX */
 205     OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
 206     OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
 207     OUT_CS(0x0);
 208     OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE);
 209
 210     OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
 211     OUT_CS_REG(R500_US_PIXSIZE, 0x00000000);
 212     OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) |
 213         R500_US_CODE_END_ADDR(1));
 214     OUT_CS_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) |
 215         R500_US_CODE_RANGE_SIZE(1));
 216     OUT_CS_REG(R500_US_CODE_OFFSET, R500_US_CODE_OFFSET_ADDR(0));
 217     R300_PACIFY;
 218     OUT_CS_REG(R500_GA_US_VECTOR_INDEX,
 219         0 | R500_GA_US_VECTOR_INDEX_TYPE_INSTR);
 220     OUT_CS_REG(R500_GA_US_VECTOR_DATA,
 221         R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST |
 222         R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B |
 223         R500_INST_ALPHA_OMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP);
 224     OUT_CS_REG(R500_GA_US_VECTOR_DATA,
 225         R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST |
 226         R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST);
 227     OUT_CS_REG(R500_GA_US_VECTOR_DATA,
 228         R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST |
 229         R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST);
 230     OUT_CS_REG(R500_GA_US_VECTOR_DATA,
 231         R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R |
 232         R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B |
 233         R500_ALU_RGB_SEL_B_SRC0 | R500_ALU_RGB_R_SWIZ_B_R |
 234         R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B);
 235     OUT_CS_REG(R500_GA_US_VECTOR_DATA,
 236         R500_ALPHA_OP_CMP | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_A);
 237     OUT_CS_REG(R500_GA_US_VECTOR_DATA,
 238         R500_ALU_RGBA_OP_CMP | R500_ALU_RGBA_R_SWIZ_0 |
 239         R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 |
 240         R500_ALU_RGBA_A_SWIZ_0);
 241 } else {
 242     OUT_CS_REG_SEQ(R300_RS_IP_0, 8);
 243     for (i = 0; i < 8; i++) {
 244         OUT_CS(R300_RS_SEL_T(R300_RS_SEL_K0) |
 245             R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1));
 246     }
 247     /* XXX */
 248     OUT_CS_REG_SEQ(R300_RS_COUNT, 2);
 249     OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN);
 250     OUT_CS(1);
 251     OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE);
 252
 253     /* XXX magic numbers */
 254     OUT_CS_REG(R300_US_CONFIG, 0);
 255     OUT_CS_REG(R300_US_PIXSIZE, 2);
 256     OUT_CS_REG(R300_US_CODE_OFFSET, 0x0);
 257     OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0);
 258     OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0);
 259     OUT_CS_REG(R300_US_CODE_ADDR_2, 0x0);
 260     OUT_CS_REG(R300_US_CODE_ADDR_3, 0x400000);
 261     OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x50A80);
 262     OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000);
 263     OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x40889);
 264     OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1000000);
 265     OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4);
 266     OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_C3_SEL_A);
 267     OUT_CS(R300_US_OUT_FMT_UNUSED);
 268     OUT_CS(R300_US_OUT_FMT_UNUSED);
 269     OUT_CS(R300_US_OUT_FMT_UNUSED);
 270     OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0);
 271 }
 272 /* XXX these magic numbers should be explained when
 273  * this becomes a cached state object */
 274 if (caps->has_tcl) {
 275     OUT_CS_REG(R300_VAP_CNTL, 0xA |
 276         (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 277         (0xB << R300_VF_MAX_VTX_NUM_SHIFT) |
 278         (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
 279     OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000);
 280     OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000);
 281     OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001);
 282     R300_PACIFY;
 283     /* XXX translate these back into normal instructions */
 284     OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1);
 285     OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0);
 286     OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF00203);
 287     OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10001);
 288     OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248001);
 289     OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0);
 290     OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF02203);
 291     OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021);
 292     OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021);
 293     OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0);
 294 } else {
 295     OUT_CS_REG(R300_VAP_CNTL, 0xA |
 296         (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) |
 297         (0x5 << R300_VF_MAX_VTX_NUM_SHIFT) |
 298         (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT));
 299 }
 300 R300_PACIFY;
 301 END_CS;
 302
 303 r300_emit_blend_state(r300, &blend_clear_state);
 304 r300_emit_blend_color_state(r300, &blend_color_clear_state);
 305 r300_emit_dsa_state(r300, &dsa_clear_state);
 306
 307 BEGIN_CS(36);
 308 R300_PACIFY;
 309 /* Flush colorbuffer and blend caches. */
 310 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
 311     R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D |
 312     R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL);
 313 OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 314     R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 315     R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
 316
 317 OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1);
 318 OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
 319 /* XXX this should not be so rigid and it still doesn't work right */
 320 OUT_CS_REG(R300_RB3D_COLORPITCH0, (dest->stride >> 2) | R300_COLOR_FORMAT_ARGB8888);
 321 OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F);
 322 /* XXX Packet3 */
 323 OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
 324 OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
 325 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
 326 OUT_CS_32F(w / 2.0);
 327 OUT_CS_32F(h / 2.0);
 328 /* XXX this should be the depth value to clear to */
 329 OUT_CS_32F(1.0);
 330 OUT_CS_32F(1.0);
 331 OUT_CS_32F(r);
 332 OUT_CS_32F(g);
 333 OUT_CS_32F(b);
 334 OUT_CS_32F(1.0);
 335
 336 /* XXX figure out why this is 0xA and not 0x2 */
 337 OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA);
 338 /* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT,
 339     R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
 340     R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */
 341 R300_PACIFY;
 342
 343 END_CS;
 344 FLUSH_CS;
 345
 346     r300->dirty_state = R300_NEW_KITCHEN_SINK;
 347 }
 348
 349 void r300_init_surface_functions(struct r300_context* r300)
 350 {
 351     r300->context.surface_fill = r300_surface_fill;
 352 }