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Merge branch 'gallium-polygon-stipple'
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "r600_formats.h"
50
51 static uint32_t r600_translate_blend_function(int blend_func)
52 {
53 switch (blend_func) {
54 case PIPE_BLEND_ADD:
55 return V_028780_COMB_DST_PLUS_SRC;
56 case PIPE_BLEND_SUBTRACT:
57 return V_028780_COMB_SRC_MINUS_DST;
58 case PIPE_BLEND_REVERSE_SUBTRACT:
59 return V_028780_COMB_DST_MINUS_SRC;
60 case PIPE_BLEND_MIN:
61 return V_028780_COMB_MIN_DST_SRC;
62 case PIPE_BLEND_MAX:
63 return V_028780_COMB_MAX_DST_SRC;
64 default:
65 R600_ERR("Unknown blend function %d\n", blend_func);
66 assert(0);
67 break;
68 }
69 return 0;
70 }
71
72 static uint32_t r600_translate_blend_factor(int blend_fact)
73 {
74 switch (blend_fact) {
75 case PIPE_BLENDFACTOR_ONE:
76 return V_028780_BLEND_ONE;
77 case PIPE_BLENDFACTOR_SRC_COLOR:
78 return V_028780_BLEND_SRC_COLOR;
79 case PIPE_BLENDFACTOR_SRC_ALPHA:
80 return V_028780_BLEND_SRC_ALPHA;
81 case PIPE_BLENDFACTOR_DST_ALPHA:
82 return V_028780_BLEND_DST_ALPHA;
83 case PIPE_BLENDFACTOR_DST_COLOR:
84 return V_028780_BLEND_DST_COLOR;
85 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
86 return V_028780_BLEND_SRC_ALPHA_SATURATE;
87 case PIPE_BLENDFACTOR_CONST_COLOR:
88 return V_028780_BLEND_CONST_COLOR;
89 case PIPE_BLENDFACTOR_CONST_ALPHA:
90 return V_028780_BLEND_CONST_ALPHA;
91 case PIPE_BLENDFACTOR_ZERO:
92 return V_028780_BLEND_ZERO;
93 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
94 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
95 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
96 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
97 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
98 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
99 case PIPE_BLENDFACTOR_INV_DST_COLOR:
100 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
101 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
102 return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
103 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
105 case PIPE_BLENDFACTOR_SRC1_COLOR:
106 return V_028780_BLEND_SRC1_COLOR;
107 case PIPE_BLENDFACTOR_SRC1_ALPHA:
108 return V_028780_BLEND_SRC1_ALPHA;
109 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
110 return V_028780_BLEND_INV_SRC1_COLOR;
111 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
112 return V_028780_BLEND_INV_SRC1_ALPHA;
113 default:
114 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
115 assert(0);
116 break;
117 }
118 return 0;
119 }
120
121 static uint32_t r600_translate_stencil_op(int s_op)
122 {
123 switch (s_op) {
124 case PIPE_STENCIL_OP_KEEP:
125 return V_028800_STENCIL_KEEP;
126 case PIPE_STENCIL_OP_ZERO:
127 return V_028800_STENCIL_ZERO;
128 case PIPE_STENCIL_OP_REPLACE:
129 return V_028800_STENCIL_REPLACE;
130 case PIPE_STENCIL_OP_INCR:
131 return V_028800_STENCIL_INCR;
132 case PIPE_STENCIL_OP_DECR:
133 return V_028800_STENCIL_DECR;
134 case PIPE_STENCIL_OP_INCR_WRAP:
135 return V_028800_STENCIL_INCR_WRAP;
136 case PIPE_STENCIL_OP_DECR_WRAP:
137 return V_028800_STENCIL_DECR_WRAP;
138 case PIPE_STENCIL_OP_INVERT:
139 return V_028800_STENCIL_INVERT;
140 default:
141 R600_ERR("Unknown stencil op %d", s_op);
142 assert(0);
143 break;
144 }
145 return 0;
146 }
147
148 static uint32_t r600_translate_fill(uint32_t func)
149 {
150 switch(func) {
151 case PIPE_POLYGON_MODE_FILL:
152 return 2;
153 case PIPE_POLYGON_MODE_LINE:
154 return 1;
155 case PIPE_POLYGON_MODE_POINT:
156 return 0;
157 default:
158 assert(0);
159 return 0;
160 }
161 }
162
163 /* translates straight */
164 static uint32_t r600_translate_ds_func(int func)
165 {
166 return func;
167 }
168
169 static unsigned r600_tex_wrap(unsigned wrap)
170 {
171 switch (wrap) {
172 default:
173 case PIPE_TEX_WRAP_REPEAT:
174 return V_03C000_SQ_TEX_WRAP;
175 case PIPE_TEX_WRAP_CLAMP:
176 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
177 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
178 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
179 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
180 return V_03C000_SQ_TEX_CLAMP_BORDER;
181 case PIPE_TEX_WRAP_MIRROR_REPEAT:
182 return V_03C000_SQ_TEX_MIRROR;
183 case PIPE_TEX_WRAP_MIRROR_CLAMP:
184 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
185 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
186 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
187 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
188 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
189 }
190 }
191
192 static unsigned r600_tex_filter(unsigned filter)
193 {
194 switch (filter) {
195 default:
196 case PIPE_TEX_FILTER_NEAREST:
197 return V_03C000_SQ_TEX_XY_FILTER_POINT;
198 case PIPE_TEX_FILTER_LINEAR:
199 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
200 }
201 }
202
203 static unsigned r600_tex_mipfilter(unsigned filter)
204 {
205 switch (filter) {
206 case PIPE_TEX_MIPFILTER_NEAREST:
207 return V_03C000_SQ_TEX_Z_FILTER_POINT;
208 case PIPE_TEX_MIPFILTER_LINEAR:
209 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
210 default:
211 case PIPE_TEX_MIPFILTER_NONE:
212 return V_03C000_SQ_TEX_Z_FILTER_NONE;
213 }
214 }
215
216 static unsigned r600_tex_compare(unsigned compare)
217 {
218 switch (compare) {
219 default:
220 case PIPE_FUNC_NEVER:
221 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
222 case PIPE_FUNC_LESS:
223 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
224 case PIPE_FUNC_EQUAL:
225 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
226 case PIPE_FUNC_LEQUAL:
227 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
228 case PIPE_FUNC_GREATER:
229 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
230 case PIPE_FUNC_NOTEQUAL:
231 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
232 case PIPE_FUNC_GEQUAL:
233 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
234 case PIPE_FUNC_ALWAYS:
235 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
236 }
237 }
238
239 static unsigned r600_tex_dim(unsigned dim)
240 {
241 switch (dim) {
242 default:
243 case PIPE_TEXTURE_1D:
244 return V_030000_SQ_TEX_DIM_1D;
245 case PIPE_TEXTURE_1D_ARRAY:
246 return V_030000_SQ_TEX_DIM_1D_ARRAY;
247 case PIPE_TEXTURE_2D:
248 case PIPE_TEXTURE_RECT:
249 return V_030000_SQ_TEX_DIM_2D;
250 case PIPE_TEXTURE_2D_ARRAY:
251 return V_030000_SQ_TEX_DIM_2D_ARRAY;
252 case PIPE_TEXTURE_3D:
253 return V_030000_SQ_TEX_DIM_3D;
254 case PIPE_TEXTURE_CUBE:
255 return V_030000_SQ_TEX_DIM_CUBEMAP;
256 }
257 }
258
259 static uint32_t r600_translate_dbformat(enum pipe_format format)
260 {
261 switch (format) {
262 case PIPE_FORMAT_Z16_UNORM:
263 return V_028040_Z_16;
264 case PIPE_FORMAT_Z24X8_UNORM:
265 return V_028040_Z_24;
266 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
267 return V_028040_Z_24;
268 default:
269 return ~0U;
270 }
271 }
272
273 static uint32_t r600_translate_stencilformat(enum pipe_format format)
274 {
275 if (format == PIPE_FORMAT_Z24_UNORM_S8_USCALED)
276 return 1;
277 else
278 return 0;
279 }
280
281 static uint32_t r600_translate_colorswap(enum pipe_format format)
282 {
283 switch (format) {
284 /* 8-bit buffers. */
285 case PIPE_FORMAT_L4A4_UNORM:
286 return V_028C70_SWAP_ALT;
287
288 case PIPE_FORMAT_A8_UNORM:
289 return V_028C70_SWAP_ALT_REV;
290 case PIPE_FORMAT_I8_UNORM:
291 case PIPE_FORMAT_L8_UNORM:
292 case PIPE_FORMAT_L8_SRGB:
293 case PIPE_FORMAT_R8_UNORM:
294 case PIPE_FORMAT_R8_SNORM:
295 return V_028C70_SWAP_STD;
296
297 /* 16-bit buffers. */
298 case PIPE_FORMAT_B5G6R5_UNORM:
299 return V_028C70_SWAP_STD_REV;
300
301 case PIPE_FORMAT_B5G5R5A1_UNORM:
302 case PIPE_FORMAT_B5G5R5X1_UNORM:
303 return V_028C70_SWAP_ALT;
304
305 case PIPE_FORMAT_B4G4R4A4_UNORM:
306 case PIPE_FORMAT_B4G4R4X4_UNORM:
307 return V_028C70_SWAP_ALT;
308
309 case PIPE_FORMAT_Z16_UNORM:
310 return V_028C70_SWAP_STD;
311
312 case PIPE_FORMAT_L8A8_UNORM:
313 case PIPE_FORMAT_L8A8_SRGB:
314 return V_028C70_SWAP_ALT;
315 case PIPE_FORMAT_R8G8_UNORM:
316 return V_028C70_SWAP_STD;
317
318 case PIPE_FORMAT_R16_UNORM:
319 case PIPE_FORMAT_R16_FLOAT:
320 return V_028C70_SWAP_STD;
321
322 /* 32-bit buffers. */
323 case PIPE_FORMAT_A8B8G8R8_SRGB:
324 return V_028C70_SWAP_STD_REV;
325 case PIPE_FORMAT_B8G8R8A8_SRGB:
326 return V_028C70_SWAP_ALT;
327
328 case PIPE_FORMAT_B8G8R8A8_UNORM:
329 case PIPE_FORMAT_B8G8R8X8_UNORM:
330 return V_028C70_SWAP_ALT;
331
332 case PIPE_FORMAT_A8R8G8B8_UNORM:
333 case PIPE_FORMAT_X8R8G8B8_UNORM:
334 return V_028C70_SWAP_ALT_REV;
335 case PIPE_FORMAT_R8G8B8A8_SNORM:
336 case PIPE_FORMAT_R8G8B8A8_UNORM:
337 case PIPE_FORMAT_R8G8B8X8_UNORM:
338 return V_028C70_SWAP_STD;
339
340 case PIPE_FORMAT_A8B8G8R8_UNORM:
341 case PIPE_FORMAT_X8B8G8R8_UNORM:
342 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
343 return V_028C70_SWAP_STD_REV;
344
345 case PIPE_FORMAT_Z24X8_UNORM:
346 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
347 return V_028C70_SWAP_STD;
348
349 case PIPE_FORMAT_X8Z24_UNORM:
350 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
351 return V_028C70_SWAP_STD;
352
353 case PIPE_FORMAT_R10G10B10A2_UNORM:
354 case PIPE_FORMAT_R10G10B10X2_SNORM:
355 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
356 return V_028C70_SWAP_STD;
357
358 case PIPE_FORMAT_B10G10R10A2_UNORM:
359 return V_028C70_SWAP_ALT;
360
361 case PIPE_FORMAT_R11G11B10_FLOAT:
362 case PIPE_FORMAT_R32_FLOAT:
363 case PIPE_FORMAT_R16G16_FLOAT:
364 case PIPE_FORMAT_R16G16_UNORM:
365 return V_028C70_SWAP_STD;
366
367 /* 64-bit buffers. */
368 case PIPE_FORMAT_R32G32_FLOAT:
369 case PIPE_FORMAT_R16G16B16A16_UNORM:
370 case PIPE_FORMAT_R16G16B16A16_SNORM:
371 case PIPE_FORMAT_R16G16B16A16_FLOAT:
372
373 /* 128-bit buffers. */
374 case PIPE_FORMAT_R32G32B32A32_FLOAT:
375 case PIPE_FORMAT_R32G32B32A32_SNORM:
376 case PIPE_FORMAT_R32G32B32A32_UNORM:
377 return V_028C70_SWAP_STD;
378 default:
379 R600_ERR("unsupported colorswap format %d\n", format);
380 return ~0U;
381 }
382 return ~0U;
383 }
384
385 static uint32_t r600_translate_colorformat(enum pipe_format format)
386 {
387 switch (format) {
388 /* 8-bit buffers. */
389 case PIPE_FORMAT_L4A4_UNORM:
390 return V_028C70_COLOR_4_4;
391
392 case PIPE_FORMAT_A8_UNORM:
393 case PIPE_FORMAT_I8_UNORM:
394 case PIPE_FORMAT_L8_UNORM:
395 case PIPE_FORMAT_L8_SRGB:
396 case PIPE_FORMAT_R8_UNORM:
397 case PIPE_FORMAT_R8_SNORM:
398 return V_028C70_COLOR_8;
399
400 /* 16-bit buffers. */
401 case PIPE_FORMAT_B5G6R5_UNORM:
402 return V_028C70_COLOR_5_6_5;
403
404 case PIPE_FORMAT_B5G5R5A1_UNORM:
405 case PIPE_FORMAT_B5G5R5X1_UNORM:
406 return V_028C70_COLOR_1_5_5_5;
407
408 case PIPE_FORMAT_B4G4R4A4_UNORM:
409 case PIPE_FORMAT_B4G4R4X4_UNORM:
410 return V_028C70_COLOR_4_4_4_4;
411
412 case PIPE_FORMAT_Z16_UNORM:
413 return V_028C70_COLOR_16;
414
415 case PIPE_FORMAT_L8A8_UNORM:
416 case PIPE_FORMAT_L8A8_SRGB:
417 case PIPE_FORMAT_R8G8_UNORM:
418 return V_028C70_COLOR_8_8;
419
420 case PIPE_FORMAT_R16_UNORM:
421 return V_028C70_COLOR_16;
422
423 case PIPE_FORMAT_R16_FLOAT:
424 return V_028C70_COLOR_16_FLOAT;
425
426 /* 32-bit buffers. */
427 case PIPE_FORMAT_A8B8G8R8_SRGB:
428 case PIPE_FORMAT_A8B8G8R8_UNORM:
429 case PIPE_FORMAT_A8R8G8B8_UNORM:
430 case PIPE_FORMAT_B8G8R8A8_SRGB:
431 case PIPE_FORMAT_B8G8R8A8_UNORM:
432 case PIPE_FORMAT_B8G8R8X8_UNORM:
433 case PIPE_FORMAT_R8G8B8A8_SNORM:
434 case PIPE_FORMAT_R8G8B8A8_UNORM:
435 case PIPE_FORMAT_R8G8B8X8_UNORM:
436 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
437 case PIPE_FORMAT_X8B8G8R8_UNORM:
438 case PIPE_FORMAT_X8R8G8B8_UNORM:
439 case PIPE_FORMAT_R8G8B8_UNORM:
440 return V_028C70_COLOR_8_8_8_8;
441
442 case PIPE_FORMAT_R10G10B10A2_UNORM:
443 case PIPE_FORMAT_R10G10B10X2_SNORM:
444 case PIPE_FORMAT_B10G10R10A2_UNORM:
445 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
446 return V_028C70_COLOR_2_10_10_10;
447
448 case PIPE_FORMAT_Z24X8_UNORM:
449 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
450 return V_028C70_COLOR_8_24;
451
452 case PIPE_FORMAT_X8Z24_UNORM:
453 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
454 return V_028C70_COLOR_24_8;
455
456 case PIPE_FORMAT_R32_FLOAT:
457 return V_028C70_COLOR_32_FLOAT;
458
459 case PIPE_FORMAT_R16G16_FLOAT:
460 return V_028C70_COLOR_16_16_FLOAT;
461
462 case PIPE_FORMAT_R16G16_SSCALED:
463 case PIPE_FORMAT_R16G16_UNORM:
464 return V_028C70_COLOR_16_16;
465
466 case PIPE_FORMAT_R11G11B10_FLOAT:
467 return V_028C70_COLOR_10_11_11_FLOAT;
468
469 /* 64-bit buffers. */
470 case PIPE_FORMAT_R16G16B16_USCALED:
471 case PIPE_FORMAT_R16G16B16A16_USCALED:
472 case PIPE_FORMAT_R16G16B16_SSCALED:
473 case PIPE_FORMAT_R16G16B16A16_SSCALED:
474 case PIPE_FORMAT_R16G16B16A16_UNORM:
475 case PIPE_FORMAT_R16G16B16A16_SNORM:
476 return V_028C70_COLOR_16_16_16_16;
477
478 case PIPE_FORMAT_R16G16B16_FLOAT:
479 case PIPE_FORMAT_R16G16B16A16_FLOAT:
480 return V_028C70_COLOR_16_16_16_16_FLOAT;
481
482 case PIPE_FORMAT_R32G32_FLOAT:
483 return V_028C70_COLOR_32_32_FLOAT;
484
485 case PIPE_FORMAT_R32G32_USCALED:
486 case PIPE_FORMAT_R32G32_SSCALED:
487 return V_028C70_COLOR_32_32;
488
489 /* 96-bit buffers. */
490 case PIPE_FORMAT_R32G32B32_FLOAT:
491 return V_028C70_COLOR_32_32_32_FLOAT;
492
493 /* 128-bit buffers. */
494 case PIPE_FORMAT_R32G32B32A32_SNORM:
495 case PIPE_FORMAT_R32G32B32A32_UNORM:
496 return V_028C70_COLOR_32_32_32_32;
497 case PIPE_FORMAT_R32G32B32A32_FLOAT:
498 return V_028C70_COLOR_32_32_32_32_FLOAT;
499
500 /* YUV buffers. */
501 case PIPE_FORMAT_UYVY:
502 case PIPE_FORMAT_YUYV:
503 default:
504 return ~0U; /* Unsupported. */
505 }
506 }
507
508 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
509 {
510 if (R600_BIG_ENDIAN) {
511 switch(colorformat) {
512 case V_028C70_COLOR_4_4:
513 return ENDIAN_NONE;
514
515 /* 8-bit buffers. */
516 case V_028C70_COLOR_8:
517 return ENDIAN_NONE;
518
519 /* 16-bit buffers. */
520 case V_028C70_COLOR_5_6_5:
521 case V_028C70_COLOR_1_5_5_5:
522 case V_028C70_COLOR_4_4_4_4:
523 case V_028C70_COLOR_16:
524 case V_028C70_COLOR_8_8:
525 return ENDIAN_8IN16;
526
527 /* 32-bit buffers. */
528 case V_028C70_COLOR_8_8_8_8:
529 case V_028C70_COLOR_2_10_10_10:
530 case V_028C70_COLOR_8_24:
531 case V_028C70_COLOR_24_8:
532 case V_028C70_COLOR_32_FLOAT:
533 case V_028C70_COLOR_16_16_FLOAT:
534 case V_028C70_COLOR_16_16:
535 return ENDIAN_8IN32;
536
537 /* 64-bit buffers. */
538 case V_028C70_COLOR_16_16_16_16:
539 case V_028C70_COLOR_16_16_16_16_FLOAT:
540 return ENDIAN_8IN16;
541
542 case V_028C70_COLOR_32_32_FLOAT:
543 case V_028C70_COLOR_32_32:
544 return ENDIAN_8IN32;
545
546 /* 96-bit buffers. */
547 case V_028C70_COLOR_32_32_32_FLOAT:
548 /* 128-bit buffers. */
549 case V_028C70_COLOR_32_32_32_32_FLOAT:
550 case V_028C70_COLOR_32_32_32_32:
551 return ENDIAN_8IN32;
552 default:
553 return ENDIAN_NONE; /* Unsupported. */
554 }
555 } else {
556 return ENDIAN_NONE;
557 }
558 }
559
560 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
561 {
562 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
563 }
564
565 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
566 {
567 return r600_translate_colorformat(format) != ~0U &&
568 r600_translate_colorswap(format) != ~0U;
569 }
570
571 static bool r600_is_zs_format_supported(enum pipe_format format)
572 {
573 return r600_translate_dbformat(format) != ~0U;
574 }
575
576 boolean evergreen_is_format_supported(struct pipe_screen *screen,
577 enum pipe_format format,
578 enum pipe_texture_target target,
579 unsigned sample_count,
580 unsigned usage)
581 {
582 unsigned retval = 0;
583
584 if (target >= PIPE_MAX_TEXTURE_TYPES) {
585 R600_ERR("r600: unsupported texture type %d\n", target);
586 return FALSE;
587 }
588
589 if (!util_format_is_supported(format, usage))
590 return FALSE;
591
592 /* Multisample */
593 if (sample_count > 1)
594 return FALSE;
595
596 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
597 r600_is_sampler_format_supported(screen, format)) {
598 retval |= PIPE_BIND_SAMPLER_VIEW;
599 }
600
601 if ((usage & (PIPE_BIND_RENDER_TARGET |
602 PIPE_BIND_DISPLAY_TARGET |
603 PIPE_BIND_SCANOUT |
604 PIPE_BIND_SHARED)) &&
605 r600_is_colorbuffer_format_supported(format)) {
606 retval |= usage &
607 (PIPE_BIND_RENDER_TARGET |
608 PIPE_BIND_DISPLAY_TARGET |
609 PIPE_BIND_SCANOUT |
610 PIPE_BIND_SHARED);
611 }
612
613 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
614 r600_is_zs_format_supported(format)) {
615 retval |= PIPE_BIND_DEPTH_STENCIL;
616 }
617
618 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
619 r600_is_vertex_format_supported(format)) {
620 retval |= PIPE_BIND_VERTEX_BUFFER;
621 }
622
623 if (usage & PIPE_BIND_TRANSFER_READ)
624 retval |= PIPE_BIND_TRANSFER_READ;
625 if (usage & PIPE_BIND_TRANSFER_WRITE)
626 retval |= PIPE_BIND_TRANSFER_WRITE;
627
628 return retval == usage;
629 }
630
631 static void evergreen_set_blend_color(struct pipe_context *ctx,
632 const struct pipe_blend_color *state)
633 {
634 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
635 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
636
637 if (rstate == NULL)
638 return;
639
640 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
641 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
642 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
643 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
644 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
645
646 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
647 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
648 r600_context_pipe_state_set(&rctx->ctx, rstate);
649 }
650
651 static void *evergreen_create_blend_state(struct pipe_context *ctx,
652 const struct pipe_blend_state *state)
653 {
654 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
655 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
656 struct r600_pipe_state *rstate;
657 u32 color_control, target_mask;
658 /* FIXME there is more then 8 framebuffer */
659 unsigned blend_cntl[8];
660
661 if (blend == NULL) {
662 return NULL;
663 }
664
665 rstate = &blend->rstate;
666
667 rstate->id = R600_PIPE_STATE_BLEND;
668
669 target_mask = 0;
670 color_control = S_028808_MODE(1);
671 if (state->logicop_enable) {
672 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
673 } else {
674 color_control |= (0xcc << 16);
675 }
676 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
677 if (state->independent_blend_enable) {
678 for (int i = 0; i < 8; i++) {
679 target_mask |= (state->rt[i].colormask << (4 * i));
680 }
681 } else {
682 for (int i = 0; i < 8; i++) {
683 target_mask |= (state->rt[0].colormask << (4 * i));
684 }
685 }
686 blend->cb_target_mask = target_mask;
687
688 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
689 color_control, 0xFFFFFFFD, NULL);
690
691 if (rctx->chip_class != CAYMAN)
692 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
693 else {
694 r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
695 r600_pipe_state_add_reg(rstate, CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
696 }
697
698 for (int i = 0; i < 8; i++) {
699 /* state->rt entries > 0 only written if independent blending */
700 const int j = state->independent_blend_enable ? i : 0;
701
702 unsigned eqRGB = state->rt[j].rgb_func;
703 unsigned srcRGB = state->rt[j].rgb_src_factor;
704 unsigned dstRGB = state->rt[j].rgb_dst_factor;
705 unsigned eqA = state->rt[j].alpha_func;
706 unsigned srcA = state->rt[j].alpha_src_factor;
707 unsigned dstA = state->rt[j].alpha_dst_factor;
708
709 blend_cntl[i] = 0;
710 if (!state->rt[j].blend_enable)
711 continue;
712
713 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
714 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
715 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
716 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
717
718 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
719 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
720 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
721 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
722 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
723 }
724 }
725 for (int i = 0; i < 8; i++) {
726 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
727 }
728
729 return rstate;
730 }
731
732 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
733 const struct pipe_depth_stencil_alpha_state *state)
734 {
735 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
736 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
737 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
738 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
739 struct r600_pipe_state *rstate;
740
741 if (dsa == NULL) {
742 return NULL;
743 }
744
745 rstate = &dsa->rstate;
746
747 rstate->id = R600_PIPE_STATE_DSA;
748 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
749 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
750 stencil_ref_mask = 0;
751 stencil_ref_mask_bf = 0;
752 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
753 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
754 S_028800_ZFUNC(state->depth.func);
755
756 /* stencil */
757 if (state->stencil[0].enabled) {
758 db_depth_control |= S_028800_STENCIL_ENABLE(1);
759 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
760 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
761 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
762 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
763
764
765 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
766 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
767 if (state->stencil[1].enabled) {
768 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
769 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
770 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
771 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
772 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
773 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
774 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
775 }
776 }
777
778 /* alpha */
779 alpha_test_control = 0;
780 alpha_ref = 0;
781 if (state->alpha.enabled) {
782 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
783 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
784 alpha_ref = fui(state->alpha.ref_value);
785 }
786 dsa->alpha_ref = alpha_ref;
787
788 /* misc */
789 db_render_control = 0;
790 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
791 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
792 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
793 /* TODO db_render_override depends on query */
794 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
795 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
796 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
797 r600_pipe_state_add_reg(rstate,
798 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
799 0xFFFFFFFF & C_028430_STENCILREF, NULL);
800 r600_pipe_state_add_reg(rstate,
801 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
802 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
803 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
804 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
805 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
806 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
807 * evergreen_pipe_shader_ps().*/
808 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
809 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
810 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
811 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
812 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
813 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
814 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
815
816 return rstate;
817 }
818
819 static void *evergreen_create_rs_state(struct pipe_context *ctx,
820 const struct pipe_rasterizer_state *state)
821 {
822 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
823 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
824 struct r600_pipe_state *rstate;
825 unsigned tmp;
826 unsigned prov_vtx = 1, polygon_dual_mode;
827 unsigned clip_rule;
828
829 if (rs == NULL) {
830 return NULL;
831 }
832
833 rstate = &rs->rstate;
834 rs->clamp_vertex_color = state->clamp_vertex_color;
835 rs->clamp_fragment_color = state->clamp_fragment_color;
836 rs->flatshade = state->flatshade;
837 rs->sprite_coord_enable = state->sprite_coord_enable;
838
839 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
840
841 /* offset */
842 rs->offset_units = state->offset_units;
843 rs->offset_scale = state->offset_scale * 12.0f;
844
845 rstate->id = R600_PIPE_STATE_RASTERIZER;
846 if (state->flatshade_first)
847 prov_vtx = 0;
848 tmp = S_0286D4_FLAT_SHADE_ENA(1);
849 if (state->sprite_coord_enable) {
850 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
851 S_0286D4_PNT_SPRITE_OVRD_X(2) |
852 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
853 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
854 S_0286D4_PNT_SPRITE_OVRD_W(1);
855 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
856 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
857 }
858 }
859 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
860
861 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
862 state->fill_back != PIPE_POLYGON_MODE_FILL);
863 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
864 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
865 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
866 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
867 S_028814_FACE(!state->front_ccw) |
868 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
869 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
870 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
871 S_028814_POLY_MODE(polygon_dual_mode) |
872 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
873 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
874 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
875 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
876 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
877 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
878 /* point size 12.4 fixed point */
879 tmp = (unsigned)(state->point_size * 8.0);
880 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
881 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
882
883 tmp = (unsigned)state->line_width * 8;
884 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
885
886 if (rctx->chip_class == CAYMAN) {
887 r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
888 r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
889 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
890 0xFFFFFFFF, NULL);
891 r600_pipe_state_add_reg(rstate, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
892 r600_pipe_state_add_reg(rstate, CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
893 r600_pipe_state_add_reg(rstate, CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
894 r600_pipe_state_add_reg(rstate, CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
895
896
897 } else {
898 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
899
900 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
901 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
902 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
903 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
904
905 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
906 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
907 0xFFFFFFFF, NULL);
908 }
909 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
910 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
911 return rstate;
912 }
913
914 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
915 const struct pipe_sampler_state *state)
916 {
917 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
918 union util_color uc;
919 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
920
921 if (rstate == NULL) {
922 return NULL;
923 }
924
925 rstate->id = R600_PIPE_STATE_SAMPLER;
926 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
927 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
928 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
929 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
930 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
931 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
932 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
933 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
934 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
935 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
936 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
937 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
938 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
939 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
940 0xFFFFFFFF, NULL);
941 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
942 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
943 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
944 S_03C008_TYPE(1),
945 0xFFFFFFFF, NULL);
946
947 if (uc.ui) {
948 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
949 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
950 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
951 r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
952 }
953 return rstate;
954 }
955
956 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
957 struct pipe_resource *texture,
958 const struct pipe_sampler_view *state)
959 {
960 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
961 struct r600_pipe_resource_state *rstate;
962 const struct util_format_description *desc;
963 struct r600_resource_texture *tmp;
964 struct r600_resource *rbuffer;
965 unsigned format, endian;
966 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
967 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
968 struct r600_bo *bo[2];
969
970 if (resource == NULL)
971 return NULL;
972 rstate = &resource->state;
973
974 /* initialize base object */
975 resource->base = *state;
976 resource->base.texture = NULL;
977 pipe_reference(NULL, &texture->reference);
978 resource->base.texture = texture;
979 resource->base.reference.count = 1;
980 resource->base.context = ctx;
981
982 swizzle[0] = state->swizzle_r;
983 swizzle[1] = state->swizzle_g;
984 swizzle[2] = state->swizzle_b;
985 swizzle[3] = state->swizzle_a;
986 format = r600_translate_texformat(ctx->screen, state->format,
987 swizzle,
988 &word4, &yuv_format);
989 if (format == ~0) {
990 format = 0;
991 }
992 desc = util_format_description(state->format);
993 if (desc == NULL) {
994 R600_ERR("unknow format %d\n", state->format);
995 }
996 tmp = (struct r600_resource_texture *)texture;
997 if (tmp->depth && !tmp->is_flushing_texture) {
998 r600_texture_depth_flush(ctx, texture, TRUE);
999 tmp = tmp->flushed_depth_texture;
1000 }
1001
1002 endian = r600_colorformat_endian_swap(format);
1003
1004 if (tmp->force_int_type) {
1005 word4 &= C_030010_NUM_FORMAT_ALL;
1006 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT);
1007 }
1008
1009 rbuffer = &tmp->resource;
1010 bo[0] = rbuffer->bo;
1011 bo[1] = rbuffer->bo;
1012
1013 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8);
1014 array_mode = tmp->array_mode[0];
1015 tile_type = tmp->tile_type;
1016
1017 rstate->bo[0] = bo[0];
1018 rstate->bo[1] = bo[1];
1019 rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1020 S_030000_PITCH((pitch / 8) - 1) |
1021 S_030000_NON_DISP_TILING_ORDER(tile_type) |
1022 S_030000_TEX_WIDTH(texture->width0 - 1));
1023 rstate->val[1] = (S_030004_TEX_HEIGHT(texture->height0 - 1) |
1024 S_030004_TEX_DEPTH(texture->depth0 - 1) |
1025 S_030004_ARRAY_MODE(array_mode));
1026 rstate->val[2] = (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8;
1027 rstate->val[3] = (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8;
1028 rstate->val[4] = (word4 |
1029 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1030 S_030010_ENDIAN_SWAP(endian) |
1031 S_030010_BASE_LEVEL(state->u.tex.first_level));
1032 rstate->val[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1033 S_030014_BASE_ARRAY(0) |
1034 S_030014_LAST_ARRAY(0));
1035 rstate->val[6] = (S_030018_MAX_ANISO(4 /* max 16 samples */));
1036 rstate->val[7] = (S_03001C_DATA_FORMAT(format) |
1037 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE));
1038
1039 return &resource->base;
1040 }
1041
1042 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1043 struct pipe_sampler_view **views)
1044 {
1045 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1046 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1047
1048 for (int i = 0; i < count; i++) {
1049 if (resource[i]) {
1050 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1051 i + R600_MAX_CONST_BUFFERS);
1052 }
1053 }
1054 }
1055
1056 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1057 struct pipe_sampler_view **views)
1058 {
1059 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1060 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1061 int i;
1062 int has_depth = 0;
1063
1064 for (i = 0; i < count; i++) {
1065 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1066 if (resource[i]) {
1067 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1068 has_depth = 1;
1069 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1070 i + R600_MAX_CONST_BUFFERS);
1071 } else
1072 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1073 i + R600_MAX_CONST_BUFFERS);
1074
1075 pipe_sampler_view_reference(
1076 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1077 views[i]);
1078 } else {
1079 if (resource[i]) {
1080 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1081 has_depth = 1;
1082 }
1083 }
1084 }
1085 for (i = count; i < NUM_TEX_UNITS; i++) {
1086 if (rctx->ps_samplers.views[i]) {
1087 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1088 i + R600_MAX_CONST_BUFFERS);
1089 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1090 }
1091 }
1092 rctx->have_depth_texture = has_depth;
1093 rctx->ps_samplers.n_views = count;
1094 }
1095
1096 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1097 {
1098 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1099 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1100
1101
1102 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1103 rctx->ps_samplers.n_samplers = count;
1104
1105 for (int i = 0; i < count; i++) {
1106 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
1107 }
1108 }
1109
1110 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1111 {
1112 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1113 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
1114
1115 for (int i = 0; i < count; i++) {
1116 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
1117 }
1118 }
1119
1120 static void evergreen_set_clip_state(struct pipe_context *ctx,
1121 const struct pipe_clip_state *state)
1122 {
1123 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1124 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1125
1126 if (rstate == NULL)
1127 return;
1128
1129 rctx->clip = *state;
1130 rstate->id = R600_PIPE_STATE_CLIP;
1131 for (int i = 0; i < state->nr; i++) {
1132 r600_pipe_state_add_reg(rstate,
1133 R_0285BC_PA_CL_UCP0_X + i * 16,
1134 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
1135 r600_pipe_state_add_reg(rstate,
1136 R_0285C0_PA_CL_UCP0_Y + i * 16,
1137 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
1138 r600_pipe_state_add_reg(rstate,
1139 R_0285C4_PA_CL_UCP0_Z + i * 16,
1140 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
1141 r600_pipe_state_add_reg(rstate,
1142 R_0285C8_PA_CL_UCP0_W + i * 16,
1143 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
1144 }
1145 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1146 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1147 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1148 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
1149
1150 free(rctx->states[R600_PIPE_STATE_CLIP]);
1151 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1152 r600_context_pipe_state_set(&rctx->ctx, rstate);
1153 }
1154
1155 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1156 const struct pipe_poly_stipple *state)
1157 {
1158 }
1159
1160 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1161 {
1162 }
1163
1164 static void evergreen_set_scissor_state(struct pipe_context *ctx,
1165 const struct pipe_scissor_state *state)
1166 {
1167 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1168 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1169 u32 tl, br;
1170
1171 if (rstate == NULL)
1172 return;
1173
1174 rstate->id = R600_PIPE_STATE_SCISSOR;
1175 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
1176 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1177 r600_pipe_state_add_reg(rstate,
1178 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1179 0xFFFFFFFF, NULL);
1180 r600_pipe_state_add_reg(rstate,
1181 R_028214_PA_SC_CLIPRECT_0_BR, br,
1182 0xFFFFFFFF, NULL);
1183 r600_pipe_state_add_reg(rstate,
1184 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1185 0xFFFFFFFF, NULL);
1186 r600_pipe_state_add_reg(rstate,
1187 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1188 0xFFFFFFFF, NULL);
1189 r600_pipe_state_add_reg(rstate,
1190 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1191 0xFFFFFFFF, NULL);
1192 r600_pipe_state_add_reg(rstate,
1193 R_028224_PA_SC_CLIPRECT_2_BR, br,
1194 0xFFFFFFFF, NULL);
1195 r600_pipe_state_add_reg(rstate,
1196 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1197 0xFFFFFFFF, NULL);
1198 r600_pipe_state_add_reg(rstate,
1199 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1200 0xFFFFFFFF, NULL);
1201
1202 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1203 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1204 r600_context_pipe_state_set(&rctx->ctx, rstate);
1205 }
1206
1207 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
1208 const struct pipe_stencil_ref *state)
1209 {
1210 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1211 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1212 u32 tmp;
1213
1214 if (rstate == NULL)
1215 return;
1216
1217 rctx->stencil_ref = *state;
1218 rstate->id = R600_PIPE_STATE_STENCIL_REF;
1219 tmp = S_028430_STENCILREF(state->ref_value[0]);
1220 r600_pipe_state_add_reg(rstate,
1221 R_028430_DB_STENCILREFMASK, tmp,
1222 ~C_028430_STENCILREF, NULL);
1223 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1224 r600_pipe_state_add_reg(rstate,
1225 R_028434_DB_STENCILREFMASK_BF, tmp,
1226 ~C_028434_STENCILREF_BF, NULL);
1227
1228 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1229 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1230 r600_context_pipe_state_set(&rctx->ctx, rstate);
1231 }
1232
1233 static void evergreen_set_viewport_state(struct pipe_context *ctx,
1234 const struct pipe_viewport_state *state)
1235 {
1236 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1237 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1238
1239 if (rstate == NULL)
1240 return;
1241
1242 rctx->viewport = *state;
1243 rstate->id = R600_PIPE_STATE_VIEWPORT;
1244 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
1245 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
1246 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
1247 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
1248 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
1249 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
1250 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
1251 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
1252 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
1253
1254 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1255 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1256 r600_context_pipe_state_set(&rctx->ctx, rstate);
1257 }
1258
1259 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1260 const struct pipe_framebuffer_state *state, int cb)
1261 {
1262 struct r600_resource_texture *rtex;
1263 struct r600_resource *rbuffer;
1264 struct r600_surface *surf;
1265 unsigned level = state->cbufs[cb]->u.tex.level;
1266 unsigned pitch, slice;
1267 unsigned color_info;
1268 unsigned format, swap, ntype, endian;
1269 unsigned offset;
1270 unsigned tile_type;
1271 const struct util_format_description *desc;
1272 struct r600_bo *bo[3];
1273 int i;
1274
1275 surf = (struct r600_surface *)state->cbufs[cb];
1276 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1277
1278 if (rtex->depth)
1279 rctx->have_depth_fb = TRUE;
1280
1281 if (rtex->depth && !rtex->is_flushing_texture) {
1282 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1283 rtex = rtex->flushed_depth_texture;
1284 }
1285
1286 rbuffer = &rtex->resource;
1287 bo[0] = rbuffer->bo;
1288 bo[1] = rbuffer->bo;
1289 bo[2] = rbuffer->bo;
1290
1291 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1292 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
1293 level, state->cbufs[cb]->u.tex.first_layer);
1294 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1295 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1296 desc = util_format_description(surf->base.format);
1297 for (i = 0; i < 4; i++) {
1298 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1299 break;
1300 }
1301 }
1302 ntype = V_028C70_NUMBER_UNORM;
1303 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1304 ntype = V_028C70_NUMBER_SRGB;
1305 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
1306 ntype = V_028C70_NUMBER_SNORM;
1307
1308 format = r600_translate_colorformat(surf->base.format);
1309 swap = r600_translate_colorswap(surf->base.format);
1310 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
1311 endian = ENDIAN_NONE;
1312 } else {
1313 endian = r600_colorformat_endian_swap(format);
1314 }
1315
1316 /* disable when gallium grows int textures */
1317 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
1318 ntype = V_028C70_NUMBER_UINT;
1319
1320 color_info = S_028C70_FORMAT(format) |
1321 S_028C70_COMP_SWAP(swap) |
1322 S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
1323 S_028C70_BLEND_CLAMP(1) |
1324 S_028C70_NUMBER_TYPE(ntype) |
1325 S_028C70_ENDIAN(endian);
1326
1327
1328 /* EXPORT_NORM is an optimzation that can be enabled for better
1329 * performance in certain cases.
1330 * EXPORT_NORM can be enabled if:
1331 * - 11-bit or smaller UNORM/SNORM/SRGB
1332 * - 16-bit or smaller FLOAT
1333 */
1334 /* FIXME: This should probably be the same for all CBs if we want
1335 * useful alpha tests. */
1336 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1337 ((desc->channel[i].size < 12 &&
1338 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1339 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1340 (desc->channel[i].size < 17 &&
1341 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1342 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1343 rctx->export_16bpc = true;
1344 } else {
1345 rctx->export_16bpc = false;
1346 }
1347 rctx->alpha_ref_dirty = true;
1348
1349 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1350 tile_type = rtex->tile_type;
1351 } else /* workaround for linear buffers */
1352 tile_type = 1;
1353
1354 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1355 r600_pipe_state_add_reg(rstate,
1356 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1357 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
1358 r600_pipe_state_add_reg(rstate,
1359 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1360 0x0, 0xFFFFFFFF, NULL);
1361 r600_pipe_state_add_reg(rstate,
1362 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1363 color_info, 0xFFFFFFFF, bo[0]);
1364 r600_pipe_state_add_reg(rstate,
1365 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1366 S_028C64_PITCH_TILE_MAX(pitch),
1367 0xFFFFFFFF, NULL);
1368 r600_pipe_state_add_reg(rstate,
1369 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1370 S_028C68_SLICE_TILE_MAX(slice),
1371 0xFFFFFFFF, NULL);
1372 r600_pipe_state_add_reg(rstate,
1373 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1374 0x00000000, 0xFFFFFFFF, NULL);
1375 r600_pipe_state_add_reg(rstate,
1376 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1377 S_028C74_NON_DISP_TILING_ORDER(tile_type),
1378 0xFFFFFFFF, bo[0]);
1379 }
1380
1381 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1382 const struct pipe_framebuffer_state *state)
1383 {
1384 struct r600_resource_texture *rtex;
1385 struct r600_resource *rbuffer;
1386 struct r600_surface *surf;
1387 unsigned level;
1388 unsigned pitch, slice, format, stencil_format;
1389 unsigned offset;
1390
1391 if (state->zsbuf == NULL)
1392 return;
1393
1394 level = state->zsbuf->u.tex.level;
1395
1396 surf = (struct r600_surface *)state->zsbuf;
1397 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1398
1399 rbuffer = &rtex->resource;
1400
1401 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1402 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1403 level, state->zsbuf->u.tex.first_layer);
1404 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1405 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1406 format = r600_translate_dbformat(state->zsbuf->texture->format);
1407 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
1408
1409 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
1410 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1411 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
1412 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1413
1414 if (stencil_format) {
1415 uint32_t stencil_offset;
1416
1417 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
1418 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
1419 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1420 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1421 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1422 }
1423
1424 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1425 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
1426 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
1427
1428 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
1429 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
1430 0xFFFFFFFF, rbuffer->bo);
1431 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1432 S_028058_PITCH_TILE_MAX(pitch),
1433 0xFFFFFFFF, NULL);
1434 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1435 S_02805C_SLICE_TILE_MAX(slice),
1436 0xFFFFFFFF, NULL);
1437 }
1438
1439 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1440 const struct pipe_framebuffer_state *state)
1441 {
1442 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1443 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1444 u32 shader_mask, tl, br, target_mask;
1445 int tl_x, tl_y, br_x, br_y;
1446
1447 if (rstate == NULL)
1448 return;
1449
1450 evergreen_context_flush_dest_caches(&rctx->ctx);
1451 rctx->ctx.num_dest_buffers = state->nr_cbufs;
1452
1453 /* unreference old buffer and reference new one */
1454 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1455
1456 util_copy_framebuffer_state(&rctx->framebuffer, state);
1457
1458 /* build states */
1459 rctx->have_depth_fb = 0;
1460 rctx->nr_cbufs = state->nr_cbufs;
1461 for (int i = 0; i < state->nr_cbufs; i++) {
1462 evergreen_cb(rctx, rstate, state, i);
1463 }
1464 if (state->zsbuf) {
1465 evergreen_db(rctx, rstate, state);
1466 rctx->ctx.num_dest_buffers++;
1467 }
1468
1469 target_mask = 0x00000000;
1470 target_mask = 0xFFFFFFFF;
1471 shader_mask = 0;
1472 for (int i = 0; i < state->nr_cbufs; i++) {
1473 target_mask ^= 0xf << (i * 4);
1474 shader_mask |= 0xf << (i * 4);
1475 }
1476 tl_x = 0;
1477 tl_y = 0;
1478 br_x = state->width;
1479 br_y = state->height;
1480 /* EG hw workaround */
1481 if (br_x == 0)
1482 tl_x = 1;
1483 if (br_y == 0)
1484 tl_y = 1;
1485 /* cayman hw workaround */
1486 if (rctx->chip_class == CAYMAN) {
1487 if (br_x == 1 && br_y == 1)
1488 br_x = 2;
1489 }
1490 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1491 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1492
1493 r600_pipe_state_add_reg(rstate,
1494 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1495 0xFFFFFFFF, NULL);
1496 r600_pipe_state_add_reg(rstate,
1497 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1498 0xFFFFFFFF, NULL);
1499 r600_pipe_state_add_reg(rstate,
1500 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1501 0xFFFFFFFF, NULL);
1502 r600_pipe_state_add_reg(rstate,
1503 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1504 0xFFFFFFFF, NULL);
1505 r600_pipe_state_add_reg(rstate,
1506 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1507 0xFFFFFFFF, NULL);
1508 r600_pipe_state_add_reg(rstate,
1509 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1510 0xFFFFFFFF, NULL);
1511 r600_pipe_state_add_reg(rstate,
1512 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1513 0xFFFFFFFF, NULL);
1514 r600_pipe_state_add_reg(rstate,
1515 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1516 0xFFFFFFFF, NULL);
1517 r600_pipe_state_add_reg(rstate,
1518 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1519 0xFFFFFFFF, NULL);
1520 r600_pipe_state_add_reg(rstate,
1521 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1522 0xFFFFFFFF, NULL);
1523
1524 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1525 0x00000000, target_mask, NULL);
1526 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1527 shader_mask, 0xFFFFFFFF, NULL);
1528
1529
1530 if (rctx->chip_class == CAYMAN) {
1531 r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1532 0x00000000, 0xFFFFFFFF, NULL);
1533 } else {
1534 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1535 0x00000000, 0xFFFFFFFF, NULL);
1536 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1537 0x00000000, 0xFFFFFFFF, NULL);
1538 }
1539
1540 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1541 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1542 r600_context_pipe_state_set(&rctx->ctx, rstate);
1543
1544 if (state->zsbuf) {
1545 evergreen_polygon_offset_update(rctx);
1546 }
1547 }
1548
1549 static void evergreen_texture_barrier(struct pipe_context *ctx)
1550 {
1551 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1552
1553 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1554 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1555 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1556 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1557 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) |
1558 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) |
1559 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1));
1560 }
1561
1562 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
1563 {
1564 rctx->context.create_blend_state = evergreen_create_blend_state;
1565 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1566 rctx->context.create_fs_state = r600_create_shader_state;
1567 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1568 rctx->context.create_sampler_state = evergreen_create_sampler_state;
1569 rctx->context.create_sampler_view = evergreen_create_sampler_view;
1570 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1571 rctx->context.create_vs_state = r600_create_shader_state;
1572 rctx->context.bind_blend_state = r600_bind_blend_state;
1573 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1574 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
1575 rctx->context.bind_fs_state = r600_bind_ps_shader;
1576 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1577 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1578 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
1579 rctx->context.bind_vs_state = r600_bind_vs_shader;
1580 rctx->context.delete_blend_state = r600_delete_state;
1581 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1582 rctx->context.delete_fs_state = r600_delete_ps_shader;
1583 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1584 rctx->context.delete_sampler_state = r600_delete_state;
1585 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1586 rctx->context.delete_vs_state = r600_delete_vs_shader;
1587 rctx->context.set_blend_color = evergreen_set_blend_color;
1588 rctx->context.set_clip_state = evergreen_set_clip_state;
1589 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1590 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
1591 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1592 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1593 rctx->context.set_sample_mask = evergreen_set_sample_mask;
1594 rctx->context.set_scissor_state = evergreen_set_scissor_state;
1595 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
1596 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1597 rctx->context.set_index_buffer = r600_set_index_buffer;
1598 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
1599 rctx->context.set_viewport_state = evergreen_set_viewport_state;
1600 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1601 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1602 rctx->context.texture_barrier = evergreen_texture_barrier;
1603 }
1604
1605 static void cayman_init_config(struct r600_pipe_context *rctx)
1606 {
1607 struct r600_pipe_state *rstate = &rctx->config;
1608 unsigned tmp;
1609
1610 tmp = 0x00000000;
1611 tmp |= S_008C00_EXPORT_SRC_C(1);
1612 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1613
1614 /* always set the temp clauses */
1615 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, S_008C04_NUM_CLAUSE_TEMP_GPRS(4), 0xFFFFFFFF, NULL);
1616 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL);
1617 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL);
1618 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL);
1619
1620 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1621 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1622
1623 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1624 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1625 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1626 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1627 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1628 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1629 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1630 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1631 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1632 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1633 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1634 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1635 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1636 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1637 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1638 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1639 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1640 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1641
1642 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1643 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1644 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1645 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1646 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1647 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1648 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1649 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1650 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1651 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1652 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1653 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1654 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1655 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1656 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1657 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1658 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1659 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1660 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1661 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1662 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1663 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1664 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1665 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1666 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1667 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1668 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1669 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1670 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1671 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1672 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1673 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1674
1675 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
1676
1677 r600_pipe_state_add_reg(rstate, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, 0xffffffff, 0);
1678 r600_pipe_state_add_reg(rstate, CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, 0xffffffff, 0);
1679
1680 r600_pipe_state_add_reg(rstate, CM_R_0288E8_SQ_LDS_ALLOC, 0, 0xffffffff, NULL);
1681 r600_pipe_state_add_reg(rstate, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0xffffffff, NULL);
1682
1683 r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA, 0x110000, 0xffffffff, NULL);
1684 r600_context_pipe_state_set(&rctx->ctx, rstate);
1685 }
1686
1687 void evergreen_init_config(struct r600_pipe_context *rctx)
1688 {
1689 struct r600_pipe_state *rstate = &rctx->config;
1690 int ps_prio;
1691 int vs_prio;
1692 int gs_prio;
1693 int es_prio;
1694 int hs_prio, cs_prio, ls_prio;
1695 int num_ps_gprs;
1696 int num_vs_gprs;
1697 int num_gs_gprs;
1698 int num_es_gprs;
1699 int num_hs_gprs;
1700 int num_ls_gprs;
1701 int num_temp_gprs;
1702 int num_ps_threads;
1703 int num_vs_threads;
1704 int num_gs_threads;
1705 int num_es_threads;
1706 int num_hs_threads;
1707 int num_ls_threads;
1708 int num_ps_stack_entries;
1709 int num_vs_stack_entries;
1710 int num_gs_stack_entries;
1711 int num_es_stack_entries;
1712 int num_hs_stack_entries;
1713 int num_ls_stack_entries;
1714 enum radeon_family family;
1715 unsigned tmp;
1716
1717 family = rctx->family;
1718
1719 if (rctx->chip_class == CAYMAN) {
1720 cayman_init_config(rctx);
1721 return;
1722 }
1723
1724 ps_prio = 0;
1725 vs_prio = 1;
1726 gs_prio = 2;
1727 es_prio = 3;
1728 hs_prio = 0;
1729 ls_prio = 0;
1730 cs_prio = 0;
1731
1732 switch (family) {
1733 case CHIP_CEDAR:
1734 default:
1735 num_ps_gprs = 93;
1736 num_vs_gprs = 46;
1737 num_temp_gprs = 4;
1738 num_gs_gprs = 31;
1739 num_es_gprs = 31;
1740 num_hs_gprs = 23;
1741 num_ls_gprs = 23;
1742 num_ps_threads = 96;
1743 num_vs_threads = 16;
1744 num_gs_threads = 16;
1745 num_es_threads = 16;
1746 num_hs_threads = 16;
1747 num_ls_threads = 16;
1748 num_ps_stack_entries = 42;
1749 num_vs_stack_entries = 42;
1750 num_gs_stack_entries = 42;
1751 num_es_stack_entries = 42;
1752 num_hs_stack_entries = 42;
1753 num_ls_stack_entries = 42;
1754 break;
1755 case CHIP_REDWOOD:
1756 num_ps_gprs = 93;
1757 num_vs_gprs = 46;
1758 num_temp_gprs = 4;
1759 num_gs_gprs = 31;
1760 num_es_gprs = 31;
1761 num_hs_gprs = 23;
1762 num_ls_gprs = 23;
1763 num_ps_threads = 128;
1764 num_vs_threads = 20;
1765 num_gs_threads = 20;
1766 num_es_threads = 20;
1767 num_hs_threads = 20;
1768 num_ls_threads = 20;
1769 num_ps_stack_entries = 42;
1770 num_vs_stack_entries = 42;
1771 num_gs_stack_entries = 42;
1772 num_es_stack_entries = 42;
1773 num_hs_stack_entries = 42;
1774 num_ls_stack_entries = 42;
1775 break;
1776 case CHIP_JUNIPER:
1777 num_ps_gprs = 93;
1778 num_vs_gprs = 46;
1779 num_temp_gprs = 4;
1780 num_gs_gprs = 31;
1781 num_es_gprs = 31;
1782 num_hs_gprs = 23;
1783 num_ls_gprs = 23;
1784 num_ps_threads = 128;
1785 num_vs_threads = 20;
1786 num_gs_threads = 20;
1787 num_es_threads = 20;
1788 num_hs_threads = 20;
1789 num_ls_threads = 20;
1790 num_ps_stack_entries = 85;
1791 num_vs_stack_entries = 85;
1792 num_gs_stack_entries = 85;
1793 num_es_stack_entries = 85;
1794 num_hs_stack_entries = 85;
1795 num_ls_stack_entries = 85;
1796 break;
1797 case CHIP_CYPRESS:
1798 case CHIP_HEMLOCK:
1799 num_ps_gprs = 93;
1800 num_vs_gprs = 46;
1801 num_temp_gprs = 4;
1802 num_gs_gprs = 31;
1803 num_es_gprs = 31;
1804 num_hs_gprs = 23;
1805 num_ls_gprs = 23;
1806 num_ps_threads = 128;
1807 num_vs_threads = 20;
1808 num_gs_threads = 20;
1809 num_es_threads = 20;
1810 num_hs_threads = 20;
1811 num_ls_threads = 20;
1812 num_ps_stack_entries = 85;
1813 num_vs_stack_entries = 85;
1814 num_gs_stack_entries = 85;
1815 num_es_stack_entries = 85;
1816 num_hs_stack_entries = 85;
1817 num_ls_stack_entries = 85;
1818 break;
1819 case CHIP_PALM:
1820 num_ps_gprs = 93;
1821 num_vs_gprs = 46;
1822 num_temp_gprs = 4;
1823 num_gs_gprs = 31;
1824 num_es_gprs = 31;
1825 num_hs_gprs = 23;
1826 num_ls_gprs = 23;
1827 num_ps_threads = 96;
1828 num_vs_threads = 16;
1829 num_gs_threads = 16;
1830 num_es_threads = 16;
1831 num_hs_threads = 16;
1832 num_ls_threads = 16;
1833 num_ps_stack_entries = 42;
1834 num_vs_stack_entries = 42;
1835 num_gs_stack_entries = 42;
1836 num_es_stack_entries = 42;
1837 num_hs_stack_entries = 42;
1838 num_ls_stack_entries = 42;
1839 break;
1840 case CHIP_SUMO:
1841 num_ps_gprs = 93;
1842 num_vs_gprs = 46;
1843 num_temp_gprs = 4;
1844 num_gs_gprs = 31;
1845 num_es_gprs = 31;
1846 num_hs_gprs = 23;
1847 num_ls_gprs = 23;
1848 num_ps_threads = 96;
1849 num_vs_threads = 25;
1850 num_gs_threads = 25;
1851 num_es_threads = 25;
1852 num_hs_threads = 25;
1853 num_ls_threads = 25;
1854 num_ps_stack_entries = 42;
1855 num_vs_stack_entries = 42;
1856 num_gs_stack_entries = 42;
1857 num_es_stack_entries = 42;
1858 num_hs_stack_entries = 42;
1859 num_ls_stack_entries = 42;
1860 break;
1861 case CHIP_SUMO2:
1862 num_ps_gprs = 93;
1863 num_vs_gprs = 46;
1864 num_temp_gprs = 4;
1865 num_gs_gprs = 31;
1866 num_es_gprs = 31;
1867 num_hs_gprs = 23;
1868 num_ls_gprs = 23;
1869 num_ps_threads = 96;
1870 num_vs_threads = 25;
1871 num_gs_threads = 25;
1872 num_es_threads = 25;
1873 num_hs_threads = 25;
1874 num_ls_threads = 25;
1875 num_ps_stack_entries = 85;
1876 num_vs_stack_entries = 85;
1877 num_gs_stack_entries = 85;
1878 num_es_stack_entries = 85;
1879 num_hs_stack_entries = 85;
1880 num_ls_stack_entries = 85;
1881 break;
1882 case CHIP_BARTS:
1883 num_ps_gprs = 93;
1884 num_vs_gprs = 46;
1885 num_temp_gprs = 4;
1886 num_gs_gprs = 31;
1887 num_es_gprs = 31;
1888 num_hs_gprs = 23;
1889 num_ls_gprs = 23;
1890 num_ps_threads = 128;
1891 num_vs_threads = 20;
1892 num_gs_threads = 20;
1893 num_es_threads = 20;
1894 num_hs_threads = 20;
1895 num_ls_threads = 20;
1896 num_ps_stack_entries = 85;
1897 num_vs_stack_entries = 85;
1898 num_gs_stack_entries = 85;
1899 num_es_stack_entries = 85;
1900 num_hs_stack_entries = 85;
1901 num_ls_stack_entries = 85;
1902 break;
1903 case CHIP_TURKS:
1904 num_ps_gprs = 93;
1905 num_vs_gprs = 46;
1906 num_temp_gprs = 4;
1907 num_gs_gprs = 31;
1908 num_es_gprs = 31;
1909 num_hs_gprs = 23;
1910 num_ls_gprs = 23;
1911 num_ps_threads = 128;
1912 num_vs_threads = 20;
1913 num_gs_threads = 20;
1914 num_es_threads = 20;
1915 num_hs_threads = 20;
1916 num_ls_threads = 20;
1917 num_ps_stack_entries = 42;
1918 num_vs_stack_entries = 42;
1919 num_gs_stack_entries = 42;
1920 num_es_stack_entries = 42;
1921 num_hs_stack_entries = 42;
1922 num_ls_stack_entries = 42;
1923 break;
1924 case CHIP_CAICOS:
1925 num_ps_gprs = 93;
1926 num_vs_gprs = 46;
1927 num_temp_gprs = 4;
1928 num_gs_gprs = 31;
1929 num_es_gprs = 31;
1930 num_hs_gprs = 23;
1931 num_ls_gprs = 23;
1932 num_ps_threads = 128;
1933 num_vs_threads = 10;
1934 num_gs_threads = 10;
1935 num_es_threads = 10;
1936 num_hs_threads = 10;
1937 num_ls_threads = 10;
1938 num_ps_stack_entries = 42;
1939 num_vs_stack_entries = 42;
1940 num_gs_stack_entries = 42;
1941 num_es_stack_entries = 42;
1942 num_hs_stack_entries = 42;
1943 num_ls_stack_entries = 42;
1944 break;
1945 }
1946
1947 tmp = 0x00000000;
1948 switch (family) {
1949 case CHIP_CEDAR:
1950 case CHIP_PALM:
1951 case CHIP_SUMO:
1952 case CHIP_SUMO2:
1953 case CHIP_CAICOS:
1954 break;
1955 default:
1956 tmp |= S_008C00_VC_ENABLE(1);
1957 break;
1958 }
1959 tmp |= S_008C00_EXPORT_SRC_C(1);
1960 tmp |= S_008C00_CS_PRIO(cs_prio);
1961 tmp |= S_008C00_LS_PRIO(ls_prio);
1962 tmp |= S_008C00_HS_PRIO(hs_prio);
1963 tmp |= S_008C00_PS_PRIO(ps_prio);
1964 tmp |= S_008C00_VS_PRIO(vs_prio);
1965 tmp |= S_008C00_GS_PRIO(gs_prio);
1966 tmp |= S_008C00_ES_PRIO(es_prio);
1967 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1968
1969 /* enable dynamic GPR resource management */
1970 if (r600_get_minor_version(rctx->radeon) >= 7) {
1971 /* always set temp clauses */
1972 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
1973 S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL);
1974 r600_pipe_state_add_reg(rstate, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 0, 0xFFFFFFFF, NULL);
1975 r600_pipe_state_add_reg(rstate, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0, 0xFFFFFFFF, NULL);
1976 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8), 0xFFFFFFFF, NULL);
1977 r600_pipe_state_add_reg(rstate, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
1978 S_028838_PS_GPRS(0x1e) |
1979 S_028838_VS_GPRS(0x1e) |
1980 S_028838_GS_GPRS(0x1e) |
1981 S_028838_ES_GPRS(0x1e) |
1982 S_028838_HS_GPRS(0x1e) |
1983 S_028838_LS_GPRS(0x1e), 0xFFFFFFFF, NULL); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
1984 } else {
1985 tmp = 0;
1986 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1987 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1988 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1989 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1990
1991 tmp = 0;
1992 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1993 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1994 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1995
1996 tmp = 0;
1997 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1998 tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
1999 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
2000 }
2001
2002 tmp = 0;
2003 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
2004 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2005 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2006 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2007 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
2008
2009 tmp = 0;
2010 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
2011 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2012 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
2013
2014 tmp = 0;
2015 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2016 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2017 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
2018
2019 tmp = 0;
2020 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2021 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2022 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
2023
2024 tmp = 0;
2025 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2026 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2027 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
2028
2029 tmp = 0;
2030 tmp |= S_008E2C_NUM_PS_LDS(0x1000);
2031 tmp |= S_008E2C_NUM_LS_LDS(0x1000);
2032 r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
2033
2034 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
2035 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
2036
2037 #if 0
2038 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
2039
2040 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
2041 #endif
2042 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
2043 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
2044
2045 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
2046 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
2047 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
2048 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
2049 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
2050 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
2051
2052 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
2053 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
2054 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
2055 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
2056
2057 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
2058 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
2059 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
2060 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
2061 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
2062 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
2063 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
2064 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
2065 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
2066 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
2067 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
2068 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
2069 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
2070 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
2071 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
2072 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
2073 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
2074 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
2075
2076 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
2077 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
2078 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
2079 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
2080 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
2081 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
2082 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
2083 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
2084 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
2085 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
2086 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
2087 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
2088 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
2089 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
2090 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
2091 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
2092 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
2093 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
2094 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
2095 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
2096 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
2097 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
2098 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
2099 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
2100 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
2101 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
2102 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
2103 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
2104 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
2105 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
2106 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
2107 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
2108
2109 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL);
2110
2111 r600_context_pipe_state_set(&rctx->ctx, rstate);
2112 }
2113
2114 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
2115 {
2116 struct r600_pipe_state state;
2117
2118 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2119 state.nregs = 0;
2120 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2121 float offset_units = rctx->rasterizer->offset_units;
2122 unsigned offset_db_fmt_cntl = 0, depth;
2123
2124 switch (rctx->framebuffer.zsbuf->texture->format) {
2125 case PIPE_FORMAT_Z24X8_UNORM:
2126 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
2127 depth = -24;
2128 offset_units *= 2.0f;
2129 break;
2130 case PIPE_FORMAT_Z32_FLOAT:
2131 depth = -23;
2132 offset_units *= 1.0f;
2133 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2134 break;
2135 case PIPE_FORMAT_Z16_UNORM:
2136 depth = -16;
2137 offset_units *= 4.0f;
2138 break;
2139 default:
2140 return;
2141 }
2142 /* FIXME some of those reg can be computed with cso */
2143 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2144 r600_pipe_state_add_reg(&state,
2145 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2146 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
2147 r600_pipe_state_add_reg(&state,
2148 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2149 fui(offset_units), 0xFFFFFFFF, NULL);
2150 r600_pipe_state_add_reg(&state,
2151 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2152 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
2153 r600_pipe_state_add_reg(&state,
2154 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2155 fui(offset_units), 0xFFFFFFFF, NULL);
2156 r600_pipe_state_add_reg(&state,
2157 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2158 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
2159 r600_context_pipe_state_set(&rctx->ctx, &state);
2160 }
2161 }
2162
2163 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2164 {
2165 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2166 struct r600_pipe_state *rstate = &shader->rstate;
2167 struct r600_shader *rshader = &shader->shader;
2168 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2169 int pos_index = -1, face_index = -1;
2170 int ninterp = 0;
2171 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2172 unsigned spi_baryc_cntl;
2173
2174 rstate->nregs = 0;
2175
2176 db_shader_control = 0;
2177 for (i = 0; i < rshader->ninput; i++) {
2178 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
2179 POSITION goes via GPRs from the SC so isn't counted */
2180 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2181 pos_index = i;
2182 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2183 face_index = i;
2184 else {
2185 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
2186 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2187 ninterp++;
2188 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2189 have_linear = TRUE;
2190 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2191 have_perspective = TRUE;
2192 if (rshader->input[i].centroid)
2193 have_centroid = TRUE;
2194 }
2195 }
2196 for (i = 0; i < rshader->noutput; i++) {
2197 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2198 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2199 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2200 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1);
2201 }
2202 if (rshader->uses_kill)
2203 db_shader_control |= S_02880C_KILL_ENABLE(1);
2204
2205 exports_ps = 0;
2206 num_cout = 0;
2207 for (i = 0; i < rshader->noutput; i++) {
2208 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2209 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2210 exports_ps |= 1;
2211 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2212 if (rshader->fs_write_all)
2213 num_cout = rshader->nr_cbufs;
2214 else
2215 num_cout++;
2216 }
2217 }
2218 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2219 if (!exports_ps) {
2220 /* always at least export 1 component per pixel */
2221 exports_ps = 2;
2222 }
2223
2224 if (ninterp == 0) {
2225 ninterp = 1;
2226 have_perspective = TRUE;
2227 }
2228
2229 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2230 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2231 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2232 spi_input_z = 0;
2233 if (pos_index != -1) {
2234 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
2235 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2236 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2237 spi_input_z |= 1;
2238 }
2239
2240 spi_ps_in_control_1 = 0;
2241 if (face_index != -1) {
2242 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2243 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2244 }
2245
2246 spi_baryc_cntl = 0;
2247 if (have_perspective)
2248 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2249 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2250 if (have_linear)
2251 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2252 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2253
2254 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2255 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
2256 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2257 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
2258 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2259 0, 0xFFFFFFFF, NULL);
2260 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
2261 r600_pipe_state_add_reg(rstate,
2262 R_0286E0_SPI_BARYC_CNTL,
2263 spi_baryc_cntl,
2264 0xFFFFFFFF, NULL);
2265
2266 r600_pipe_state_add_reg(rstate,
2267 R_028840_SQ_PGM_START_PS,
2268 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
2269 r600_pipe_state_add_reg(rstate,
2270 R_028844_SQ_PGM_RESOURCES_PS,
2271 S_028844_NUM_GPRS(rshader->bc.ngpr) |
2272 S_028844_PRIME_CACHE_ON_DRAW(1) |
2273 S_028844_STACK_SIZE(rshader->bc.nstack),
2274 0xFFFFFFFF, NULL);
2275 r600_pipe_state_add_reg(rstate,
2276 R_028848_SQ_PGM_RESOURCES_2_PS,
2277 0x0, 0xFFFFFFFF, NULL);
2278 r600_pipe_state_add_reg(rstate,
2279 R_02884C_SQ_PGM_EXPORTS_PS,
2280 exports_ps, 0xFFFFFFFF, NULL);
2281 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */
2282 /* only set some bits here, the other bits are set in the dsa state */
2283 r600_pipe_state_add_reg(rstate,
2284 R_02880C_DB_SHADER_CONTROL,
2285 db_shader_control,
2286 S_02880C_Z_EXPORT_ENABLE(1) |
2287 S_02880C_STENCIL_EXPORT_ENABLE(1) |
2288 S_02880C_KILL_ENABLE(1),
2289 NULL);
2290 r600_pipe_state_add_reg(rstate,
2291 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
2292 0xFFFFFFFF, NULL);
2293 }
2294
2295 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2296 {
2297 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2298 struct r600_pipe_state *rstate = &shader->rstate;
2299 struct r600_shader *rshader = &shader->shader;
2300 unsigned spi_vs_out_id[10];
2301 unsigned i, tmp;
2302
2303 /* clear previous register */
2304 rstate->nregs = 0;
2305
2306 /* so far never got proper semantic id from tgsi */
2307 for (i = 0; i < 10; i++) {
2308 spi_vs_out_id[i] = 0;
2309 }
2310 for (i = 0; i < 32; i++) {
2311 tmp = i << ((i & 3) * 8);
2312 spi_vs_out_id[i / 4] |= tmp;
2313 }
2314 for (i = 0; i < 10; i++) {
2315 r600_pipe_state_add_reg(rstate,
2316 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2317 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
2318 }
2319
2320 r600_pipe_state_add_reg(rstate,
2321 R_0286C4_SPI_VS_OUT_CONFIG,
2322 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
2323 0xFFFFFFFF, NULL);
2324 r600_pipe_state_add_reg(rstate,
2325 R_028860_SQ_PGM_RESOURCES_VS,
2326 S_028860_NUM_GPRS(rshader->bc.ngpr) |
2327 S_028860_STACK_SIZE(rshader->bc.nstack),
2328 0xFFFFFFFF, NULL);
2329 r600_pipe_state_add_reg(rstate,
2330 R_028864_SQ_PGM_RESOURCES_2_VS,
2331 0x0, 0xFFFFFFFF, NULL);
2332 r600_pipe_state_add_reg(rstate,
2333 R_02885C_SQ_PGM_START_VS,
2334 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
2335
2336 r600_pipe_state_add_reg(rstate,
2337 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2338 0xFFFFFFFF, NULL);
2339 }
2340
2341 void evergreen_fetch_shader(struct pipe_context *ctx,
2342 struct r600_vertex_element *ve)
2343 {
2344 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2345 struct r600_pipe_state *rstate = &ve->rstate;
2346 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2347 rstate->nregs = 0;
2348 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
2349 0x00000000, 0xFFFFFFFF, NULL);
2350 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
2351 (r600_bo_offset(ve->fetch_shader)) >> 8,
2352 0xFFFFFFFF, ve->fetch_shader);
2353 }
2354
2355 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
2356 {
2357 struct pipe_depth_stencil_alpha_state dsa;
2358 struct r600_pipe_state *rstate;
2359
2360 memset(&dsa, 0, sizeof(dsa));
2361
2362 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2363 r600_pipe_state_add_reg(rstate,
2364 R_02880C_DB_SHADER_CONTROL,
2365 0x0,
2366 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
2367 r600_pipe_state_add_reg(rstate,
2368 R_028000_DB_RENDER_CONTROL,
2369 S_028000_DEPTH_COPY_ENABLE(1) |
2370 S_028000_STENCIL_COPY_ENABLE(1) |
2371 S_028000_COPY_CENTROID(1),
2372 S_028000_DEPTH_COPY_ENABLE(1) |
2373 S_028000_STENCIL_COPY_ENABLE(1) |
2374 S_028000_COPY_CENTROID(1), NULL);
2375 return rstate;
2376 }
2377
2378 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2379 struct r600_pipe_resource_state *rstate)
2380 {
2381 rstate->id = R600_PIPE_STATE_RESOURCE;
2382
2383 rstate->val[0] = 0;
2384 rstate->bo[0] = NULL;
2385 rstate->val[1] = 0;
2386 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32));
2387 rstate->val[3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2388 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2389 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2390 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
2391 rstate->val[4] = 0;
2392 rstate->val[5] = 0;
2393 rstate->val[6] = 0;
2394 rstate->val[7] = 0xc0000000;
2395 }
2396
2397
2398 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2399 struct r600_resource *rbuffer,
2400 unsigned offset, unsigned stride)
2401 {
2402 rstate->bo[0] = rbuffer->bo;
2403 rstate->val[0] = offset;
2404 rstate->val[1] = rbuffer->bo_size - offset - 1;
2405 rstate->val[2] = S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2406 S_030008_STRIDE(stride);
2407 }