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[g3dvl] move stuff from flush into own functions
[mesa.git] / src / gallium / drivers / r600 / evergreen_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_blitter.h>
36 #include <util/u_double_list.h>
37 #include <util/u_transfer.h>
38 #include <util/u_surface.h>
39 #include <util/u_pack_color.h>
40 #include <util/u_memory.h>
41 #include <util/u_inlines.h>
42 #include <util/u_framebuffer.h>
43 #include <pipebuffer/pb_buffer.h>
44 #include "r600.h"
45 #include "evergreend.h"
46 #include "r600_resource.h"
47 #include "r600_shader.h"
48 #include "r600_pipe.h"
49 #include "eg_state_inlines.h"
50
51 static void evergreen_set_blend_color(struct pipe_context *ctx,
52 const struct pipe_blend_color *state)
53 {
54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
56
57 if (rstate == NULL)
58 return;
59
60 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
65
66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
68 r600_context_pipe_state_set(&rctx->ctx, rstate);
69 }
70
71 static void *evergreen_create_blend_state(struct pipe_context *ctx,
72 const struct pipe_blend_state *state)
73 {
74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
75 struct r600_pipe_state *rstate;
76 u32 color_control, target_mask;
77 /* FIXME there is more then 8 framebuffer */
78 unsigned blend_cntl[8];
79
80 if (blend == NULL) {
81 return NULL;
82 }
83 rstate = &blend->rstate;
84
85 rstate->id = R600_PIPE_STATE_BLEND;
86
87 target_mask = 0;
88 color_control = S_028808_MODE(1);
89 if (state->logicop_enable) {
90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
91 } else {
92 color_control |= (0xcc << 16);
93 }
94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
95 if (state->independent_blend_enable) {
96 for (int i = 0; i < 8; i++) {
97 target_mask |= (state->rt[i].colormask << (4 * i));
98 }
99 } else {
100 for (int i = 0; i < 8; i++) {
101 target_mask |= (state->rt[0].colormask << (4 * i));
102 }
103 }
104 blend->cb_target_mask = target_mask;
105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
106 color_control, 0xFFFFFFFF, NULL);
107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
108
109 for (int i = 0; i < 8; i++) {
110 unsigned eqRGB = state->rt[i].rgb_func;
111 unsigned srcRGB = state->rt[i].rgb_src_factor;
112 unsigned dstRGB = state->rt[i].rgb_dst_factor;
113 unsigned eqA = state->rt[i].alpha_func;
114 unsigned srcA = state->rt[i].alpha_src_factor;
115 unsigned dstA = state->rt[i].alpha_dst_factor;
116
117 blend_cntl[i] = 0;
118 if (!state->rt[i].blend_enable)
119 continue;
120
121 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
122 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
123 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
124 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
125
126 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
127 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
128 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
129 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
130 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
131 }
132 }
133 for (int i = 0; i < 8; i++) {
134 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
135 }
136
137 return rstate;
138 }
139
140 static void *evergreen_create_dsa_state(struct pipe_context *ctx,
141 const struct pipe_depth_stencil_alpha_state *state)
142 {
143 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
144 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
145 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
146
147 if (rstate == NULL) {
148 return NULL;
149 }
150
151 rstate->id = R600_PIPE_STATE_DSA;
152 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
153 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
154 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
155 * be set if shader use texkill instruction
156 */
157 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
158 stencil_ref_mask = 0;
159 stencil_ref_mask_bf = 0;
160 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
161 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
162 S_028800_ZFUNC(state->depth.func);
163
164 /* stencil */
165 if (state->stencil[0].enabled) {
166 db_depth_control |= S_028800_STENCIL_ENABLE(1);
167 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
168 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
169 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
170 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
171
172
173 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
174 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
175 if (state->stencil[1].enabled) {
176 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
177 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
178 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
179 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
180 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
181 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
182 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
183 }
184 }
185
186 /* alpha */
187 alpha_test_control = 0;
188 alpha_ref = 0;
189 if (state->alpha.enabled) {
190 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
191 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
192 alpha_ref = fui(state->alpha.ref_value);
193 }
194
195 /* misc */
196 db_render_control = 0;
197 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
198 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
199 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
200 /* TODO db_render_override depends on query */
201 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
202 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
203 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
204 r600_pipe_state_add_reg(rstate,
205 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
206 0xFFFFFFFF & C_028430_STENCILREF, NULL);
207 r600_pipe_state_add_reg(rstate,
208 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
209 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
210 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
211 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
212 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
213 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
214 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
215 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
216 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
217 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
218 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
219 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
220
221 return rstate;
222 }
223
224 static void *evergreen_create_rs_state(struct pipe_context *ctx,
225 const struct pipe_rasterizer_state *state)
226 {
227 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
228 struct r600_pipe_state *rstate;
229 unsigned tmp;
230 unsigned prov_vtx = 1, polygon_dual_mode;
231 unsigned clip_rule;
232
233 if (rs == NULL) {
234 return NULL;
235 }
236
237 rstate = &rs->rstate;
238 rs->flatshade = state->flatshade;
239 rs->sprite_coord_enable = state->sprite_coord_enable;
240
241 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
242
243 /* offset */
244 rs->offset_units = state->offset_units;
245 rs->offset_scale = state->offset_scale * 12.0f;
246
247 rstate->id = R600_PIPE_STATE_RASTERIZER;
248 if (state->flatshade_first)
249 prov_vtx = 0;
250 tmp = S_0286D4_FLAT_SHADE_ENA(1);
251 if (state->sprite_coord_enable) {
252 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
253 S_0286D4_PNT_SPRITE_OVRD_X(2) |
254 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
255 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
256 S_0286D4_PNT_SPRITE_OVRD_W(1);
257 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
258 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
259 }
260 }
261 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
262
263 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
264 state->fill_back != PIPE_POLYGON_MODE_FILL);
265 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
266 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
267 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
268 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
269 S_028814_FACE(!state->front_ccw) |
270 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
271 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
272 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
273 S_028814_POLY_MODE(polygon_dual_mode) |
274 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
275 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
276 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
277 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
278 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
279 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
280 /* point size 12.4 fixed point */
281 tmp = (unsigned)(state->point_size * 8.0);
282 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
283 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
284 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
285 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
286 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
287 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
288 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
289 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
290 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
291 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL);
292 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
293 return rstate;
294 }
295
296 static void *evergreen_create_sampler_state(struct pipe_context *ctx,
297 const struct pipe_sampler_state *state)
298 {
299 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
300 union util_color uc;
301
302 if (rstate == NULL) {
303 return NULL;
304 }
305
306 rstate->id = R600_PIPE_STATE_SAMPLER;
307 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
308 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
309 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
310 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
311 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
312 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
313 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
314 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
315 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
316 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
317 /* FIXME LOD it depends on texture base level ... */
318 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
319 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
320 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
321 0xFFFFFFFF, NULL);
322 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
323 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
324 S_03C008_TYPE(1),
325 0xFFFFFFFF, NULL);
326
327 if (uc.ui) {
328 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
329 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
330 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
331 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
332 }
333 return rstate;
334 }
335
336 static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
337 struct pipe_resource *texture,
338 const struct pipe_sampler_view *state)
339 {
340 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
341 struct r600_pipe_state *rstate;
342 const struct util_format_description *desc;
343 struct r600_resource_texture *tmp;
344 struct r600_resource *rbuffer;
345 unsigned format;
346 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
347 unsigned char swizzle[4];
348 struct r600_bo *bo[2];
349
350 if (resource == NULL)
351 return NULL;
352 rstate = &resource->state;
353
354 /* initialize base object */
355 resource->base = *state;
356 resource->base.texture = NULL;
357 pipe_reference(NULL, &texture->reference);
358 resource->base.texture = texture;
359 resource->base.reference.count = 1;
360 resource->base.context = ctx;
361
362 swizzle[0] = state->swizzle_r;
363 swizzle[1] = state->swizzle_g;
364 swizzle[2] = state->swizzle_b;
365 swizzle[3] = state->swizzle_a;
366 format = r600_translate_texformat(state->format,
367 swizzle,
368 &word4, &yuv_format);
369 if (format == ~0) {
370 format = 0;
371 }
372 desc = util_format_description(state->format);
373 if (desc == NULL) {
374 R600_ERR("unknow format %d\n", state->format);
375 }
376 tmp = (struct r600_resource_texture*)texture;
377 rbuffer = &tmp->resource;
378 bo[0] = rbuffer->bo;
379 bo[1] = rbuffer->bo;
380 /* FIXME depth texture decompression */
381 if (tmp->depth) {
382 r600_texture_depth_flush(ctx, texture);
383 tmp = (struct r600_resource_texture*)texture;
384 rbuffer = &tmp->flushed_depth_texture->resource;
385 bo[0] = rbuffer->bo;
386 bo[1] = rbuffer->bo;
387 }
388 pitch = align(tmp->pitch_in_pixels[0], 8);
389
390 /* FIXME properly handle first level != 0 */
391 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
392 S_030000_DIM(r600_tex_dim(texture->target)) |
393 S_030000_PITCH((pitch / 8) - 1) |
394 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
395 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
396 S_030004_TEX_HEIGHT(texture->height0 - 1) |
397 S_030004_TEX_DEPTH(texture->depth0 - 1),
398 0xFFFFFFFF, NULL);
399 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
400 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
401 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
402 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
403 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
404 word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
405 S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
406 S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
407 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
408 S_030014_LAST_LEVEL(state->last_level) |
409 S_030014_BASE_ARRAY(0) |
410 S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
411 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
412 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
413 S_03001C_DATA_FORMAT(format) |
414 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
415
416 return &resource->base;
417 }
418
419 static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
420 struct pipe_sampler_view **views)
421 {
422 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
423 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
424
425 for (int i = 0; i < count; i++) {
426 if (resource[i]) {
427 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
428 }
429 }
430 }
431
432 static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
433 struct pipe_sampler_view **views)
434 {
435 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
436 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
437 int i;
438
439 for (i = 0; i < count; i++) {
440 if (&rctx->ps_samplers.views[i]->base != views[i]) {
441 if (resource[i])
442 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
443 else
444 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
445
446 pipe_sampler_view_reference(
447 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
448 views[i]);
449 }
450 }
451 for (i = count; i < NUM_TEX_UNITS; i++) {
452 if (rctx->ps_samplers.views[i]) {
453 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
454 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
455 }
456 }
457 rctx->ps_samplers.n_views = count;
458 }
459
460 static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
461 {
462 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
463 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
464
465
466 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
467 rctx->ps_samplers.n_samplers = count;
468
469 for (int i = 0; i < count; i++) {
470 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
471 }
472 }
473
474 static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
475 {
476 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
477 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
478
479 for (int i = 0; i < count; i++) {
480 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
481 }
482 }
483
484 static void evergreen_set_clip_state(struct pipe_context *ctx,
485 const struct pipe_clip_state *state)
486 {
487 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
488 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
489
490 if (rstate == NULL)
491 return;
492
493 rctx->clip = *state;
494 rstate->id = R600_PIPE_STATE_CLIP;
495 for (int i = 0; i < state->nr; i++) {
496 r600_pipe_state_add_reg(rstate,
497 R_0285BC_PA_CL_UCP0_X + i * 4,
498 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
499 r600_pipe_state_add_reg(rstate,
500 R_0285C0_PA_CL_UCP0_Y + i * 4,
501 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
502 r600_pipe_state_add_reg(rstate,
503 R_0285C4_PA_CL_UCP0_Z + i * 4,
504 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
505 r600_pipe_state_add_reg(rstate,
506 R_0285C8_PA_CL_UCP0_W + i * 4,
507 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
508 }
509 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
510 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
511 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
512 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
513
514 free(rctx->states[R600_PIPE_STATE_CLIP]);
515 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
516 r600_context_pipe_state_set(&rctx->ctx, rstate);
517 }
518
519 static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
520 const struct pipe_poly_stipple *state)
521 {
522 }
523
524 static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
525 {
526 }
527
528 static void evergreen_set_scissor_state(struct pipe_context *ctx,
529 const struct pipe_scissor_state *state)
530 {
531 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
532 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
533 u32 tl, br;
534
535 if (rstate == NULL)
536 return;
537
538 rstate->id = R600_PIPE_STATE_SCISSOR;
539 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
540 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
541 r600_pipe_state_add_reg(rstate,
542 R_028210_PA_SC_CLIPRECT_0_TL, tl,
543 0xFFFFFFFF, NULL);
544 r600_pipe_state_add_reg(rstate,
545 R_028214_PA_SC_CLIPRECT_0_BR, br,
546 0xFFFFFFFF, NULL);
547 r600_pipe_state_add_reg(rstate,
548 R_028218_PA_SC_CLIPRECT_1_TL, tl,
549 0xFFFFFFFF, NULL);
550 r600_pipe_state_add_reg(rstate,
551 R_02821C_PA_SC_CLIPRECT_1_BR, br,
552 0xFFFFFFFF, NULL);
553 r600_pipe_state_add_reg(rstate,
554 R_028220_PA_SC_CLIPRECT_2_TL, tl,
555 0xFFFFFFFF, NULL);
556 r600_pipe_state_add_reg(rstate,
557 R_028224_PA_SC_CLIPRECT_2_BR, br,
558 0xFFFFFFFF, NULL);
559 r600_pipe_state_add_reg(rstate,
560 R_028228_PA_SC_CLIPRECT_3_TL, tl,
561 0xFFFFFFFF, NULL);
562 r600_pipe_state_add_reg(rstate,
563 R_02822C_PA_SC_CLIPRECT_3_BR, br,
564 0xFFFFFFFF, NULL);
565
566 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
567 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
568 r600_context_pipe_state_set(&rctx->ctx, rstate);
569 }
570
571 static void evergreen_set_stencil_ref(struct pipe_context *ctx,
572 const struct pipe_stencil_ref *state)
573 {
574 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
575 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
576 u32 tmp;
577
578 if (rstate == NULL)
579 return;
580
581 rctx->stencil_ref = *state;
582 rstate->id = R600_PIPE_STATE_STENCIL_REF;
583 tmp = S_028430_STENCILREF(state->ref_value[0]);
584 r600_pipe_state_add_reg(rstate,
585 R_028430_DB_STENCILREFMASK, tmp,
586 ~C_028430_STENCILREF, NULL);
587 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
588 r600_pipe_state_add_reg(rstate,
589 R_028434_DB_STENCILREFMASK_BF, tmp,
590 ~C_028434_STENCILREF_BF, NULL);
591
592 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
593 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
594 r600_context_pipe_state_set(&rctx->ctx, rstate);
595 }
596
597 static void evergreen_set_viewport_state(struct pipe_context *ctx,
598 const struct pipe_viewport_state *state)
599 {
600 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
601 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
602
603 if (rstate == NULL)
604 return;
605
606 rctx->viewport = *state;
607 rstate->id = R600_PIPE_STATE_VIEWPORT;
608 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
609 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
610 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
611 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
612 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
613 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
614 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
615 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
616 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
617
618 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
619 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
620 r600_context_pipe_state_set(&rctx->ctx, rstate);
621 }
622
623 static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
624 const struct pipe_framebuffer_state *state, int cb)
625 {
626 struct r600_resource_texture *rtex;
627 struct r600_resource *rbuffer;
628 struct r600_surface *surf;
629 unsigned level = state->cbufs[cb]->level;
630 unsigned pitch, slice;
631 unsigned color_info;
632 unsigned format, swap, ntype;
633 const struct util_format_description *desc;
634 struct r600_bo *bo[3];
635
636 surf = (struct r600_surface *)state->cbufs[cb];
637 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
638 rbuffer = &rtex->resource;
639 bo[0] = rbuffer->bo;
640 bo[1] = rbuffer->bo;
641 bo[2] = rbuffer->bo;
642
643 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
644 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
645 ntype = 0;
646 desc = util_format_description(rtex->resource.base.b.format);
647 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
648 ntype = V_028C70_NUMBER_SRGB;
649
650 format = r600_translate_colorformat(rtex->resource.base.b.format);
651 swap = r600_translate_colorswap(rtex->resource.base.b.format);
652 color_info = S_028C70_FORMAT(format) |
653 S_028C70_COMP_SWAP(swap) |
654 S_028C70_BLEND_CLAMP(1) |
655 S_028C70_NUMBER_TYPE(ntype);
656 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
657 color_info |= S_028C70_SOURCE_FORMAT(1);
658
659 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
660 r600_pipe_state_add_reg(rstate,
661 R_028C60_CB_COLOR0_BASE + cb * 0x3C,
662 (state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
663 r600_pipe_state_add_reg(rstate,
664 R_028C78_CB_COLOR0_DIM + cb * 0x3C,
665 0x0, 0xFFFFFFFF, NULL);
666 r600_pipe_state_add_reg(rstate,
667 R_028C70_CB_COLOR0_INFO + cb * 0x3C,
668 color_info, 0xFFFFFFFF, bo[0]);
669 r600_pipe_state_add_reg(rstate,
670 R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
671 S_028C64_PITCH_TILE_MAX(pitch),
672 0xFFFFFFFF, NULL);
673 r600_pipe_state_add_reg(rstate,
674 R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
675 S_028C68_SLICE_TILE_MAX(slice),
676 0xFFFFFFFF, NULL);
677 r600_pipe_state_add_reg(rstate,
678 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
679 0x00000000, 0xFFFFFFFF, NULL);
680 r600_pipe_state_add_reg(rstate,
681 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
682 S_028C74_NON_DISP_TILING_ORDER(1),
683 0xFFFFFFFF, bo[0]);
684 }
685
686 static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
687 const struct pipe_framebuffer_state *state)
688 {
689 struct r600_resource_texture *rtex;
690 struct r600_resource *rbuffer;
691 struct r600_surface *surf;
692 unsigned level;
693 unsigned pitch, slice, format, stencil_format;
694
695 if (state->zsbuf == NULL)
696 return;
697
698 level = state->zsbuf->level;
699
700 surf = (struct r600_surface *)state->zsbuf;
701 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
702 rtex->tiled = 1;
703 rtex->array_mode[level] = 2;
704 rtex->tile_type = 1;
705 rtex->depth = 1;
706 rbuffer = &rtex->resource;
707
708 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
709 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
710 format = r600_translate_dbformat(state->zsbuf->texture->format);
711 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
712
713 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
714 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
715 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
716 (state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
717
718 if (stencil_format) {
719 uint32_t stencil_offset;
720
721 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255;
722 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
723 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
724 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
725 (state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
726 }
727
728 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
729 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
730 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
731
732 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
733 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format),
734 0xFFFFFFFF, rbuffer->bo);
735 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
736 S_028058_PITCH_TILE_MAX(pitch),
737 0xFFFFFFFF, NULL);
738 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
739 S_02805C_SLICE_TILE_MAX(slice),
740 0xFFFFFFFF, NULL);
741 }
742
743 static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
744 const struct pipe_framebuffer_state *state)
745 {
746 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
747 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
748 u32 shader_mask, tl, br, target_mask;
749
750 if (rstate == NULL)
751 return;
752
753 /* unreference old buffer and reference new one */
754 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
755
756 util_copy_framebuffer_state(&rctx->framebuffer, state);
757
758 rctx->pframebuffer = &rctx->framebuffer;
759
760 /* build states */
761 for (int i = 0; i < state->nr_cbufs; i++) {
762 evergreen_cb(rctx, rstate, state, i);
763 }
764 if (state->zsbuf) {
765 evergreen_db(rctx, rstate, state);
766 }
767
768 target_mask = 0x00000000;
769 target_mask = 0xFFFFFFFF;
770 shader_mask = 0;
771 for (int i = 0; i < state->nr_cbufs; i++) {
772 target_mask ^= 0xf << (i * 4);
773 shader_mask |= 0xf << (i * 4);
774 }
775 tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
776 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
777
778 r600_pipe_state_add_reg(rstate,
779 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
780 0xFFFFFFFF, NULL);
781 r600_pipe_state_add_reg(rstate,
782 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
783 0xFFFFFFFF, NULL);
784 r600_pipe_state_add_reg(rstate,
785 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
786 0xFFFFFFFF, NULL);
787 r600_pipe_state_add_reg(rstate,
788 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
789 0xFFFFFFFF, NULL);
790 r600_pipe_state_add_reg(rstate,
791 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
792 0xFFFFFFFF, NULL);
793 r600_pipe_state_add_reg(rstate,
794 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
795 0xFFFFFFFF, NULL);
796 r600_pipe_state_add_reg(rstate,
797 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
798 0xFFFFFFFF, NULL);
799 r600_pipe_state_add_reg(rstate,
800 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
801 0xFFFFFFFF, NULL);
802 r600_pipe_state_add_reg(rstate,
803 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
804 0xFFFFFFFF, NULL);
805 r600_pipe_state_add_reg(rstate,
806 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
807 0xFFFFFFFF, NULL);
808
809 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
810 0x00000000, target_mask, NULL);
811 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
812 shader_mask, 0xFFFFFFFF, NULL);
813 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
814 0x00000000, 0xFFFFFFFF, NULL);
815 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
816 0x00000000, 0xFFFFFFFF, NULL);
817
818 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
819 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
820 r600_context_pipe_state_set(&rctx->ctx, rstate);
821 }
822
823 static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
824 struct pipe_resource *buffer)
825 {
826 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
827 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
828
829 switch (shader) {
830 case PIPE_SHADER_VERTEX:
831 rctx->vs_const_buffer.nregs = 0;
832 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
833 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
834 ALIGN_DIVUP(buffer->width0 >> 4, 16),
835 0xFFFFFFFF, NULL);
836 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
837 R_028980_ALU_CONST_CACHE_VS_0,
838 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
839 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
840 break;
841 case PIPE_SHADER_FRAGMENT:
842 rctx->ps_const_buffer.nregs = 0;
843 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
844 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
845 ALIGN_DIVUP(buffer->width0 >> 4, 16),
846 0xFFFFFFFF, NULL);
847 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
848 R_028940_ALU_CONST_CACHE_PS_0,
849 (r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
850 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
851 break;
852 default:
853 R600_ERR("unsupported %d\n", shader);
854 return;
855 }
856 }
857
858 void evergreen_init_state_functions(struct r600_pipe_context *rctx)
859 {
860 rctx->context.create_blend_state = evergreen_create_blend_state;
861 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
862 rctx->context.create_fs_state = r600_create_shader_state;
863 rctx->context.create_rasterizer_state = evergreen_create_rs_state;
864 rctx->context.create_sampler_state = evergreen_create_sampler_state;
865 rctx->context.create_sampler_view = evergreen_create_sampler_view;
866 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
867 rctx->context.create_vs_state = r600_create_shader_state;
868 rctx->context.bind_blend_state = r600_bind_blend_state;
869 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
870 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
871 rctx->context.bind_fs_state = r600_bind_ps_shader;
872 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
873 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
874 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
875 rctx->context.bind_vs_state = r600_bind_vs_shader;
876 rctx->context.delete_blend_state = r600_delete_state;
877 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
878 rctx->context.delete_fs_state = r600_delete_ps_shader;
879 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
880 rctx->context.delete_sampler_state = r600_delete_state;
881 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
882 rctx->context.delete_vs_state = r600_delete_vs_shader;
883 rctx->context.set_blend_color = evergreen_set_blend_color;
884 rctx->context.set_clip_state = evergreen_set_clip_state;
885 rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
886 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
887 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
888 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
889 rctx->context.set_sample_mask = evergreen_set_sample_mask;
890 rctx->context.set_scissor_state = evergreen_set_scissor_state;
891 rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
892 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
893 rctx->context.set_index_buffer = r600_set_index_buffer;
894 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
895 rctx->context.set_viewport_state = evergreen_set_viewport_state;
896 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
897 }
898
899 void evergreen_init_config(struct r600_pipe_context *rctx)
900 {
901 struct r600_pipe_state *rstate = &rctx->config;
902 int ps_prio;
903 int vs_prio;
904 int gs_prio;
905 int es_prio;
906 int hs_prio, cs_prio, ls_prio;
907 int num_ps_gprs;
908 int num_vs_gprs;
909 int num_gs_gprs;
910 int num_es_gprs;
911 int num_hs_gprs;
912 int num_ls_gprs;
913 int num_temp_gprs;
914 int num_ps_threads;
915 int num_vs_threads;
916 int num_gs_threads;
917 int num_es_threads;
918 int num_hs_threads;
919 int num_ls_threads;
920 int num_ps_stack_entries;
921 int num_vs_stack_entries;
922 int num_gs_stack_entries;
923 int num_es_stack_entries;
924 int num_hs_stack_entries;
925 int num_ls_stack_entries;
926 enum radeon_family family;
927 unsigned tmp;
928
929 family = r600_get_family(rctx->radeon);
930 ps_prio = 0;
931 vs_prio = 1;
932 gs_prio = 2;
933 es_prio = 3;
934 hs_prio = 0;
935 ls_prio = 0;
936 cs_prio = 0;
937
938 switch (family) {
939 case CHIP_CEDAR:
940 default:
941 num_ps_gprs = 93;
942 num_vs_gprs = 46;
943 num_temp_gprs = 4;
944 num_gs_gprs = 31;
945 num_es_gprs = 31;
946 num_hs_gprs = 23;
947 num_ls_gprs = 23;
948 num_ps_threads = 96;
949 num_vs_threads = 16;
950 num_gs_threads = 16;
951 num_es_threads = 16;
952 num_hs_threads = 16;
953 num_ls_threads = 16;
954 num_ps_stack_entries = 42;
955 num_vs_stack_entries = 42;
956 num_gs_stack_entries = 42;
957 num_es_stack_entries = 42;
958 num_hs_stack_entries = 42;
959 num_ls_stack_entries = 42;
960 break;
961 case CHIP_REDWOOD:
962 num_ps_gprs = 93;
963 num_vs_gprs = 46;
964 num_temp_gprs = 4;
965 num_gs_gprs = 31;
966 num_es_gprs = 31;
967 num_hs_gprs = 23;
968 num_ls_gprs = 23;
969 num_ps_threads = 128;
970 num_vs_threads = 20;
971 num_gs_threads = 20;
972 num_es_threads = 20;
973 num_hs_threads = 20;
974 num_ls_threads = 20;
975 num_ps_stack_entries = 42;
976 num_vs_stack_entries = 42;
977 num_gs_stack_entries = 42;
978 num_es_stack_entries = 42;
979 num_hs_stack_entries = 42;
980 num_ls_stack_entries = 42;
981 break;
982 case CHIP_JUNIPER:
983 num_ps_gprs = 93;
984 num_vs_gprs = 46;
985 num_temp_gprs = 4;
986 num_gs_gprs = 31;
987 num_es_gprs = 31;
988 num_hs_gprs = 23;
989 num_ls_gprs = 23;
990 num_ps_threads = 128;
991 num_vs_threads = 20;
992 num_gs_threads = 20;
993 num_es_threads = 20;
994 num_hs_threads = 20;
995 num_ls_threads = 20;
996 num_ps_stack_entries = 85;
997 num_vs_stack_entries = 85;
998 num_gs_stack_entries = 85;
999 num_es_stack_entries = 85;
1000 num_hs_stack_entries = 85;
1001 num_ls_stack_entries = 85;
1002 break;
1003 case CHIP_CYPRESS:
1004 case CHIP_HEMLOCK:
1005 num_ps_gprs = 93;
1006 num_vs_gprs = 46;
1007 num_temp_gprs = 4;
1008 num_gs_gprs = 31;
1009 num_es_gprs = 31;
1010 num_hs_gprs = 23;
1011 num_ls_gprs = 23;
1012 num_ps_threads = 128;
1013 num_vs_threads = 20;
1014 num_gs_threads = 20;
1015 num_es_threads = 20;
1016 num_hs_threads = 20;
1017 num_ls_threads = 20;
1018 num_ps_stack_entries = 85;
1019 num_vs_stack_entries = 85;
1020 num_gs_stack_entries = 85;
1021 num_es_stack_entries = 85;
1022 num_hs_stack_entries = 85;
1023 num_ls_stack_entries = 85;
1024 break;
1025 }
1026
1027 tmp = 0x00000000;
1028 switch (family) {
1029 case CHIP_CEDAR:
1030 break;
1031 default:
1032 tmp |= S_008C00_VC_ENABLE(1);
1033 break;
1034 }
1035 tmp |= S_008C00_EXPORT_SRC_C(1);
1036 tmp |= S_008C00_CS_PRIO(cs_prio);
1037 tmp |= S_008C00_LS_PRIO(ls_prio);
1038 tmp |= S_008C00_HS_PRIO(hs_prio);
1039 tmp |= S_008C00_PS_PRIO(ps_prio);
1040 tmp |= S_008C00_VS_PRIO(vs_prio);
1041 tmp |= S_008C00_GS_PRIO(gs_prio);
1042 tmp |= S_008C00_ES_PRIO(es_prio);
1043 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1044
1045 tmp = 0;
1046 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1047 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1048 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1049 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1050
1051 tmp = 0;
1052 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1053 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1054 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1055
1056 tmp = 0;
1057 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
1058 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
1059 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1060
1061 tmp = 0;
1062 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
1063 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
1064 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
1065 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
1066 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1067
1068 tmp = 0;
1069 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
1070 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
1071 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1072
1073 tmp = 0;
1074 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1075 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1076 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1077
1078 tmp = 0;
1079 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1080 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1081 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1082
1083 tmp = 0;
1084 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
1085 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
1086 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
1087
1088 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
1089 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
1090
1091 // r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
1092
1093 // r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
1094 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
1095 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
1096
1097 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1098 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1099 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1100 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1101 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1102 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1103
1104 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
1105 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
1106 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
1107 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
1108
1109 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
1110 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
1111 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1112 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
1113 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
1114 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
1115 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
1116 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
1117 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
1118 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
1119 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1120 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
1121 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
1122 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1123 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
1124 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
1125 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
1126 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
1127
1128 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
1129 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
1130 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
1131 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
1132 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
1133 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
1134 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
1135 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
1136 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
1137 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
1138 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
1139 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
1140 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
1141 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
1142 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
1143 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
1144 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
1145 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
1146 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
1147 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
1148 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
1149 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
1150 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
1151 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
1152 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
1153 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
1154 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
1155 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
1156 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
1157 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
1158 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
1159 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
1160
1161 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1162 0x0, 0xFFFFFFFF, NULL);
1163
1164 r600_context_pipe_state_set(&rctx->ctx, rstate);
1165 }
1166
1167 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
1168 void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
1169 {
1170 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1171 struct r600_pipe_state *rstate;
1172 struct r600_resource *rbuffer;
1173 unsigned i, j, offset, prim;
1174 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
1175 struct pipe_vertex_buffer *vertex_buffer;
1176 struct r600_draw rdraw;
1177 struct r600_pipe_state vgt;
1178 struct r600_drawl draw;
1179 boolean translate = FALSE;
1180
1181 if (rctx->vertex_elements->incompatible_layout) {
1182 r600_begin_vertex_translate(rctx);
1183 translate = TRUE;
1184 }
1185
1186 if (rctx->any_user_vbs) {
1187 r600_upload_user_buffers(rctx);
1188 rctx->any_user_vbs = FALSE;
1189 }
1190
1191 memset(&draw, 0, sizeof(struct r600_drawl));
1192 draw.ctx = ctx;
1193 draw.mode = info->mode;
1194 draw.start = info->start;
1195 draw.count = info->count;
1196 if (info->indexed && rctx->index_buffer.buffer) {
1197 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
1198 draw.min_index = info->min_index;
1199 draw.max_index = info->max_index;
1200 draw.index_bias = info->index_bias;
1201
1202 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
1203 &rctx->index_buffer.index_size,
1204 &draw.start,
1205 info->count);
1206
1207 draw.index_size = rctx->index_buffer.index_size;
1208 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
1209 draw.index_buffer_offset = draw.start * draw.index_size;
1210 draw.start = 0;
1211 r600_upload_index_buffer(rctx, &draw);
1212 } else {
1213 draw.index_size = 0;
1214 draw.index_buffer = NULL;
1215 draw.min_index = info->min_index;
1216 draw.max_index = info->max_index;
1217 draw.index_bias = info->start;
1218 }
1219
1220 switch (draw.index_size) {
1221 case 2:
1222 vgt_draw_initiator = 0;
1223 vgt_dma_index_type = 0;
1224 break;
1225 case 4:
1226 vgt_draw_initiator = 0;
1227 vgt_dma_index_type = 1;
1228 break;
1229 case 0:
1230 vgt_draw_initiator = 2;
1231 vgt_dma_index_type = 0;
1232 break;
1233 default:
1234 R600_ERR("unsupported index size %d\n", draw.index_size);
1235 return;
1236 }
1237 if (r600_conv_pipe_prim(draw.mode, &prim))
1238 return;
1239
1240 /* rebuild vertex shader if input format changed */
1241 if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
1242 return;
1243 if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
1244 return;
1245
1246 for (i = 0 ; i < rctx->vertex_elements->count; i++) {
1247 uint32_t word3, word2;
1248 uint32_t format;
1249 rstate = &rctx->vs_resource[i];
1250
1251 rstate->id = R600_PIPE_STATE_RESOURCE;
1252 rstate->nregs = 0;
1253
1254 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
1255 vertex_buffer = &rctx->vertex_buffer[j];
1256 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
1257 offset = rctx->vertex_elements->elements[i].src_offset +
1258 vertex_buffer->buffer_offset +
1259 r600_bo_offset(rbuffer->bo);
1260
1261 format = r600_translate_vertex_data_type(rctx->vertex_elements->hw_format[i]);
1262
1263 word2 = format | S_030008_STRIDE(vertex_buffer->stride);
1264
1265 word3 = r600_translate_vertex_data_swizzle(rctx->vertex_elements->hw_format[i]);
1266
1267 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
1268 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
1269 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
1270 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, word3, 0xFFFFFFFF, NULL);
1271 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
1272 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
1273 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
1274 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
1275 evergreen_vs_resource_set(&rctx->ctx, rstate, i);
1276 }
1277
1278 mask = 0;
1279 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
1280 mask |= (0xF << (i * 4));
1281 }
1282
1283 vgt.id = R600_PIPE_STATE_VGT;
1284 vgt.nregs = 0;
1285 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
1286 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.index_bias, 0xFFFFFFFF, NULL);
1287 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
1288 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
1289 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
1290 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
1291 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
1292
1293 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
1294 float offset_units = rctx->rasterizer->offset_units;
1295 unsigned offset_db_fmt_cntl = 0, depth;
1296
1297 switch (rctx->framebuffer.zsbuf->texture->format) {
1298 case PIPE_FORMAT_Z24X8_UNORM:
1299 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
1300 depth = -24;
1301 offset_units *= 2.0f;
1302 break;
1303 case PIPE_FORMAT_Z32_FLOAT:
1304 depth = -23;
1305 offset_units *= 1.0f;
1306 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1307 break;
1308 case PIPE_FORMAT_Z16_UNORM:
1309 depth = -16;
1310 offset_units *= 4.0f;
1311 break;
1312 default:
1313 return;
1314 }
1315 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
1316 r600_pipe_state_add_reg(&vgt,
1317 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1318 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1319 r600_pipe_state_add_reg(&vgt,
1320 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1321 fui(offset_units), 0xFFFFFFFF, NULL);
1322 r600_pipe_state_add_reg(&vgt,
1323 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1324 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
1325 r600_pipe_state_add_reg(&vgt,
1326 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1327 fui(offset_units), 0xFFFFFFFF, NULL);
1328 r600_pipe_state_add_reg(&vgt,
1329 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1330 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
1331 }
1332 r600_context_pipe_state_set(&rctx->ctx, &vgt);
1333
1334 rdraw.vgt_num_indices = draw.count;
1335 rdraw.vgt_num_instances = 1;
1336 rdraw.vgt_index_type = vgt_dma_index_type;
1337 rdraw.vgt_draw_initiator = vgt_draw_initiator;
1338 rdraw.indices = NULL;
1339 if (draw.index_buffer) {
1340 rbuffer = (struct r600_resource*)draw.index_buffer;
1341 rdraw.indices = rbuffer->bo;
1342 rdraw.indices_bo_offset = draw.index_buffer_offset;
1343 }
1344 evergreen_context_draw(&rctx->ctx, &rdraw);
1345
1346 if (translate)
1347 r600_end_vertex_translate(rctx);
1348
1349 pipe_resource_reference(&draw.index_buffer, NULL);
1350 }
1351
1352 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1353 {
1354 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1355 struct r600_pipe_state *rstate = &shader->rstate;
1356 struct r600_shader *rshader = &shader->shader;
1357 unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
1358 int pos_index = -1, face_index = -1;
1359 int ninterp = 0;
1360 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1361 unsigned spi_baryc_cntl;
1362
1363 /* clear previous register */
1364 rstate->nregs = 0;
1365
1366 for (i = 0; i < rshader->ninput; i++) {
1367 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
1368 /* evergreen NUM_INTERP only contains values interpolated into the LDS,
1369 POSITION goes via GPRs from the SC so isn't counted */
1370 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1371 pos_index = i;
1372 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1373 face_index = i;
1374 else {
1375 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
1376 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1377 ninterp++;
1378 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1379 have_linear = TRUE;
1380 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1381 have_perspective = TRUE;
1382 if (rshader->input[i].centroid)
1383 have_centroid = TRUE;
1384 }
1385 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
1386 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
1387 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
1388 tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
1389 }
1390 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
1391 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
1392 tmp |= S_028644_PT_SPRITE_TEX(1);
1393 }
1394 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
1395 }
1396 for (i = 0; i < rshader->noutput; i++) {
1397 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1398 r600_pipe_state_add_reg(rstate,
1399 R_02880C_DB_SHADER_CONTROL,
1400 S_02880C_Z_EXPORT_ENABLE(1),
1401 S_02880C_Z_EXPORT_ENABLE(1), NULL);
1402 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1403 r600_pipe_state_add_reg(rstate,
1404 R_02880C_DB_SHADER_CONTROL,
1405 S_02880C_STENCIL_EXPORT_ENABLE(1),
1406 S_02880C_STENCIL_EXPORT_ENABLE(1), NULL);
1407 }
1408
1409 exports_ps = 0;
1410 num_cout = 0;
1411 for (i = 0; i < rshader->noutput; i++) {
1412 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1413 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1414 exports_ps |= 1;
1415 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1416 num_cout++;
1417 }
1418 }
1419 exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
1420 if (!exports_ps) {
1421 /* always at least export 1 component per pixel */
1422 exports_ps = 2;
1423 }
1424
1425 if (ninterp == 0) {
1426 ninterp = 1;
1427 have_perspective = TRUE;
1428 }
1429
1430 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
1431 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
1432 S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
1433 spi_input_z = 0;
1434 if (pos_index != -1) {
1435 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) |
1436 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1437 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
1438 spi_input_z |= 1;
1439 }
1440
1441 spi_ps_in_control_1 = 0;
1442 if (face_index != -1) {
1443 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1444 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1445 }
1446
1447 spi_baryc_cntl = 0;
1448 if (have_perspective)
1449 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
1450 S_0286E0_PERSP_CENTROID_ENA(have_centroid);
1451 if (have_linear)
1452 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
1453 S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
1454
1455 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
1456 spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1457 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
1458 spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1459 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
1460 0, 0xFFFFFFFF, NULL);
1461 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1462 r600_pipe_state_add_reg(rstate,
1463 R_0286E0_SPI_BARYC_CNTL,
1464 spi_baryc_cntl,
1465 0xFFFFFFFF, NULL);
1466
1467 r600_pipe_state_add_reg(rstate,
1468 R_028840_SQ_PGM_START_PS,
1469 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1470 r600_pipe_state_add_reg(rstate,
1471 R_028844_SQ_PGM_RESOURCES_PS,
1472 S_028844_NUM_GPRS(rshader->bc.ngpr) |
1473 S_028844_PRIME_CACHE_ON_DRAW(1) |
1474 S_028844_STACK_SIZE(rshader->bc.nstack),
1475 0xFFFFFFFF, NULL);
1476 r600_pipe_state_add_reg(rstate,
1477 R_028848_SQ_PGM_RESOURCES_2_PS,
1478 0x0, 0xFFFFFFFF, NULL);
1479 r600_pipe_state_add_reg(rstate,
1480 R_02884C_SQ_PGM_EXPORTS_PS,
1481 exports_ps, 0xFFFFFFFF, NULL);
1482
1483 if (rshader->uses_kill) {
1484 /* only set some bits here, the other bits are set in the dsa state */
1485 r600_pipe_state_add_reg(rstate,
1486 R_02880C_DB_SHADER_CONTROL,
1487 S_02880C_KILL_ENABLE(1),
1488 S_02880C_KILL_ENABLE(1), NULL);
1489 }
1490
1491 r600_pipe_state_add_reg(rstate,
1492 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
1493 0xFFFFFFFF, NULL);
1494 }
1495
1496 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1497 {
1498 struct r600_pipe_state *rstate = &shader->rstate;
1499 struct r600_shader *rshader = &shader->shader;
1500 unsigned spi_vs_out_id[10];
1501 unsigned i, tmp;
1502
1503 /* clear previous register */
1504 rstate->nregs = 0;
1505
1506 /* so far never got proper semantic id from tgsi */
1507 for (i = 0; i < 10; i++) {
1508 spi_vs_out_id[i] = 0;
1509 }
1510 for (i = 0; i < 32; i++) {
1511 tmp = i << ((i & 3) * 8);
1512 spi_vs_out_id[i / 4] |= tmp;
1513 }
1514 for (i = 0; i < 10; i++) {
1515 r600_pipe_state_add_reg(rstate,
1516 R_02861C_SPI_VS_OUT_ID_0 + i * 4,
1517 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1518 }
1519
1520 r600_pipe_state_add_reg(rstate,
1521 R_0286C4_SPI_VS_OUT_CONFIG,
1522 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1523 0xFFFFFFFF, NULL);
1524 r600_pipe_state_add_reg(rstate,
1525 R_028860_SQ_PGM_RESOURCES_VS,
1526 S_028860_NUM_GPRS(rshader->bc.ngpr) |
1527 S_028860_STACK_SIZE(rshader->bc.nstack),
1528 0xFFFFFFFF, NULL);
1529 r600_pipe_state_add_reg(rstate,
1530 R_028864_SQ_PGM_RESOURCES_2_VS,
1531 0x0, 0xFFFFFFFF, NULL);
1532 r600_pipe_state_add_reg(rstate,
1533 R_0288A8_SQ_PGM_RESOURCES_FS,
1534 0x00000000, 0xFFFFFFFF, NULL);
1535 r600_pipe_state_add_reg(rstate,
1536 R_02885C_SQ_PGM_START_VS,
1537 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1538 r600_pipe_state_add_reg(rstate,
1539 R_0288A4_SQ_PGM_START_FS,
1540 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
1541
1542 r600_pipe_state_add_reg(rstate,
1543 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1544 0xFFFFFFFF, NULL);
1545 }
1546
1547 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
1548 {
1549 struct pipe_depth_stencil_alpha_state dsa;
1550 struct r600_pipe_state *rstate;
1551
1552 memset(&dsa, 0, sizeof(dsa));
1553
1554 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1555 r600_pipe_state_add_reg(rstate,
1556 R_02880C_DB_SHADER_CONTROL,
1557 0x0,
1558 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1559 r600_pipe_state_add_reg(rstate,
1560 R_028000_DB_RENDER_CONTROL,
1561 S_028000_DEPTH_COPY_ENABLE(1) |
1562 S_028000_STENCIL_COPY_ENABLE(1) |
1563 S_028000_COPY_CENTROID(1),
1564 S_028000_DEPTH_COPY_ENABLE(1) |
1565 S_028000_STENCIL_COPY_ENABLE(1) |
1566 S_028000_COPY_CENTROID(1), NULL);
1567 return rstate;
1568 }