src/gallium/drivers/r600/r600.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_H
  27 #define R600_H
  28
  29 #include <assert.h>
  30 #include <stdint.h>
  31 #include <stdio.h>
  32 #include <util/u_double_list.h>
  33 #include <pipe/p_compiler.h>
  34
  35 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  36
  37 #define R600_ERR(fmt, args...) \
  38         fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
  39
  40 typedef uint64_t                u64;
  41 typedef uint32_t                u32;
  42 typedef uint16_t                u16;
  43 typedef uint8_t                 u8;
  44
  45 struct radeon;
  46
  47 enum radeon_family {
  48         CHIP_UNKNOWN,
  49         CHIP_R100,
  50         CHIP_RV100,
  51         CHIP_RS100,
  52         CHIP_RV200,
  53         CHIP_RS200,
  54         CHIP_R200,
  55         CHIP_RV250,
  56         CHIP_RS300,
  57         CHIP_RV280,
  58         CHIP_R300,
  59         CHIP_R350,
  60         CHIP_RV350,
  61         CHIP_RV380,
  62         CHIP_R420,
  63         CHIP_R423,
  64         CHIP_RV410,
  65         CHIP_RS400,
  66         CHIP_RS480,
  67         CHIP_RS600,
  68         CHIP_RS690,
  69         CHIP_RS740,
  70         CHIP_RV515,
  71         CHIP_R520,
  72         CHIP_RV530,
  73         CHIP_RV560,
  74         CHIP_RV570,
  75         CHIP_R580,
  76         CHIP_R600,
  77         CHIP_RV610,
  78         CHIP_RV630,
  79         CHIP_RV670,
  80         CHIP_RV620,
  81         CHIP_RV635,
  82         CHIP_RS780,
  83         CHIP_RS880,
  84         CHIP_RV770,
  85         CHIP_RV730,
  86         CHIP_RV710,
  87         CHIP_RV740,
  88         CHIP_CEDAR,
  89         CHIP_REDWOOD,
  90         CHIP_JUNIPER,
  91         CHIP_CYPRESS,
  92         CHIP_HEMLOCK,
  93         CHIP_LAST,
  94 };
  95
  96 enum chip_class {
  97         R600,
  98         R700,
  99         EVERGREEN,
 100 };
 101
 102 struct r600_tiling_info {
 103         unsigned num_channels;
 104         unsigned num_banks;
 105         unsigned group_bytes;
 106 };
 107
 108 enum radeon_family r600_get_family(struct radeon *rw);
 109 enum chip_class r600_get_family_class(struct radeon *radeon);
 110 struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
 111
 112 /* r600_bo.c */
 113 struct r600_bo;
 114 struct r600_bo *r600_bo(struct radeon *radeon,
 115                                   unsigned size, unsigned alignment, unsigned usage);
 116 struct r600_bo *r600_bo_handle(struct radeon *radeon,
 117                                unsigned handle, unsigned *array_mode);
 118 void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
 119 void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
 120 void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
 121                             struct r600_bo *src);
 122 static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
 123 {
 124         return 0;
 125 }
 126
 127
 128 /* R600/R700 STATES */
 129 #define R600_GROUP_MAX                  16
 130 #define R600_BLOCK_MAX_BO               32
 131 #define R600_BLOCK_MAX_REG              128
 132
 133 struct r600_pipe_reg {
 134         u32                             offset;
 135         u32                             mask;
 136         u32                             value;
 137         struct r600_bo          *bo;
 138 };
 139
 140 struct r600_pipe_state {
 141         unsigned                        id;
 142         unsigned                        nregs;
 143         struct r600_pipe_reg            regs[R600_BLOCK_MAX_REG];
 144 };
 145
 146 static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
 147                                         u32 offset, u32 value, u32 mask,
 148                                         struct r600_bo *bo)
 149 {
 150         state->regs[state->nregs].offset = offset;
 151         state->regs[state->nregs].value = value;
 152         state->regs[state->nregs].mask = mask;
 153         state->regs[state->nregs].bo = bo;
 154         state->nregs++;
 155         assert(state->nregs < R600_BLOCK_MAX_REG);
 156 }
 157
 158 #define R600_BLOCK_STATUS_ENABLED       (1 << 0)
 159 #define R600_BLOCK_STATUS_DIRTY         (1 << 1)
 160
 161 struct r600_block_reloc {
 162         struct r600_bo          *bo;
 163         unsigned                flush_flags;
 164         unsigned                flush_mask;
 165         unsigned                bo_pm4_index;
 166 };
 167
 168 struct r600_block {
 169         struct list_head        list;
 170         unsigned                status;
 171         unsigned                start_offset;
 172         unsigned                pm4_ndwords;
 173         unsigned                pm4_flush_ndwords;
 174         unsigned                nbo;
 175         unsigned                nreg;
 176         u32                     *reg;
 177         u32                     pm4[R600_BLOCK_MAX_REG];
 178         unsigned                pm4_bo_index[R600_BLOCK_MAX_REG];
 179         struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
 180 };
 181
 182 struct r600_range {
 183         unsigned                start_offset;
 184         unsigned                end_offset;
 185         struct r600_block       **blocks;
 186 };
 187
 188 /*
 189  * relocation
 190  */
 191 #pragma pack(1)
 192 struct r600_reloc {
 193         uint32_t        handle;
 194         uint32_t        read_domain;
 195         uint32_t        write_domain;
 196         uint32_t        flags;
 197 };
 198 #pragma pack()
 199
 200 /*
 201  * query
 202  */
 203 struct r600_query {
 204         u64                                     result;
 205         /* The kind of query. Currently only OQ is supported. */
 206         unsigned                                type;
 207         /* How many results have been written, in dwords. It's incremented
 208          * after end_query and flush. */
 209         unsigned                                num_results;
 210         /* if we've flushed the query */
 211         unsigned                                state;
 212         /* The buffer where query results are stored. */
 213         struct r600_bo                  *buffer;
 214         unsigned                                buffer_size;
 215         /* linked list of queries */
 216         struct list_head                        list;
 217 };
 218
 219 #define R600_QUERY_STATE_STARTED        (1 << 0)
 220 #define R600_QUERY_STATE_ENDED          (1 << 1)
 221 #define R600_QUERY_STATE_SUSPENDED      (1 << 2)
 222
 223
 224 struct r600_context {
 225         struct radeon           *radeon;
 226         unsigned                hash_size;
 227         unsigned                hash_shift;
 228         struct r600_range       range[256];
 229         unsigned                nblocks;
 230         struct r600_block       **blocks;
 231         struct list_head        dirty;
 232         unsigned                pm4_ndwords;
 233         unsigned                pm4_cdwords;
 234         unsigned                pm4_dirty_cdwords;
 235         unsigned                ctx_pm4_ndwords;
 236         unsigned                nreloc;
 237         unsigned                creloc;
 238         struct r600_reloc       *reloc;
 239         struct radeon_bo        **bo;
 240         u32                     *pm4;
 241         struct list_head        query_list;
 242         unsigned                num_query_running;
 243         unsigned                fence;
 244         struct list_head        fenced_bo;
 245         unsigned                *cfence;
 246         struct r600_bo          *fence_bo;
 247 };
 248
 249 struct r600_draw {
 250         u32                     vgt_num_indices;
 251         u32                     vgt_num_instances;
 252         u32                     vgt_index_type;
 253         u32                     vgt_draw_initiator;
 254         u32                     indices_bo_offset;
 255         struct r600_bo          *indices;
 256 };
 257
 258 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
 259 void r600_context_fini(struct r600_context *ctx);
 260 void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state);
 261 void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 262 void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 263 void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 264 void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 265 void r600_context_flush(struct r600_context *ctx);
 266 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
 267 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 268
 269 struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
 270 void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
 271 boolean r600_context_query_result(struct r600_context *ctx,
 272                                 struct r600_query *query,
 273                                 boolean wait, void *vresult);
 274 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 275 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 276 void r600_context_queries_suspend(struct r600_context *ctx);
 277 void r600_context_queries_resume(struct r600_context *ctx);
 278
 279 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
 280 void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 281 void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 282 void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 283
 284 void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 285 void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
 286 void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 287 void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
 288
 289 #endif