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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / gallium / drivers / r600 / r600_asm.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_sq.h"
24 #include "r600_opcodes.h"
25 #include "r600_formats.h"
26 #include "r600_shader.h"
27 #include "r600d.h"
28
29 #include <errno.h>
30 #include "util/u_bitcast.h"
31 #include "util/u_dump.h"
32 #include "util/u_memory.h"
33 #include "util/u_math.h"
34 #include "pipe/p_shader_tokens.h"
35
36 #include "sb/sb_public.h"
37
38 #define NUM_OF_CYCLES 3
39 #define NUM_OF_COMPONENTS 4
40
41 static inline bool alu_writes(struct r600_bytecode_alu *alu)
42 {
43 return alu->dst.write || alu->is_op3;
44 }
45
46 static inline unsigned int r600_bytecode_get_num_operands(const struct r600_bytecode_alu *alu)
47 {
48 return r600_isa_alu(alu->op)->src_count;
49 }
50
51 static struct r600_bytecode_cf *r600_bytecode_cf(void)
52 {
53 struct r600_bytecode_cf *cf = CALLOC_STRUCT(r600_bytecode_cf);
54
55 if (!cf)
56 return NULL;
57 list_inithead(&cf->list);
58 list_inithead(&cf->alu);
59 list_inithead(&cf->vtx);
60 list_inithead(&cf->tex);
61 list_inithead(&cf->gds);
62 return cf;
63 }
64
65 static struct r600_bytecode_alu *r600_bytecode_alu(void)
66 {
67 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu);
68
69 if (!alu)
70 return NULL;
71 list_inithead(&alu->list);
72 return alu;
73 }
74
75 static struct r600_bytecode_vtx *r600_bytecode_vtx(void)
76 {
77 struct r600_bytecode_vtx *vtx = CALLOC_STRUCT(r600_bytecode_vtx);
78
79 if (!vtx)
80 return NULL;
81 list_inithead(&vtx->list);
82 return vtx;
83 }
84
85 static struct r600_bytecode_tex *r600_bytecode_tex(void)
86 {
87 struct r600_bytecode_tex *tex = CALLOC_STRUCT(r600_bytecode_tex);
88
89 if (!tex)
90 return NULL;
91 list_inithead(&tex->list);
92 return tex;
93 }
94
95 static struct r600_bytecode_gds *r600_bytecode_gds(void)
96 {
97 struct r600_bytecode_gds *gds = CALLOC_STRUCT(r600_bytecode_gds);
98
99 if (gds == NULL)
100 return NULL;
101 list_inithead(&gds->list);
102 return gds;
103 }
104
105 static unsigned stack_entry_size(enum radeon_family chip) {
106 /* Wavefront size:
107 * 64: R600/RV670/RV770/Cypress/R740/Barts/Turks/Caicos/
108 * Aruba/Sumo/Sumo2/redwood/juniper
109 * 32: R630/R730/R710/Palm/Cedar
110 * 16: R610/Rs780
111 *
112 * Stack row size:
113 * Wavefront Size 16 32 48 64
114 * Columns per Row (R6xx/R7xx/R8xx only) 8 8 4 4
115 * Columns per Row (R9xx+) 8 4 4 4 */
116
117 switch (chip) {
118 /* FIXME: are some chips missing here? */
119 /* wavefront size 16 */
120 case CHIP_RV610:
121 case CHIP_RS780:
122 case CHIP_RV620:
123 case CHIP_RS880:
124 /* wavefront size 32 */
125 case CHIP_RV630:
126 case CHIP_RV635:
127 case CHIP_RV730:
128 case CHIP_RV710:
129 case CHIP_PALM:
130 case CHIP_CEDAR:
131 return 8;
132
133 /* wavefront size 64 */
134 default:
135 return 4;
136 }
137 }
138
139 void r600_bytecode_init(struct r600_bytecode *bc,
140 enum chip_class chip_class,
141 enum radeon_family family,
142 bool has_compressed_msaa_texturing)
143 {
144 static unsigned next_shader_id = 0;
145
146 bc->debug_id = ++next_shader_id;
147
148 if ((chip_class == R600) &&
149 (family != CHIP_RV670 && family != CHIP_RS780 && family != CHIP_RS880)) {
150 bc->ar_handling = AR_HANDLE_RV6XX;
151 bc->r6xx_nop_after_rel_dst = 1;
152 } else {
153 bc->ar_handling = AR_HANDLE_NORMAL;
154 bc->r6xx_nop_after_rel_dst = 0;
155 }
156
157 list_inithead(&bc->cf);
158 bc->chip_class = chip_class;
159 bc->family = family;
160 bc->has_compressed_msaa_texturing = has_compressed_msaa_texturing;
161 bc->stack.entry_size = stack_entry_size(family);
162 }
163
164 int r600_bytecode_add_cf(struct r600_bytecode *bc)
165 {
166 struct r600_bytecode_cf *cf = r600_bytecode_cf();
167
168 if (!cf)
169 return -ENOMEM;
170 list_addtail(&cf->list, &bc->cf);
171 if (bc->cf_last) {
172 cf->id = bc->cf_last->id + 2;
173 if (bc->cf_last->eg_alu_extended) {
174 /* take into account extended alu size */
175 cf->id += 2;
176 bc->ndw += 2;
177 }
178 }
179 bc->cf_last = cf;
180 bc->ncf++;
181 bc->ndw += 2;
182 bc->force_add_cf = 0;
183 bc->ar_loaded = 0;
184 return 0;
185 }
186
187 int r600_bytecode_add_output(struct r600_bytecode *bc,
188 const struct r600_bytecode_output *output)
189 {
190 int r;
191
192 if (output->gpr >= bc->ngpr)
193 bc->ngpr = output->gpr + 1;
194
195 if (bc->cf_last && (bc->cf_last->op == output->op ||
196 (bc->cf_last->op == CF_OP_EXPORT &&
197 output->op == CF_OP_EXPORT_DONE)) &&
198 output->type == bc->cf_last->output.type &&
199 output->elem_size == bc->cf_last->output.elem_size &&
200 output->swizzle_x == bc->cf_last->output.swizzle_x &&
201 output->swizzle_y == bc->cf_last->output.swizzle_y &&
202 output->swizzle_z == bc->cf_last->output.swizzle_z &&
203 output->swizzle_w == bc->cf_last->output.swizzle_w &&
204 output->comp_mask == bc->cf_last->output.comp_mask &&
205 (output->burst_count + bc->cf_last->output.burst_count) <= 16) {
206
207 if ((output->gpr + output->burst_count) == bc->cf_last->output.gpr &&
208 (output->array_base + output->burst_count) == bc->cf_last->output.array_base) {
209
210 bc->cf_last->op = bc->cf_last->output.op = output->op;
211 bc->cf_last->output.gpr = output->gpr;
212 bc->cf_last->output.array_base = output->array_base;
213 bc->cf_last->output.burst_count += output->burst_count;
214 return 0;
215
216 } else if (output->gpr == (bc->cf_last->output.gpr + bc->cf_last->output.burst_count) &&
217 output->array_base == (bc->cf_last->output.array_base + bc->cf_last->output.burst_count)) {
218
219 bc->cf_last->op = bc->cf_last->output.op = output->op;
220 bc->cf_last->output.burst_count += output->burst_count;
221 return 0;
222 }
223 }
224
225 r = r600_bytecode_add_cf(bc);
226 if (r)
227 return r;
228 bc->cf_last->op = output->op;
229 memcpy(&bc->cf_last->output, output, sizeof(struct r600_bytecode_output));
230 bc->cf_last->barrier = 1;
231 return 0;
232 }
233
234 int r600_bytecode_add_pending_output(struct r600_bytecode *bc,
235 const struct r600_bytecode_output *output)
236 {
237 assert(bc->n_pending_outputs + 1 < ARRAY_SIZE(bc->pending_outputs));
238 bc->pending_outputs[bc->n_pending_outputs++] = *output;
239
240 return 0;
241 }
242
243 void r600_bytecode_need_wait_ack(struct r600_bytecode *bc, boolean need_wait_ack)
244 {
245 bc->need_wait_ack = need_wait_ack;
246 }
247
248 boolean r600_bytecode_get_need_wait_ack(struct r600_bytecode *bc)
249 {
250 return bc->need_wait_ack;
251 }
252
253 /* alu instructions that can ony exits once per group */
254 static int is_alu_once_inst(struct r600_bytecode_alu *alu)
255 {
256 return r600_isa_alu(alu->op)->flags & (AF_KILL | AF_PRED) || alu->is_lds_idx_op || alu->op == ALU_OP0_GROUP_BARRIER;
257 }
258
259 static int is_alu_reduction_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
260 {
261 return (r600_isa_alu(alu->op)->flags & AF_REPL) &&
262 (r600_isa_alu_slots(bc->isa->hw_class, alu->op) == AF_4V);
263 }
264
265 static int is_alu_mova_inst(struct r600_bytecode_alu *alu)
266 {
267 return r600_isa_alu(alu->op)->flags & AF_MOVA;
268 }
269
270 static int alu_uses_rel(struct r600_bytecode_alu *alu)
271 {
272 unsigned num_src = r600_bytecode_get_num_operands(alu);
273 unsigned src;
274
275 if (alu->dst.rel) {
276 return 1;
277 }
278
279 for (src = 0; src < num_src; ++src) {
280 if (alu->src[src].rel) {
281 return 1;
282 }
283 }
284 return 0;
285 }
286
287 static int is_lds_read(int sel)
288 {
289 return sel == EG_V_SQ_ALU_SRC_LDS_OQ_A_POP || sel == EG_V_SQ_ALU_SRC_LDS_OQ_B_POP;
290 }
291
292 static int alu_uses_lds(struct r600_bytecode_alu *alu)
293 {
294 unsigned num_src = r600_bytecode_get_num_operands(alu);
295 unsigned src;
296
297 for (src = 0; src < num_src; ++src) {
298 if (is_lds_read(alu->src[src].sel)) {
299 return 1;
300 }
301 }
302 return 0;
303 }
304
305 static int is_alu_64bit_inst(struct r600_bytecode_alu *alu)
306 {
307 const struct alu_op_info *op = r600_isa_alu(alu->op);
308 return (op->flags & AF_64);
309 }
310
311 static int is_alu_vec_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
312 {
313 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
314 return !(slots & AF_S);
315 }
316
317 static int is_alu_trans_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
318 {
319 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
320 return !(slots & AF_V);
321 }
322
323 /* alu instructions that can execute on any unit */
324 static int is_alu_any_unit_inst(struct r600_bytecode *bc, struct r600_bytecode_alu *alu)
325 {
326 unsigned slots = r600_isa_alu_slots(bc->isa->hw_class, alu->op);
327 return slots == AF_VS;
328 }
329
330 static int is_nop_inst(struct r600_bytecode_alu *alu)
331 {
332 return alu->op == ALU_OP0_NOP;
333 }
334
335 static int assign_alu_units(struct r600_bytecode *bc, struct r600_bytecode_alu *alu_first,
336 struct r600_bytecode_alu *assignment[5])
337 {
338 struct r600_bytecode_alu *alu;
339 unsigned i, chan, trans;
340 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
341
342 for (i = 0; i < max_slots; i++)
343 assignment[i] = NULL;
344
345 for (alu = alu_first; alu; alu = LIST_ENTRY(struct r600_bytecode_alu, alu->list.next, list)) {
346 chan = alu->dst.chan;
347 if (max_slots == 4)
348 trans = 0;
349 else if (is_alu_trans_unit_inst(bc, alu))
350 trans = 1;
351 else if (is_alu_vec_unit_inst(bc, alu))
352 trans = 0;
353 else if (assignment[chan])
354 trans = 1; /* Assume ALU_INST_PREFER_VECTOR. */
355 else
356 trans = 0;
357
358 if (trans) {
359 if (assignment[4]) {
360 assert(0); /* ALU.Trans has already been allocated. */
361 return -1;
362 }
363 assignment[4] = alu;
364 } else {
365 if (assignment[chan]) {
366 assert(0); /* ALU.chan has already been allocated. */
367 return -1;
368 }
369 assignment[chan] = alu;
370 }
371
372 if (alu->last)
373 break;
374 }
375 return 0;
376 }
377
378 struct alu_bank_swizzle {
379 int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
380 int hw_cfile_addr[4];
381 int hw_cfile_elem[4];
382 };
383
384 static const unsigned cycle_for_bank_swizzle_vec[][3] = {
385 [SQ_ALU_VEC_012] = { 0, 1, 2 },
386 [SQ_ALU_VEC_021] = { 0, 2, 1 },
387 [SQ_ALU_VEC_120] = { 1, 2, 0 },
388 [SQ_ALU_VEC_102] = { 1, 0, 2 },
389 [SQ_ALU_VEC_201] = { 2, 0, 1 },
390 [SQ_ALU_VEC_210] = { 2, 1, 0 }
391 };
392
393 static const unsigned cycle_for_bank_swizzle_scl[][3] = {
394 [SQ_ALU_SCL_210] = { 2, 1, 0 },
395 [SQ_ALU_SCL_122] = { 1, 2, 2 },
396 [SQ_ALU_SCL_212] = { 2, 1, 2 },
397 [SQ_ALU_SCL_221] = { 2, 2, 1 }
398 };
399
400 static void init_bank_swizzle(struct alu_bank_swizzle *bs)
401 {
402 int i, cycle, component;
403 /* set up gpr use */
404 for (cycle = 0; cycle < NUM_OF_CYCLES; cycle++)
405 for (component = 0; component < NUM_OF_COMPONENTS; component++)
406 bs->hw_gpr[cycle][component] = -1;
407 for (i = 0; i < 4; i++)
408 bs->hw_cfile_addr[i] = -1;
409 for (i = 0; i < 4; i++)
410 bs->hw_cfile_elem[i] = -1;
411 }
412
413 static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan, unsigned cycle)
414 {
415 if (bs->hw_gpr[cycle][chan] == -1)
416 bs->hw_gpr[cycle][chan] = sel;
417 else if (bs->hw_gpr[cycle][chan] != (int)sel) {
418 /* Another scalar operation has already used the GPR read port for the channel. */
419 return -1;
420 }
421 return 0;
422 }
423
424 static int reserve_cfile(const struct r600_bytecode *bc,
425 struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
426 {
427 int res, num_res = 4;
428 if (bc->chip_class >= R700) {
429 num_res = 2;
430 chan /= 2;
431 }
432 for (res = 0; res < num_res; ++res) {
433 if (bs->hw_cfile_addr[res] == -1) {
434 bs->hw_cfile_addr[res] = sel;
435 bs->hw_cfile_elem[res] = chan;
436 return 0;
437 } else if (bs->hw_cfile_addr[res] == sel &&
438 bs->hw_cfile_elem[res] == chan)
439 return 0; /* Read for this scalar element already reserved, nothing to do here. */
440 }
441 /* All cfile read ports are used, cannot reference vector element. */
442 return -1;
443 }
444
445 static int is_gpr(unsigned sel)
446 {
447 return (sel <= 127);
448 }
449
450 /* CB constants start at 512, and get translated to a kcache index when ALU
451 * clauses are constructed. Note that we handle kcache constants the same way
452 * as (the now gone) cfile constants, is that really required? */
453 static int is_cfile(unsigned sel)
454 {
455 return (sel > 255 && sel < 512) ||
456 (sel > 511 && sel < 4607) || /* Kcache before translation. */
457 (sel > 127 && sel < 192); /* Kcache after translation. */
458 }
459
460 static int is_const(int sel)
461 {
462 return is_cfile(sel) ||
463 (sel >= V_SQ_ALU_SRC_0 &&
464 sel <= V_SQ_ALU_SRC_LITERAL);
465 }
466
467 static int check_vector(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
468 struct alu_bank_swizzle *bs, int bank_swizzle)
469 {
470 int r, src, num_src, sel, elem, cycle;
471
472 num_src = r600_bytecode_get_num_operands(alu);
473 for (src = 0; src < num_src; src++) {
474 sel = alu->src[src].sel;
475 elem = alu->src[src].chan;
476 if (is_gpr(sel)) {
477 cycle = cycle_for_bank_swizzle_vec[bank_swizzle][src];
478 if (src == 1 && sel == alu->src[0].sel && elem == alu->src[0].chan)
479 /* Nothing to do; special-case optimization,
480 * second source uses first source’s reservation. */
481 continue;
482 else {
483 r = reserve_gpr(bs, sel, elem, cycle);
484 if (r)
485 return r;
486 }
487 } else if (is_cfile(sel)) {
488 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
489 if (r)
490 return r;
491 }
492 /* No restrictions on PV, PS, literal or special constants. */
493 }
494 return 0;
495 }
496
497 static int check_scalar(const struct r600_bytecode *bc, const struct r600_bytecode_alu *alu,
498 struct alu_bank_swizzle *bs, int bank_swizzle)
499 {
500 int r, src, num_src, const_count, sel, elem, cycle;
501
502 num_src = r600_bytecode_get_num_operands(alu);
503 for (const_count = 0, src = 0; src < num_src; ++src) {
504 sel = alu->src[src].sel;
505 elem = alu->src[src].chan;
506 if (is_const(sel)) { /* Any constant, including literal and inline constants. */
507 if (const_count >= 2)
508 /* More than two references to a constant in
509 * transcendental operation. */
510 return -1;
511 else
512 const_count++;
513 }
514 if (is_cfile(sel)) {
515 r = reserve_cfile(bc, bs, (alu->src[src].kc_bank<<16) + sel, elem);
516 if (r)
517 return r;
518 }
519 }
520 for (src = 0; src < num_src; ++src) {
521 sel = alu->src[src].sel;
522 elem = alu->src[src].chan;
523 if (is_gpr(sel)) {
524 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
525 if (cycle < const_count)
526 /* Cycle for GPR load conflicts with
527 * constant load in transcendental operation. */
528 return -1;
529 r = reserve_gpr(bs, sel, elem, cycle);
530 if (r)
531 return r;
532 }
533 /* PV PS restrictions */
534 if (const_count && (sel == 254 || sel == 255)) {
535 cycle = cycle_for_bank_swizzle_scl[bank_swizzle][src];
536 if (cycle < const_count)
537 return -1;
538 }
539 }
540 return 0;
541 }
542
543 static int check_and_set_bank_swizzle(const struct r600_bytecode *bc,
544 struct r600_bytecode_alu *slots[5])
545 {
546 struct alu_bank_swizzle bs;
547 int bank_swizzle[5];
548 int i, r = 0, forced = 1;
549 boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
550 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
551
552 for (i = 0; i < max_slots; i++) {
553 if (slots[i]) {
554 if (slots[i]->bank_swizzle_force) {
555 slots[i]->bank_swizzle = slots[i]->bank_swizzle_force;
556 } else {
557 forced = 0;
558 }
559 }
560
561 if (i < 4 && slots[i])
562 scalar_only = false;
563 }
564 if (forced)
565 return 0;
566
567 /* Just check every possible combination of bank swizzle.
568 * Not very efficent, but works on the first try in most of the cases. */
569 for (i = 0; i < 4; i++)
570 if (!slots[i] || !slots[i]->bank_swizzle_force)
571 bank_swizzle[i] = SQ_ALU_VEC_012;
572 else
573 bank_swizzle[i] = slots[i]->bank_swizzle;
574
575 bank_swizzle[4] = SQ_ALU_SCL_210;
576 while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
577
578 init_bank_swizzle(&bs);
579 if (scalar_only == false) {
580 for (i = 0; i < 4; i++) {
581 if (slots[i]) {
582 r = check_vector(bc, slots[i], &bs, bank_swizzle[i]);
583 if (r)
584 break;
585 }
586 }
587 } else
588 r = 0;
589
590 if (!r && max_slots == 5 && slots[4]) {
591 r = check_scalar(bc, slots[4], &bs, bank_swizzle[4]);
592 }
593 if (!r) {
594 for (i = 0; i < max_slots; i++) {
595 if (slots[i])
596 slots[i]->bank_swizzle = bank_swizzle[i];
597 }
598 return 0;
599 }
600
601 if (scalar_only) {
602 bank_swizzle[4]++;
603 } else {
604 for (i = 0; i < max_slots; i++) {
605 if (!slots[i] || !slots[i]->bank_swizzle_force) {
606 bank_swizzle[i]++;
607 if (bank_swizzle[i] <= SQ_ALU_VEC_210)
608 break;
609 else if (i < max_slots - 1)
610 bank_swizzle[i] = SQ_ALU_VEC_012;
611 else
612 return -1;
613 }
614 }
615 }
616 }
617
618 /* Couldn't find a working swizzle. */
619 return -1;
620 }
621
622 static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
623 struct r600_bytecode_alu *slots[5], struct r600_bytecode_alu *alu_prev)
624 {
625 struct r600_bytecode_alu *prev[5];
626 int gpr[5], chan[5];
627 int i, j, r, src, num_src;
628 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
629
630 r = assign_alu_units(bc, alu_prev, prev);
631 if (r)
632 return r;
633
634 for (i = 0; i < max_slots; ++i) {
635 if (prev[i] && alu_writes(prev[i]) && !prev[i]->dst.rel) {
636
637 if (is_alu_64bit_inst(prev[i])) {
638 gpr[i] = -1;
639 continue;
640 }
641
642 gpr[i] = prev[i]->dst.sel;
643 /* cube writes more than PV.X */
644 if (is_alu_reduction_inst(bc, prev[i]))
645 chan[i] = 0;
646 else
647 chan[i] = prev[i]->dst.chan;
648 } else
649 gpr[i] = -1;
650 }
651
652 for (i = 0; i < max_slots; ++i) {
653 struct r600_bytecode_alu *alu = slots[i];
654 if (!alu)
655 continue;
656
657 if (is_alu_64bit_inst(alu))
658 continue;
659 num_src = r600_bytecode_get_num_operands(alu);
660 for (src = 0; src < num_src; ++src) {
661 if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
662 continue;
663
664 if (bc->chip_class < CAYMAN) {
665 if (alu->src[src].sel == gpr[4] &&
666 alu->src[src].chan == chan[4] &&
667 alu_prev->pred_sel == alu->pred_sel) {
668 alu->src[src].sel = V_SQ_ALU_SRC_PS;
669 alu->src[src].chan = 0;
670 continue;
671 }
672 }
673
674 for (j = 0; j < 4; ++j) {
675 if (alu->src[src].sel == gpr[j] &&
676 alu->src[src].chan == j &&
677 alu_prev->pred_sel == alu->pred_sel) {
678 alu->src[src].sel = V_SQ_ALU_SRC_PV;
679 alu->src[src].chan = chan[j];
680 break;
681 }
682 }
683 }
684 }
685
686 return 0;
687 }
688
689 void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg, unsigned abs)
690 {
691 switch(value) {
692 case 0:
693 *sel = V_SQ_ALU_SRC_0;
694 break;
695 case 1:
696 *sel = V_SQ_ALU_SRC_1_INT;
697 break;
698 case -1:
699 *sel = V_SQ_ALU_SRC_M_1_INT;
700 break;
701 case 0x3F800000: /* 1.0f */
702 *sel = V_SQ_ALU_SRC_1;
703 break;
704 case 0x3F000000: /* 0.5f */
705 *sel = V_SQ_ALU_SRC_0_5;
706 break;
707 case 0xBF800000: /* -1.0f */
708 *sel = V_SQ_ALU_SRC_1;
709 *neg ^= !abs;
710 break;
711 case 0xBF000000: /* -0.5f */
712 *sel = V_SQ_ALU_SRC_0_5;
713 *neg ^= !abs;
714 break;
715 default:
716 *sel = V_SQ_ALU_SRC_LITERAL;
717 break;
718 }
719 }
720
721 /* compute how many literal are needed */
722 static int r600_bytecode_alu_nliterals(struct r600_bytecode_alu *alu,
723 uint32_t literal[4], unsigned *nliteral)
724 {
725 unsigned num_src = r600_bytecode_get_num_operands(alu);
726 unsigned i, j;
727
728 for (i = 0; i < num_src; ++i) {
729 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
730 uint32_t value = alu->src[i].value;
731 unsigned found = 0;
732 for (j = 0; j < *nliteral; ++j) {
733 if (literal[j] == value) {
734 found = 1;
735 break;
736 }
737 }
738 if (!found) {
739 if (*nliteral >= 4)
740 return -EINVAL;
741 literal[(*nliteral)++] = value;
742 }
743 }
744 }
745 return 0;
746 }
747
748 static void r600_bytecode_alu_adjust_literals(struct r600_bytecode_alu *alu,
749 uint32_t literal[4], unsigned nliteral)
750 {
751 unsigned num_src = r600_bytecode_get_num_operands(alu);
752 unsigned i, j;
753
754 for (i = 0; i < num_src; ++i) {
755 if (alu->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
756 uint32_t value = alu->src[i].value;
757 for (j = 0; j < nliteral; ++j) {
758 if (literal[j] == value) {
759 alu->src[i].chan = j;
760 break;
761 }
762 }
763 }
764 }
765 }
766
767 static int merge_inst_groups(struct r600_bytecode *bc, struct r600_bytecode_alu *slots[5],
768 struct r600_bytecode_alu *alu_prev)
769 {
770 struct r600_bytecode_alu *prev[5];
771 struct r600_bytecode_alu *result[5] = { NULL };
772
773 uint32_t literal[4], prev_literal[4];
774 unsigned nliteral = 0, prev_nliteral = 0;
775
776 int i, j, r, src, num_src;
777 int num_once_inst = 0;
778 int have_mova = 0, have_rel = 0;
779 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
780
781 r = assign_alu_units(bc, alu_prev, prev);
782 if (r)
783 return r;
784
785 for (i = 0; i < max_slots; ++i) {
786 if (prev[i]) {
787 if (prev[i]->pred_sel)
788 return 0;
789 if (is_alu_once_inst(prev[i]))
790 return 0;
791 }
792 if (slots[i]) {
793 if (slots[i]->pred_sel)
794 return 0;
795 if (is_alu_once_inst(slots[i]))
796 return 0;
797 }
798 }
799
800 for (i = 0; i < max_slots; ++i) {
801 struct r600_bytecode_alu *alu;
802
803 if (num_once_inst > 0)
804 return 0;
805
806 /* check number of literals */
807 if (prev[i]) {
808 if (r600_bytecode_alu_nliterals(prev[i], literal, &nliteral))
809 return 0;
810 if (r600_bytecode_alu_nliterals(prev[i], prev_literal, &prev_nliteral))
811 return 0;
812 if (is_alu_mova_inst(prev[i])) {
813 if (have_rel)
814 return 0;
815 have_mova = 1;
816 }
817
818 if (alu_uses_rel(prev[i])) {
819 if (have_mova) {
820 return 0;
821 }
822 have_rel = 1;
823 }
824 if (alu_uses_lds(prev[i]))
825 return 0;
826
827 num_once_inst += is_alu_once_inst(prev[i]);
828 }
829 if (slots[i] && r600_bytecode_alu_nliterals(slots[i], literal, &nliteral))
830 return 0;
831
832 /* Let's check used slots. */
833 if (prev[i] && !slots[i]) {
834 result[i] = prev[i];
835 continue;
836 } else if (prev[i] && slots[i]) {
837 if (max_slots == 5 && result[4] == NULL && prev[4] == NULL && slots[4] == NULL) {
838 /* Trans unit is still free try to use it. */
839 if (is_alu_any_unit_inst(bc, slots[i]) && !alu_uses_lds(slots[i])) {
840 result[i] = prev[i];
841 result[4] = slots[i];
842 } else if (is_alu_any_unit_inst(bc, prev[i])) {
843 if (slots[i]->dst.sel == prev[i]->dst.sel &&
844 alu_writes(slots[i]) &&
845 alu_writes(prev[i]))
846 return 0;
847
848 result[i] = slots[i];
849 result[4] = prev[i];
850 } else
851 return 0;
852 } else
853 return 0;
854 } else if(!slots[i]) {
855 continue;
856 } else {
857 if (max_slots == 5 && slots[i] && prev[4] &&
858 slots[i]->dst.sel == prev[4]->dst.sel &&
859 slots[i]->dst.chan == prev[4]->dst.chan &&
860 alu_writes(slots[i]) &&
861 alu_writes(prev[4]))
862 return 0;
863
864 result[i] = slots[i];
865 }
866
867 alu = slots[i];
868 num_once_inst += is_alu_once_inst(alu);
869
870 /* don't reschedule NOPs */
871 if (is_nop_inst(alu))
872 return 0;
873
874 if (is_alu_mova_inst(alu)) {
875 if (have_rel) {
876 return 0;
877 }
878 have_mova = 1;
879 }
880
881 if (alu_uses_rel(alu)) {
882 if (have_mova) {
883 return 0;
884 }
885 have_rel = 1;
886 }
887
888 if (alu->op == ALU_OP0_SET_CF_IDX0 ||
889 alu->op == ALU_OP0_SET_CF_IDX1)
890 return 0; /* data hazard with MOVA */
891
892 /* Let's check source gprs */
893 num_src = r600_bytecode_get_num_operands(alu);
894 for (src = 0; src < num_src; ++src) {
895
896 /* Constants don't matter. */
897 if (!is_gpr(alu->src[src].sel))
898 continue;
899
900 for (j = 0; j < max_slots; ++j) {
901 if (!prev[j] || !alu_writes(prev[j]))
902 continue;
903
904 /* If it's relative then we can't determin which gpr is really used. */
905 if (prev[j]->dst.chan == alu->src[src].chan &&
906 (prev[j]->dst.sel == alu->src[src].sel ||
907 prev[j]->dst.rel || alu->src[src].rel))
908 return 0;
909 }
910 }
911 }
912
913 /* more than one PRED_ or KILL_ ? */
914 if (num_once_inst > 1)
915 return 0;
916
917 /* check if the result can still be swizzlet */
918 r = check_and_set_bank_swizzle(bc, result);
919 if (r)
920 return 0;
921
922 /* looks like everything worked out right, apply the changes */
923
924 /* undo adding previus literals */
925 bc->cf_last->ndw -= align(prev_nliteral, 2);
926
927 /* sort instructions */
928 for (i = 0; i < max_slots; ++i) {
929 slots[i] = result[i];
930 if (result[i]) {
931 list_del(&result[i]->list);
932 result[i]->last = 0;
933 list_addtail(&result[i]->list, &bc->cf_last->alu);
934 }
935 }
936
937 /* determine new last instruction */
938 LIST_ENTRY(struct r600_bytecode_alu, bc->cf_last->alu.prev, list)->last = 1;
939
940 /* determine new first instruction */
941 for (i = 0; i < max_slots; ++i) {
942 if (result[i]) {
943 bc->cf_last->curr_bs_head = result[i];
944 break;
945 }
946 }
947
948 bc->cf_last->prev_bs_head = bc->cf_last->prev2_bs_head;
949 bc->cf_last->prev2_bs_head = NULL;
950
951 return 0;
952 }
953
954 /* we'll keep kcache sets sorted by bank & addr */
955 static int r600_bytecode_alloc_kcache_line(struct r600_bytecode *bc,
956 struct r600_bytecode_kcache *kcache,
957 unsigned bank, unsigned line, unsigned index_mode)
958 {
959 int i, kcache_banks = bc->chip_class >= EVERGREEN ? 4 : 2;
960
961 for (i = 0; i < kcache_banks; i++) {
962 if (kcache[i].mode) {
963 int d;
964
965 if (kcache[i].bank < bank)
966 continue;
967
968 if ((kcache[i].bank == bank && kcache[i].addr > line+1) ||
969 kcache[i].bank > bank) {
970 /* try to insert new line */
971 if (kcache[kcache_banks-1].mode) {
972 /* all sets are in use */
973 return -ENOMEM;
974 }
975
976 memmove(&kcache[i+1],&kcache[i], (kcache_banks-i-1)*sizeof(struct r600_bytecode_kcache));
977 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
978 kcache[i].bank = bank;
979 kcache[i].addr = line;
980 kcache[i].index_mode = index_mode;
981 return 0;
982 }
983
984 d = line - kcache[i].addr;
985
986 if (d == -1) {
987 kcache[i].addr--;
988 if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_2) {
989 /* we are prepending the line to the current set,
990 * discarding the existing second line,
991 * so we'll have to insert line+2 after it */
992 line += 2;
993 continue;
994 } else if (kcache[i].mode == V_SQ_CF_KCACHE_LOCK_1) {
995 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
996 return 0;
997 } else {
998 /* V_SQ_CF_KCACHE_LOCK_LOOP_INDEX is not supported */
999 return -ENOMEM;
1000 }
1001 } else if (d == 1) {
1002 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_2;
1003 return 0;
1004 } else if (d == 0)
1005 return 0;
1006 } else { /* free kcache set - use it */
1007 kcache[i].mode = V_SQ_CF_KCACHE_LOCK_1;
1008 kcache[i].bank = bank;
1009 kcache[i].addr = line;
1010 kcache[i].index_mode = index_mode;
1011 return 0;
1012 }
1013 }
1014 return -ENOMEM;
1015 }
1016
1017 static int r600_bytecode_alloc_inst_kcache_lines(struct r600_bytecode *bc,
1018 struct r600_bytecode_kcache *kcache,
1019 struct r600_bytecode_alu *alu)
1020 {
1021 int i, r;
1022
1023 for (i = 0; i < 3; i++) {
1024 unsigned bank, line, sel = alu->src[i].sel, index_mode;
1025
1026 if (sel < 512)
1027 continue;
1028
1029 bank = alu->src[i].kc_bank;
1030 assert(bank < R600_MAX_HW_CONST_BUFFERS);
1031 line = (sel-512)>>4;
1032 index_mode = alu->src[i].kc_rel ? 1 : 0; // V_SQ_CF_INDEX_0 / V_SQ_CF_INDEX_NONE
1033
1034 if ((r = r600_bytecode_alloc_kcache_line(bc, kcache, bank, line, index_mode)))
1035 return r;
1036 }
1037 return 0;
1038 }
1039
1040 static int r600_bytecode_assign_kcache_banks(
1041 struct r600_bytecode_alu *alu,
1042 struct r600_bytecode_kcache * kcache)
1043 {
1044 int i, j;
1045
1046 /* Alter the src operands to refer to the kcache. */
1047 for (i = 0; i < 3; ++i) {
1048 static const unsigned int base[] = {128, 160, 256, 288};
1049 unsigned int line, sel = alu->src[i].sel, found = 0;
1050
1051 if (sel < 512)
1052 continue;
1053
1054 sel -= 512;
1055 line = sel>>4;
1056
1057 for (j = 0; j < 4 && !found; ++j) {
1058 switch (kcache[j].mode) {
1059 case V_SQ_CF_KCACHE_NOP:
1060 case V_SQ_CF_KCACHE_LOCK_LOOP_INDEX:
1061 R600_ERR("unexpected kcache line mode\n");
1062 return -ENOMEM;
1063 default:
1064 if (kcache[j].bank == alu->src[i].kc_bank &&
1065 kcache[j].addr <= line &&
1066 line < kcache[j].addr + kcache[j].mode) {
1067 alu->src[i].sel = sel - (kcache[j].addr<<4);
1068 alu->src[i].sel += base[j];
1069 found=1;
1070 }
1071 }
1072 }
1073 }
1074 return 0;
1075 }
1076
1077 static int r600_bytecode_alloc_kcache_lines(struct r600_bytecode *bc,
1078 struct r600_bytecode_alu *alu,
1079 unsigned type)
1080 {
1081 struct r600_bytecode_kcache kcache_sets[4];
1082 struct r600_bytecode_kcache *kcache = kcache_sets;
1083 int r;
1084
1085 memcpy(kcache, bc->cf_last->kcache, 4 * sizeof(struct r600_bytecode_kcache));
1086
1087 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1088 /* can't alloc, need to start new clause */
1089 if ((r = r600_bytecode_add_cf(bc))) {
1090 return r;
1091 }
1092 bc->cf_last->op = type;
1093
1094 /* retry with the new clause */
1095 kcache = bc->cf_last->kcache;
1096 if ((r = r600_bytecode_alloc_inst_kcache_lines(bc, kcache, alu))) {
1097 /* can't alloc again- should never happen */
1098 return r;
1099 }
1100 } else {
1101 /* update kcache sets */
1102 memcpy(bc->cf_last->kcache, kcache, 4 * sizeof(struct r600_bytecode_kcache));
1103 }
1104
1105 /* if we actually used more than 2 kcache sets, or have relative indexing - use ALU_EXTENDED on eg+ */
1106 if (kcache[2].mode != V_SQ_CF_KCACHE_NOP ||
1107 kcache[0].index_mode || kcache[1].index_mode || kcache[2].index_mode || kcache[3].index_mode) {
1108 if (bc->chip_class < EVERGREEN)
1109 return -ENOMEM;
1110 bc->cf_last->eg_alu_extended = 1;
1111 }
1112
1113 return 0;
1114 }
1115
1116 static int insert_nop_r6xx(struct r600_bytecode *bc)
1117 {
1118 struct r600_bytecode_alu alu;
1119 int r, i;
1120
1121 for (i = 0; i < 4; i++) {
1122 memset(&alu, 0, sizeof(alu));
1123 alu.op = ALU_OP0_NOP;
1124 alu.src[0].chan = i;
1125 alu.dst.chan = i;
1126 alu.last = (i == 3);
1127 r = r600_bytecode_add_alu(bc, &alu);
1128 if (r)
1129 return r;
1130 }
1131 return 0;
1132 }
1133
1134 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1135 static int load_ar_r6xx(struct r600_bytecode *bc)
1136 {
1137 struct r600_bytecode_alu alu;
1138 int r;
1139
1140 if (bc->ar_loaded)
1141 return 0;
1142
1143 /* hack to avoid making MOVA the last instruction in the clause */
1144 if ((bc->cf_last->ndw>>1) >= 110)
1145 bc->force_add_cf = 1;
1146
1147 memset(&alu, 0, sizeof(alu));
1148 alu.op = ALU_OP1_MOVA_GPR_INT;
1149 alu.src[0].sel = bc->ar_reg;
1150 alu.src[0].chan = bc->ar_chan;
1151 alu.last = 1;
1152 alu.index_mode = INDEX_MODE_LOOP;
1153 r = r600_bytecode_add_alu(bc, &alu);
1154 if (r)
1155 return r;
1156
1157 /* no requirement to set uses waterfall on MOVA_GPR_INT */
1158 bc->ar_loaded = 1;
1159 return 0;
1160 }
1161
1162 /* load AR register from gpr (bc->ar_reg) with MOVA_INT */
1163 static int load_ar(struct r600_bytecode *bc)
1164 {
1165 struct r600_bytecode_alu alu;
1166 int r;
1167
1168 if (bc->ar_handling)
1169 return load_ar_r6xx(bc);
1170
1171 if (bc->ar_loaded)
1172 return 0;
1173
1174 /* hack to avoid making MOVA the last instruction in the clause */
1175 if ((bc->cf_last->ndw>>1) >= 110)
1176 bc->force_add_cf = 1;
1177
1178 memset(&alu, 0, sizeof(alu));
1179 alu.op = ALU_OP1_MOVA_INT;
1180 alu.src[0].sel = bc->ar_reg;
1181 alu.src[0].chan = bc->ar_chan;
1182 alu.last = 1;
1183 r = r600_bytecode_add_alu(bc, &alu);
1184 if (r)
1185 return r;
1186
1187 bc->cf_last->r6xx_uses_waterfall = 1;
1188 bc->ar_loaded = 1;
1189 return 0;
1190 }
1191
1192 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
1193 const struct r600_bytecode_alu *alu, unsigned type)
1194 {
1195 struct r600_bytecode_alu *nalu = r600_bytecode_alu();
1196 struct r600_bytecode_alu *lalu;
1197 int i, r;
1198
1199 if (!nalu)
1200 return -ENOMEM;
1201 memcpy(nalu, alu, sizeof(struct r600_bytecode_alu));
1202
1203 if (alu->is_op3) {
1204 /* will fail later since alu does not support it. */
1205 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1206 }
1207
1208 if (bc->cf_last != NULL && bc->cf_last->op != type) {
1209 /* check if we could add it anyway */
1210 if (bc->cf_last->op == CF_OP_ALU &&
1211 type == CF_OP_ALU_PUSH_BEFORE) {
1212 LIST_FOR_EACH_ENTRY(lalu, &bc->cf_last->alu, list) {
1213 if (lalu->execute_mask) {
1214 bc->force_add_cf = 1;
1215 break;
1216 }
1217 }
1218 } else
1219 bc->force_add_cf = 1;
1220 }
1221
1222 /* cf can contains only alu or only vtx or only tex */
1223 if (bc->cf_last == NULL || bc->force_add_cf) {
1224 r = r600_bytecode_add_cf(bc);
1225 if (r) {
1226 free(nalu);
1227 return r;
1228 }
1229 }
1230 bc->cf_last->op = type;
1231
1232 /* Load index register if required */
1233 if (bc->chip_class >= EVERGREEN) {
1234 for (i = 0; i < 3; i++)
1235 if (nalu->src[i].kc_bank && nalu->src[i].kc_rel)
1236 egcm_load_index_reg(bc, 0, true);
1237 }
1238
1239 /* Check AR usage and load it if required */
1240 for (i = 0; i < 3; i++)
1241 if (nalu->src[i].rel && !bc->ar_loaded)
1242 load_ar(bc);
1243
1244 if (nalu->dst.rel && !bc->ar_loaded)
1245 load_ar(bc);
1246
1247 /* Setup the kcache for this ALU instruction. This will start a new
1248 * ALU clause if needed. */
1249 if ((r = r600_bytecode_alloc_kcache_lines(bc, nalu, type))) {
1250 free(nalu);
1251 return r;
1252 }
1253
1254 if (!bc->cf_last->curr_bs_head) {
1255 bc->cf_last->curr_bs_head = nalu;
1256 }
1257 /* number of gpr == the last gpr used in any alu */
1258 for (i = 0; i < 3; i++) {
1259 if (nalu->src[i].sel >= bc->ngpr && nalu->src[i].sel < 128) {
1260 bc->ngpr = nalu->src[i].sel + 1;
1261 }
1262 if (nalu->src[i].sel == V_SQ_ALU_SRC_LITERAL)
1263 r600_bytecode_special_constants(nalu->src[i].value,
1264 &nalu->src[i].sel, &nalu->src[i].neg, nalu->src[i].abs);
1265 }
1266 if (nalu->dst.sel >= bc->ngpr) {
1267 bc->ngpr = nalu->dst.sel + 1;
1268 }
1269 list_addtail(&nalu->list, &bc->cf_last->alu);
1270 /* each alu use 2 dwords */
1271 bc->cf_last->ndw += 2;
1272 bc->ndw += 2;
1273
1274 /* process cur ALU instructions for bank swizzle */
1275 if (nalu->last) {
1276 uint32_t literal[4];
1277 unsigned nliteral;
1278 struct r600_bytecode_alu *slots[5];
1279 int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
1280 r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
1281 if (r)
1282 return r;
1283
1284 if (bc->cf_last->prev_bs_head) {
1285 r = merge_inst_groups(bc, slots, bc->cf_last->prev_bs_head);
1286 if (r)
1287 return r;
1288 }
1289
1290 if (bc->cf_last->prev_bs_head) {
1291 r = replace_gpr_with_pv_ps(bc, slots, bc->cf_last->prev_bs_head);
1292 if (r)
1293 return r;
1294 }
1295
1296 r = check_and_set_bank_swizzle(bc, slots);
1297 if (r)
1298 return r;
1299
1300 for (i = 0, nliteral = 0; i < max_slots; i++) {
1301 if (slots[i]) {
1302 r = r600_bytecode_alu_nliterals(slots[i], literal, &nliteral);
1303 if (r)
1304 return r;
1305 }
1306 }
1307 bc->cf_last->ndw += align(nliteral, 2);
1308
1309 /* at most 128 slots, one add alu can add 5 slots + 4 constants(2 slots)
1310 * worst case */
1311 if ((bc->cf_last->ndw >> 1) >= 120) {
1312 bc->force_add_cf = 1;
1313 }
1314
1315 bc->cf_last->prev2_bs_head = bc->cf_last->prev_bs_head;
1316 bc->cf_last->prev_bs_head = bc->cf_last->curr_bs_head;
1317 bc->cf_last->curr_bs_head = NULL;
1318 }
1319
1320 if (nalu->dst.rel && bc->r6xx_nop_after_rel_dst)
1321 insert_nop_r6xx(bc);
1322
1323 /* Might need to insert spill write ops after current clause */
1324 if (nalu->last && bc->n_pending_outputs) {
1325 while (bc->n_pending_outputs) {
1326 r = r600_bytecode_add_output(bc, &bc->pending_outputs[--bc->n_pending_outputs]);
1327 if (r)
1328 return r;
1329 }
1330 }
1331
1332 return 0;
1333 }
1334
1335 int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu)
1336 {
1337 return r600_bytecode_add_alu_type(bc, alu, CF_OP_ALU);
1338 }
1339
1340 static unsigned r600_bytecode_num_tex_and_vtx_instructions(const struct r600_bytecode *bc)
1341 {
1342 switch (bc->chip_class) {
1343 case R600:
1344 return 8;
1345
1346 case R700:
1347 case EVERGREEN:
1348 case CAYMAN:
1349 return 16;
1350
1351 default:
1352 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1353 return 8;
1354 }
1355 }
1356
1357 static inline boolean last_inst_was_not_vtx_fetch(struct r600_bytecode *bc)
1358 {
1359 return !((r600_isa_cf(bc->cf_last->op)->flags & CF_FETCH) &&
1360 bc->cf_last->op != CF_OP_GDS &&
1361 (bc->chip_class == CAYMAN ||
1362 bc->cf_last->op != CF_OP_TEX));
1363 }
1364
1365 static int r600_bytecode_add_vtx_internal(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx,
1366 bool use_tc)
1367 {
1368 struct r600_bytecode_vtx *nvtx = r600_bytecode_vtx();
1369 int r;
1370
1371 if (!nvtx)
1372 return -ENOMEM;
1373 memcpy(nvtx, vtx, sizeof(struct r600_bytecode_vtx));
1374
1375 /* Load index register if required */
1376 if (bc->chip_class >= EVERGREEN) {
1377 if (vtx->buffer_index_mode)
1378 egcm_load_index_reg(bc, vtx->buffer_index_mode - 1, false);
1379 }
1380
1381 /* cf can contains only alu or only vtx or only tex */
1382 if (bc->cf_last == NULL ||
1383 last_inst_was_not_vtx_fetch(bc) ||
1384 bc->force_add_cf) {
1385 r = r600_bytecode_add_cf(bc);
1386 if (r) {
1387 free(nvtx);
1388 return r;
1389 }
1390 switch (bc->chip_class) {
1391 case R600:
1392 case R700:
1393 bc->cf_last->op = CF_OP_VTX;
1394 break;
1395 case EVERGREEN:
1396 if (use_tc)
1397 bc->cf_last->op = CF_OP_TEX;
1398 else
1399 bc->cf_last->op = CF_OP_VTX;
1400 break;
1401 case CAYMAN:
1402 bc->cf_last->op = CF_OP_TEX;
1403 break;
1404 default:
1405 R600_ERR("Unknown chip class %d.\n", bc->chip_class);
1406 free(nvtx);
1407 return -EINVAL;
1408 }
1409 }
1410 list_addtail(&nvtx->list, &bc->cf_last->vtx);
1411 /* each fetch use 4 dwords */
1412 bc->cf_last->ndw += 4;
1413 bc->ndw += 4;
1414 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1415 bc->force_add_cf = 1;
1416
1417 bc->ngpr = MAX2(bc->ngpr, vtx->src_gpr + 1);
1418 bc->ngpr = MAX2(bc->ngpr, vtx->dst_gpr + 1);
1419
1420 return 0;
1421 }
1422
1423 int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1424 {
1425 return r600_bytecode_add_vtx_internal(bc, vtx, false);
1426 }
1427
1428 int r600_bytecode_add_vtx_tc(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx)
1429 {
1430 return r600_bytecode_add_vtx_internal(bc, vtx, true);
1431 }
1432
1433 int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex)
1434 {
1435 struct r600_bytecode_tex *ntex = r600_bytecode_tex();
1436 int r;
1437
1438 if (!ntex)
1439 return -ENOMEM;
1440 memcpy(ntex, tex, sizeof(struct r600_bytecode_tex));
1441
1442 /* Load index register if required */
1443 if (bc->chip_class >= EVERGREEN) {
1444 if (tex->sampler_index_mode || tex->resource_index_mode)
1445 egcm_load_index_reg(bc, 1, false);
1446 }
1447
1448 /* we can't fetch data und use it as texture lookup address in the same TEX clause */
1449 if (bc->cf_last != NULL &&
1450 bc->cf_last->op == CF_OP_TEX) {
1451 struct r600_bytecode_tex *ttex;
1452 LIST_FOR_EACH_ENTRY(ttex, &bc->cf_last->tex, list) {
1453 if (ttex->dst_gpr == ntex->src_gpr &&
1454 (ttex->dst_sel_x < 4 || ttex->dst_sel_y < 4 ||
1455 ttex->dst_sel_z < 4 || ttex->dst_sel_w < 4)) {
1456 bc->force_add_cf = 1;
1457 break;
1458 }
1459 }
1460 /* slight hack to make gradients always go into same cf */
1461 if (ntex->op == FETCH_OP_SET_GRADIENTS_H)
1462 bc->force_add_cf = 1;
1463 }
1464
1465 /* cf can contains only alu or only vtx or only tex */
1466 if (bc->cf_last == NULL ||
1467 bc->cf_last->op != CF_OP_TEX ||
1468 bc->force_add_cf) {
1469 r = r600_bytecode_add_cf(bc);
1470 if (r) {
1471 free(ntex);
1472 return r;
1473 }
1474 bc->cf_last->op = CF_OP_TEX;
1475 }
1476 if (ntex->src_gpr >= bc->ngpr) {
1477 bc->ngpr = ntex->src_gpr + 1;
1478 }
1479 if (ntex->dst_gpr >= bc->ngpr) {
1480 bc->ngpr = ntex->dst_gpr + 1;
1481 }
1482 list_addtail(&ntex->list, &bc->cf_last->tex);
1483 /* each texture fetch use 4 dwords */
1484 bc->cf_last->ndw += 4;
1485 bc->ndw += 4;
1486 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1487 bc->force_add_cf = 1;
1488 return 0;
1489 }
1490
1491 int r600_bytecode_add_gds(struct r600_bytecode *bc, const struct r600_bytecode_gds *gds)
1492 {
1493 struct r600_bytecode_gds *ngds = r600_bytecode_gds();
1494 int r;
1495
1496 if (ngds == NULL)
1497 return -ENOMEM;
1498 memcpy(ngds, gds, sizeof(struct r600_bytecode_gds));
1499
1500 if (bc->chip_class >= EVERGREEN) {
1501 if (gds->uav_index_mode)
1502 egcm_load_index_reg(bc, gds->uav_index_mode - 1, false);
1503 }
1504
1505 if (bc->cf_last == NULL ||
1506 bc->cf_last->op != CF_OP_GDS ||
1507 bc->force_add_cf) {
1508 r = r600_bytecode_add_cf(bc);
1509 if (r) {
1510 free(ngds);
1511 return r;
1512 }
1513 bc->cf_last->op = CF_OP_GDS;
1514 }
1515
1516 list_addtail(&ngds->list, &bc->cf_last->gds);
1517 bc->cf_last->ndw += 4; /* each GDS uses 4 dwords */
1518 if ((bc->cf_last->ndw / 4) >= r600_bytecode_num_tex_and_vtx_instructions(bc))
1519 bc->force_add_cf = 1;
1520 return 0;
1521 }
1522
1523 int r600_bytecode_add_cfinst(struct r600_bytecode *bc, unsigned op)
1524 {
1525 int r;
1526
1527 /* Emit WAIT_ACK before control flow to ensure pending writes are always acked. */
1528 if (op != CF_OP_MEM_SCRATCH && bc->need_wait_ack) {
1529 bc->need_wait_ack = false;
1530 r = r600_bytecode_add_cfinst(bc, CF_OP_WAIT_ACK);
1531 }
1532
1533 r = r600_bytecode_add_cf(bc);
1534 if (r)
1535 return r;
1536
1537 bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
1538 bc->cf_last->op = op;
1539 return 0;
1540 }
1541
1542 int cm_bytecode_add_cf_end(struct r600_bytecode *bc)
1543 {
1544 return r600_bytecode_add_cfinst(bc, CF_OP_CF_END);
1545 }
1546
1547 /* common to all 3 families */
1548 static int r600_bytecode_vtx_build(struct r600_bytecode *bc, struct r600_bytecode_vtx *vtx, unsigned id)
1549 {
1550 if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
1551 return r700_bytecode_fetch_mem_build(bc, vtx, id);
1552 bc->bytecode[id] = S_SQ_VTX_WORD0_VTX_INST(r600_isa_fetch_opcode(bc->isa->hw_class, vtx->op)) |
1553 S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
1554 S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
1555 S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
1556 S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
1557 if (bc->chip_class < CAYMAN)
1558 bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
1559 id++;
1560 bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
1561 S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
1562 S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
1563 S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
1564 S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
1565 S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
1566 S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
1567 S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
1568 S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
1569 S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
1570 bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
1571 S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
1572 if (bc->chip_class >= EVERGREEN)
1573 bc->bytecode[id] |= ((vtx->buffer_index_mode & 0x3) << 21); // S_SQ_VTX_WORD2_BIM(vtx->buffer_index_mode);
1574 if (bc->chip_class < CAYMAN)
1575 bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
1576 id++;
1577 bc->bytecode[id++] = 0;
1578 return 0;
1579 }
1580
1581 /* common to all 3 families */
1582 static int r600_bytecode_tex_build(struct r600_bytecode *bc, struct r600_bytecode_tex *tex, unsigned id)
1583 {
1584 bc->bytecode[id] = S_SQ_TEX_WORD0_TEX_INST(
1585 r600_isa_fetch_opcode(bc->isa->hw_class, tex->op)) |
1586 EG_S_SQ_TEX_WORD0_INST_MOD(tex->inst_mod) |
1587 S_SQ_TEX_WORD0_RESOURCE_ID(tex->resource_id) |
1588 S_SQ_TEX_WORD0_SRC_GPR(tex->src_gpr) |
1589 S_SQ_TEX_WORD0_SRC_REL(tex->src_rel);
1590 if (bc->chip_class >= EVERGREEN)
1591 bc->bytecode[id] |= ((tex->sampler_index_mode & 0x3) << 27) | // S_SQ_TEX_WORD0_SIM(tex->sampler_index_mode);
1592 ((tex->resource_index_mode & 0x3) << 25); // S_SQ_TEX_WORD0_RIM(tex->resource_index_mode)
1593 id++;
1594 bc->bytecode[id++] = S_SQ_TEX_WORD1_DST_GPR(tex->dst_gpr) |
1595 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) |
1596 S_SQ_TEX_WORD1_DST_SEL_X(tex->dst_sel_x) |
1597 S_SQ_TEX_WORD1_DST_SEL_Y(tex->dst_sel_y) |
1598 S_SQ_TEX_WORD1_DST_SEL_Z(tex->dst_sel_z) |
1599 S_SQ_TEX_WORD1_DST_SEL_W(tex->dst_sel_w) |
1600 S_SQ_TEX_WORD1_LOD_BIAS(tex->lod_bias) |
1601 S_SQ_TEX_WORD1_COORD_TYPE_X(tex->coord_type_x) |
1602 S_SQ_TEX_WORD1_COORD_TYPE_Y(tex->coord_type_y) |
1603 S_SQ_TEX_WORD1_COORD_TYPE_Z(tex->coord_type_z) |
1604 S_SQ_TEX_WORD1_COORD_TYPE_W(tex->coord_type_w);
1605 bc->bytecode[id++] = S_SQ_TEX_WORD2_OFFSET_X(tex->offset_x) |
1606 S_SQ_TEX_WORD2_OFFSET_Y(tex->offset_y) |
1607 S_SQ_TEX_WORD2_OFFSET_Z(tex->offset_z) |
1608 S_SQ_TEX_WORD2_SAMPLER_ID(tex->sampler_id) |
1609 S_SQ_TEX_WORD2_SRC_SEL_X(tex->src_sel_x) |
1610 S_SQ_TEX_WORD2_SRC_SEL_Y(tex->src_sel_y) |
1611 S_SQ_TEX_WORD2_SRC_SEL_Z(tex->src_sel_z) |
1612 S_SQ_TEX_WORD2_SRC_SEL_W(tex->src_sel_w);
1613 bc->bytecode[id++] = 0;
1614 return 0;
1615 }
1616
1617 /* r600 only, r700/eg bits in r700_asm.c */
1618 static int r600_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id)
1619 {
1620 unsigned opcode = r600_isa_alu_opcode(bc->isa->hw_class, alu->op);
1621
1622 /* don't replace gpr by pv or ps for destination register */
1623 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
1624 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
1625 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
1626 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
1627 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
1628 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
1629 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
1630 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
1631 S_SQ_ALU_WORD0_INDEX_MODE(alu->index_mode) |
1632 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
1633 S_SQ_ALU_WORD0_LAST(alu->last);
1634
1635 if (alu->is_op3) {
1636 assert(!alu->src[0].abs && !alu->src[1].abs && !alu->src[2].abs);
1637 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1638 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1639 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1640 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1641 S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
1642 S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
1643 S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
1644 S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
1645 S_SQ_ALU_WORD1_OP3_ALU_INST(opcode) |
1646 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
1647 } else {
1648 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
1649 S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
1650 S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
1651 S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
1652 S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
1653 S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
1654 S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
1655 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
1656 S_SQ_ALU_WORD1_OP2_ALU_INST(opcode) |
1657 S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
1658 S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->execute_mask) |
1659 S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->update_pred);
1660 }
1661 return 0;
1662 }
1663
1664 static void r600_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf)
1665 {
1666 *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
1667 *bytecode++ = S_SQ_CF_WORD1_CF_INST(r600_isa_cf_opcode(ISA_CC_R600, cf->op)) |
1668 S_SQ_CF_WORD1_BARRIER(1) |
1669 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1)|
1670 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1671 }
1672
1673 /* common for r600/r700 - eg in eg_asm.c */
1674 static int r600_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
1675 {
1676 unsigned id = cf->id;
1677 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1678 unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
1679
1680
1681 if (cf->op == CF_NATIVE) {
1682 bc->bytecode[id++] = cf->isa[0];
1683 bc->bytecode[id++] = cf->isa[1];
1684 } else if (cfop->flags & CF_ALU) {
1685 bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
1686 S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
1687 S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
1688 S_SQ_CF_ALU_WORD0_KCACHE_BANK1(cf->kcache[1].bank);
1689
1690 bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(opcode) |
1691 S_SQ_CF_ALU_WORD1_KCACHE_MODE1(cf->kcache[1].mode) |
1692 S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
1693 S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
1694 S_SQ_CF_ALU_WORD1_BARRIER(1) |
1695 S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
1696 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
1697 } else if (cfop->flags & CF_FETCH) {
1698 if (bc->chip_class == R700)
1699 r700_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1700 else
1701 r600_bytecode_cf_vtx_build(&bc->bytecode[id], cf);
1702 } else if (cfop->flags & CF_EXP) {
1703 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1704 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1705 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1706 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1707 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1708 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1709 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(cf->output.swizzle_x) |
1710 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(cf->output.swizzle_y) |
1711 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(cf->output.swizzle_z) |
1712 S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
1713 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1714 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1715 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program);
1716 } else if (cfop->flags & CF_MEM) {
1717 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(cf->output.gpr) |
1718 S_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(cf->output.elem_size) |
1719 S_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(cf->output.array_base) |
1720 S_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(cf->output.type) |
1721 S_SQ_CF_ALLOC_EXPORT_WORD0_INDEX_GPR(cf->output.index_gpr);
1722 bc->bytecode[id++] = S_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(cf->output.burst_count - 1) |
1723 S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->barrier) |
1724 S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(opcode) |
1725 S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->end_of_program) |
1726 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(cf->output.array_size) |
1727 S_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(cf->output.comp_mask);
1728 } else {
1729 bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
1730 bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(opcode) |
1731 S_SQ_CF_WORD1_BARRIER(1) |
1732 S_SQ_CF_WORD1_COND(cf->cond) |
1733 S_SQ_CF_WORD1_POP_COUNT(cf->pop_count) |
1734 S_SQ_CF_WORD1_END_OF_PROGRAM(cf->end_of_program);
1735 }
1736 return 0;
1737 }
1738
1739 int r600_bytecode_build(struct r600_bytecode *bc)
1740 {
1741 struct r600_bytecode_cf *cf;
1742 struct r600_bytecode_alu *alu;
1743 struct r600_bytecode_vtx *vtx;
1744 struct r600_bytecode_tex *tex;
1745 struct r600_bytecode_gds *gds;
1746 uint32_t literal[4];
1747 unsigned nliteral;
1748 unsigned addr;
1749 int i, r;
1750
1751 if (!bc->nstack) { // If not 0, Stack_size already provided by llvm
1752 if (bc->stack.max_entries)
1753 bc->nstack = bc->stack.max_entries;
1754 else if (bc->type == PIPE_SHADER_VERTEX ||
1755 bc->type == PIPE_SHADER_TESS_EVAL ||
1756 bc->type == PIPE_SHADER_TESS_CTRL)
1757 bc->nstack = 1;
1758 }
1759
1760 /* first path compute addr of each CF block */
1761 /* addr start after all the CF instructions */
1762 addr = bc->cf_last->id + 2;
1763 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1764 if (r600_isa_cf(cf->op)->flags & CF_FETCH) {
1765 addr += 3;
1766 addr &= 0xFFFFFFFCUL;
1767 }
1768 cf->addr = addr;
1769 addr += cf->ndw;
1770 bc->ndw = cf->addr + cf->ndw;
1771 }
1772 free(bc->bytecode);
1773 bc->bytecode = calloc(4, bc->ndw);
1774 if (bc->bytecode == NULL)
1775 return -ENOMEM;
1776 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
1777 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
1778 addr = cf->addr;
1779 if (bc->chip_class >= EVERGREEN)
1780 r = eg_bytecode_cf_build(bc, cf);
1781 else
1782 r = r600_bytecode_cf_build(bc, cf);
1783 if (r)
1784 return r;
1785 if (cfop->flags & CF_ALU) {
1786 nliteral = 0;
1787 memset(literal, 0, sizeof(literal));
1788 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
1789 r = r600_bytecode_alu_nliterals(alu, literal, &nliteral);
1790 if (r)
1791 return r;
1792 r600_bytecode_alu_adjust_literals(alu, literal, nliteral);
1793 r600_bytecode_assign_kcache_banks(alu, cf->kcache);
1794
1795 switch(bc->chip_class) {
1796 case R600:
1797 r = r600_bytecode_alu_build(bc, alu, addr);
1798 break;
1799 case R700:
1800 r = r700_bytecode_alu_build(bc, alu, addr);
1801 break;
1802 case EVERGREEN:
1803 case CAYMAN:
1804 r = eg_bytecode_alu_build(bc, alu, addr);
1805 break;
1806 default:
1807 R600_ERR("unknown chip class %d.\n", bc->chip_class);
1808 return -EINVAL;
1809 }
1810 if (r)
1811 return r;
1812 addr += 2;
1813 if (alu->last) {
1814 for (i = 0; i < align(nliteral, 2); ++i) {
1815 bc->bytecode[addr++] = literal[i];
1816 }
1817 nliteral = 0;
1818 memset(literal, 0, sizeof(literal));
1819 }
1820 }
1821 } else if (cf->op == CF_OP_VTX) {
1822 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1823 r = r600_bytecode_vtx_build(bc, vtx, addr);
1824 if (r)
1825 return r;
1826 addr += 4;
1827 }
1828 } else if (cf->op == CF_OP_GDS) {
1829 assert(bc->chip_class >= EVERGREEN);
1830 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
1831 r = eg_bytecode_gds_build(bc, gds, addr);
1832 if (r)
1833 return r;
1834 addr += 4;
1835 }
1836 } else if (cf->op == CF_OP_TEX) {
1837 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
1838 assert(bc->chip_class >= EVERGREEN);
1839 r = r600_bytecode_vtx_build(bc, vtx, addr);
1840 if (r)
1841 return r;
1842 addr += 4;
1843 }
1844 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
1845 r = r600_bytecode_tex_build(bc, tex, addr);
1846 if (r)
1847 return r;
1848 addr += 4;
1849 }
1850 }
1851 }
1852 return 0;
1853 }
1854
1855 void r600_bytecode_clear(struct r600_bytecode *bc)
1856 {
1857 struct r600_bytecode_cf *cf = NULL, *next_cf;
1858
1859 free(bc->bytecode);
1860 bc->bytecode = NULL;
1861
1862 LIST_FOR_EACH_ENTRY_SAFE(cf, next_cf, &bc->cf, list) {
1863 struct r600_bytecode_alu *alu = NULL, *next_alu;
1864 struct r600_bytecode_tex *tex = NULL, *next_tex;
1865 struct r600_bytecode_tex *vtx = NULL, *next_vtx;
1866 struct r600_bytecode_gds *gds = NULL, *next_gds;
1867
1868 LIST_FOR_EACH_ENTRY_SAFE(alu, next_alu, &cf->alu, list) {
1869 free(alu);
1870 }
1871
1872 list_inithead(&cf->alu);
1873
1874 LIST_FOR_EACH_ENTRY_SAFE(tex, next_tex, &cf->tex, list) {
1875 free(tex);
1876 }
1877
1878 list_inithead(&cf->tex);
1879
1880 LIST_FOR_EACH_ENTRY_SAFE(vtx, next_vtx, &cf->vtx, list) {
1881 free(vtx);
1882 }
1883
1884 list_inithead(&cf->vtx);
1885
1886 LIST_FOR_EACH_ENTRY_SAFE(gds, next_gds, &cf->gds, list) {
1887 free(gds);
1888 }
1889
1890 list_inithead(&cf->gds);
1891
1892 free(cf);
1893 }
1894
1895 list_inithead(&cf->list);
1896 }
1897
1898 static int print_swizzle(unsigned swz)
1899 {
1900 const char * swzchars = "xyzw01?_";
1901 assert(swz<8 && swz != 6);
1902 return fprintf(stderr, "%c", swzchars[swz]);
1903 }
1904
1905 static int print_sel(unsigned sel, unsigned rel, unsigned index_mode,
1906 unsigned need_brackets)
1907 {
1908 int o = 0;
1909 if (rel && index_mode >= 5 && sel < 128)
1910 o += fprintf(stderr, "G");
1911 if (rel || need_brackets) {
1912 o += fprintf(stderr, "[");
1913 }
1914 o += fprintf(stderr, "%d", sel);
1915 if (rel) {
1916 if (index_mode == 0 || index_mode == 6)
1917 o += fprintf(stderr, "+AR");
1918 else if (index_mode == 4)
1919 o += fprintf(stderr, "+AL");
1920 }
1921 if (rel || need_brackets) {
1922 o += fprintf(stderr, "]");
1923 }
1924 return o;
1925 }
1926
1927 static int print_dst(struct r600_bytecode_alu *alu)
1928 {
1929 int o = 0;
1930 unsigned sel = alu->dst.sel;
1931 char reg_char = 'R';
1932 if (sel > 128 - 4) { /* clause temporary gpr */
1933 sel -= 128 - 4;
1934 reg_char = 'T';
1935 }
1936
1937 if (alu_writes(alu)) {
1938 o += fprintf(stderr, "%c", reg_char);
1939 o += print_sel(alu->dst.sel, alu->dst.rel, alu->index_mode, 0);
1940 } else {
1941 o += fprintf(stderr, "__");
1942 }
1943 o += fprintf(stderr, ".");
1944 o += print_swizzle(alu->dst.chan);
1945 return o;
1946 }
1947
1948 static int print_src(struct r600_bytecode_alu *alu, unsigned idx)
1949 {
1950 int o = 0;
1951 struct r600_bytecode_alu_src *src = &alu->src[idx];
1952 unsigned sel = src->sel, need_sel = 1, need_chan = 1, need_brackets = 0;
1953
1954 if (src->neg)
1955 o += fprintf(stderr,"-");
1956 if (src->abs)
1957 o += fprintf(stderr,"|");
1958
1959 if (sel < 128 - 4) {
1960 o += fprintf(stderr, "R");
1961 } else if (sel < 128) {
1962 o += fprintf(stderr, "T");
1963 sel -= 128 - 4;
1964 } else if (sel < 160) {
1965 o += fprintf(stderr, "KC0");
1966 need_brackets = 1;
1967 sel -= 128;
1968 } else if (sel < 192) {
1969 o += fprintf(stderr, "KC1");
1970 need_brackets = 1;
1971 sel -= 160;
1972 } else if (sel >= 512) {
1973 o += fprintf(stderr, "C%d", src->kc_bank);
1974 need_brackets = 1;
1975 sel -= 512;
1976 } else if (sel >= 448) {
1977 o += fprintf(stderr, "Param");
1978 sel -= 448;
1979 need_chan = 0;
1980 } else if (sel >= 288) {
1981 o += fprintf(stderr, "KC3");
1982 need_brackets = 1;
1983 sel -= 288;
1984 } else if (sel >= 256) {
1985 o += fprintf(stderr, "KC2");
1986 need_brackets = 1;
1987 sel -= 256;
1988 } else {
1989 need_sel = 0;
1990 need_chan = 0;
1991 switch (sel) {
1992 case EG_V_SQ_ALU_SRC_LDS_DIRECT_A:
1993 o += fprintf(stderr, "LDS_A[0x%08X]", src->value);
1994 break;
1995 case EG_V_SQ_ALU_SRC_LDS_DIRECT_B:
1996 o += fprintf(stderr, "LDS_B[0x%08X]", src->value);
1997 break;
1998 case EG_V_SQ_ALU_SRC_LDS_OQ_A:
1999 o += fprintf(stderr, "LDS_OQ_A");
2000 need_chan = 1;
2001 break;
2002 case EG_V_SQ_ALU_SRC_LDS_OQ_B:
2003 o += fprintf(stderr, "LDS_OQ_B");
2004 need_chan = 1;
2005 break;
2006 case EG_V_SQ_ALU_SRC_LDS_OQ_A_POP:
2007 o += fprintf(stderr, "LDS_OQ_A_POP");
2008 need_chan = 1;
2009 break;
2010 case EG_V_SQ_ALU_SRC_LDS_OQ_B_POP:
2011 o += fprintf(stderr, "LDS_OQ_B_POP");
2012 need_chan = 1;
2013 break;
2014 case EG_V_SQ_ALU_SRC_TIME_LO:
2015 o += fprintf(stderr, "TIME_LO");
2016 break;
2017 case EG_V_SQ_ALU_SRC_TIME_HI:
2018 o += fprintf(stderr, "TIME_HI");
2019 break;
2020 case EG_V_SQ_ALU_SRC_SE_ID:
2021 o += fprintf(stderr, "SE_ID");
2022 break;
2023 case EG_V_SQ_ALU_SRC_SIMD_ID:
2024 o += fprintf(stderr, "SIMD_ID");
2025 break;
2026 case EG_V_SQ_ALU_SRC_HW_WAVE_ID:
2027 o += fprintf(stderr, "HW_WAVE_ID");
2028 break;
2029 case V_SQ_ALU_SRC_PS:
2030 o += fprintf(stderr, "PS");
2031 break;
2032 case V_SQ_ALU_SRC_PV:
2033 o += fprintf(stderr, "PV");
2034 need_chan = 1;
2035 break;
2036 case V_SQ_ALU_SRC_LITERAL:
2037 o += fprintf(stderr, "[0x%08X %f]", src->value, u_bitcast_u2f(src->value));
2038 break;
2039 case V_SQ_ALU_SRC_0_5:
2040 o += fprintf(stderr, "0.5");
2041 break;
2042 case V_SQ_ALU_SRC_M_1_INT:
2043 o += fprintf(stderr, "-1");
2044 break;
2045 case V_SQ_ALU_SRC_1_INT:
2046 o += fprintf(stderr, "1");
2047 break;
2048 case V_SQ_ALU_SRC_1:
2049 o += fprintf(stderr, "1.0");
2050 break;
2051 case V_SQ_ALU_SRC_0:
2052 o += fprintf(stderr, "0");
2053 break;
2054 default:
2055 o += fprintf(stderr, "??IMM_%d", sel);
2056 break;
2057 }
2058 }
2059
2060 if (need_sel)
2061 o += print_sel(sel, src->rel, alu->index_mode, need_brackets);
2062
2063 if (need_chan) {
2064 o += fprintf(stderr, ".");
2065 o += print_swizzle(src->chan);
2066 }
2067
2068 if (src->abs)
2069 o += fprintf(stderr,"|");
2070
2071 return o;
2072 }
2073
2074 static int print_indent(int p, int c)
2075 {
2076 int o = 0;
2077 while (p++ < c)
2078 o += fprintf(stderr, " ");
2079 return o;
2080 }
2081
2082 void r600_bytecode_disasm(struct r600_bytecode *bc)
2083 {
2084 const char *index_mode[] = {"CF_INDEX_NONE", "CF_INDEX_0", "CF_INDEX_1"};
2085 static int index = 0;
2086 struct r600_bytecode_cf *cf = NULL;
2087 struct r600_bytecode_alu *alu = NULL;
2088 struct r600_bytecode_vtx *vtx = NULL;
2089 struct r600_bytecode_tex *tex = NULL;
2090 struct r600_bytecode_gds *gds = NULL;
2091
2092 unsigned i, id, ngr = 0, last;
2093 uint32_t literal[4];
2094 unsigned nliteral;
2095 char chip = '6';
2096
2097 switch (bc->chip_class) {
2098 case R700:
2099 chip = '7';
2100 break;
2101 case EVERGREEN:
2102 chip = 'E';
2103 break;
2104 case CAYMAN:
2105 chip = 'C';
2106 break;
2107 case R600:
2108 default:
2109 chip = '6';
2110 break;
2111 }
2112 fprintf(stderr, "bytecode %d dw -- %d gprs -- %d nstack -------------\n",
2113 bc->ndw, bc->ngpr, bc->nstack);
2114 fprintf(stderr, "shader %d -- %c\n", index++, chip);
2115
2116 LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
2117 id = cf->id;
2118 if (cf->op == CF_NATIVE) {
2119 fprintf(stderr, "%04d %08X %08X CF_NATIVE\n", id, bc->bytecode[id],
2120 bc->bytecode[id + 1]);
2121 } else {
2122 const struct cf_op_info *cfop = r600_isa_cf(cf->op);
2123 if (cfop->flags & CF_ALU) {
2124 if (cf->eg_alu_extended) {
2125 fprintf(stderr, "%04d %08X %08X %s\n", id, bc->bytecode[id],
2126 bc->bytecode[id + 1], "ALU_EXT");
2127 id += 2;
2128 }
2129 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2130 bc->bytecode[id + 1], cfop->name);
2131 fprintf(stderr, "%d @%d ", cf->ndw / 2, cf->addr);
2132 for (i = 0; i < 4; ++i) {
2133 if (cf->kcache[i].mode) {
2134 int c_start = (cf->kcache[i].addr << 4);
2135 int c_end = c_start + (cf->kcache[i].mode << 4);
2136 fprintf(stderr, "KC%d[CB%d:%d-%d%s%s] ",
2137 i, cf->kcache[i].bank, c_start, c_end,
2138 cf->kcache[i].index_mode ? " " : "",
2139 cf->kcache[i].index_mode ? index_mode[cf->kcache[i].index_mode] : "");
2140 }
2141 }
2142 fprintf(stderr, "\n");
2143 } else if (cfop->flags & CF_FETCH) {
2144 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2145 bc->bytecode[id + 1], cfop->name);
2146 fprintf(stderr, "%d @%d ", cf->ndw / 4, cf->addr);
2147 if (cf->vpm)
2148 fprintf(stderr, "VPM ");
2149 if (cf->end_of_program)
2150 fprintf(stderr, "EOP ");
2151 fprintf(stderr, "\n");
2152
2153 } else if (cfop->flags & CF_EXP) {
2154 int o = 0;
2155 const char *exp_type[] = {"PIXEL", "POS ", "PARAM"};
2156 o += fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2157 bc->bytecode[id + 1], cfop->name);
2158 o += print_indent(o, 43);
2159 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2160 if (cf->output.burst_count > 1) {
2161 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2162 cf->output.array_base + cf->output.burst_count - 1);
2163
2164 o += print_indent(o, 55);
2165 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2166 cf->output.gpr + cf->output.burst_count - 1);
2167 } else {
2168 o += fprintf(stderr, "%d ", cf->output.array_base);
2169 o += print_indent(o, 55);
2170 o += fprintf(stderr, "R%d.", cf->output.gpr);
2171 }
2172
2173 o += print_swizzle(cf->output.swizzle_x);
2174 o += print_swizzle(cf->output.swizzle_y);
2175 o += print_swizzle(cf->output.swizzle_z);
2176 o += print_swizzle(cf->output.swizzle_w);
2177
2178 print_indent(o, 67);
2179
2180 fprintf(stderr, " ES:%X ", cf->output.elem_size);
2181 if (cf->mark)
2182 fprintf(stderr, "MARK ");
2183 if (!cf->barrier)
2184 fprintf(stderr, "NO_BARRIER ");
2185 if (cf->end_of_program)
2186 fprintf(stderr, "EOP ");
2187 fprintf(stderr, "\n");
2188 } else if (r600_isa_cf(cf->op)->flags & CF_MEM) {
2189 int o = 0;
2190 const char *exp_type[] = {"WRITE", "WRITE_IND", "WRITE_ACK",
2191 "WRITE_IND_ACK"};
2192 o += fprintf(stderr, "%04d %08X %08X %s ", id,
2193 bc->bytecode[id], bc->bytecode[id + 1], cfop->name);
2194 o += print_indent(o, 43);
2195 o += fprintf(stderr, "%s ", exp_type[cf->output.type]);
2196
2197 if (r600_isa_cf(cf->op)->flags & CF_RAT) {
2198 o += fprintf(stderr, "RAT%d", cf->rat.id);
2199 if (cf->rat.index_mode) {
2200 o += fprintf(stderr, "[IDX%d]", cf->rat.index_mode - 1);
2201 }
2202 o += fprintf(stderr, " INST: %d ", cf->rat.inst);
2203 }
2204
2205 if (cf->output.burst_count > 1) {
2206 o += fprintf(stderr, "%d-%d ", cf->output.array_base,
2207 cf->output.array_base + cf->output.burst_count - 1);
2208 o += print_indent(o, 55);
2209 o += fprintf(stderr, "R%d-%d.", cf->output.gpr,
2210 cf->output.gpr + cf->output.burst_count - 1);
2211 } else {
2212 o += fprintf(stderr, "%d ", cf->output.array_base);
2213 o += print_indent(o, 55);
2214 o += fprintf(stderr, "R%d.", cf->output.gpr);
2215 }
2216 for (i = 0; i < 4; ++i) {
2217 if (cf->output.comp_mask & (1 << i))
2218 o += print_swizzle(i);
2219 else
2220 o += print_swizzle(7);
2221 }
2222
2223 if (cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_WRITE_IND ||
2224 cf->output.type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_READ_IND)
2225 o += fprintf(stderr, " R%d", cf->output.index_gpr);
2226
2227 o += print_indent(o, 67);
2228
2229 fprintf(stderr, " ES:%i ", cf->output.elem_size);
2230 if (cf->output.array_size != 0xFFF)
2231 fprintf(stderr, "AS:%i ", cf->output.array_size);
2232 if (cf->mark)
2233 fprintf(stderr, "MARK ");
2234 if (!cf->barrier)
2235 fprintf(stderr, "NO_BARRIER ");
2236 if (cf->end_of_program)
2237 fprintf(stderr, "EOP ");
2238
2239 if (cf->output.mark)
2240 fprintf(stderr, "MARK ");
2241
2242 fprintf(stderr, "\n");
2243 } else {
2244 fprintf(stderr, "%04d %08X %08X %s ", id, bc->bytecode[id],
2245 bc->bytecode[id + 1], cfop->name);
2246 fprintf(stderr, "@%d ", cf->cf_addr);
2247 if (cf->cond)
2248 fprintf(stderr, "CND:%X ", cf->cond);
2249 if (cf->pop_count)
2250 fprintf(stderr, "POP:%X ", cf->pop_count);
2251 if (cf->count && (cfop->flags & CF_EMIT))
2252 fprintf(stderr, "STREAM%d ", cf->count);
2253 if (cf->vpm)
2254 fprintf(stderr, "VPM ");
2255 if (cf->end_of_program)
2256 fprintf(stderr, "EOP ");
2257 fprintf(stderr, "\n");
2258 }
2259 }
2260
2261 id = cf->addr;
2262 nliteral = 0;
2263 last = 1;
2264 LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
2265 const char *omod_str[] = {"","*2","*4","/2"};
2266 const struct alu_op_info *aop = r600_isa_alu(alu->op);
2267 int o = 0;
2268
2269 r600_bytecode_alu_nliterals(alu, literal, &nliteral);
2270 o += fprintf(stderr, " %04d %08X %08X ", id, bc->bytecode[id], bc->bytecode[id+1]);
2271 if (last)
2272 o += fprintf(stderr, "%4d ", ++ngr);
2273 else
2274 o += fprintf(stderr, " ");
2275 o += fprintf(stderr, "%c%c %c ", alu->execute_mask ? 'M':' ',
2276 alu->update_pred ? 'P':' ',
2277 alu->pred_sel ? alu->pred_sel==2 ? '0':'1':' ');
2278
2279 o += fprintf(stderr, "%s%s%s ", aop->name,
2280 omod_str[alu->omod], alu->dst.clamp ? "_sat":"");
2281
2282 o += print_indent(o,60);
2283 o += print_dst(alu);
2284 for (i = 0; i < aop->src_count; ++i) {
2285 o += fprintf(stderr, i == 0 ? ", ": ", ");
2286 o += print_src(alu, i);
2287 }
2288
2289 if (alu->bank_swizzle) {
2290 o += print_indent(o,75);
2291 o += fprintf(stderr, " BS:%d", alu->bank_swizzle);
2292 }
2293
2294 fprintf(stderr, "\n");
2295 id += 2;
2296
2297 if (alu->last) {
2298 for (i = 0; i < nliteral; i++, id++) {
2299 float *f = (float*)(bc->bytecode + id);
2300 o = fprintf(stderr, " %04d %08X", id, bc->bytecode[id]);
2301 print_indent(o, 60);
2302 fprintf(stderr, " %f (%d)\n", *f, *(bc->bytecode + id));
2303 }
2304 id += nliteral & 1;
2305 nliteral = 0;
2306 }
2307 last = alu->last;
2308 }
2309
2310 LIST_FOR_EACH_ENTRY(tex, &cf->tex, list) {
2311 int o = 0;
2312 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2313 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2314
2315 o += fprintf(stderr, "%s ", r600_isa_fetch(tex->op)->name);
2316
2317 o += print_indent(o, 50);
2318
2319 o += fprintf(stderr, "R%d.", tex->dst_gpr);
2320 o += print_swizzle(tex->dst_sel_x);
2321 o += print_swizzle(tex->dst_sel_y);
2322 o += print_swizzle(tex->dst_sel_z);
2323 o += print_swizzle(tex->dst_sel_w);
2324
2325 o += fprintf(stderr, ", R%d.", tex->src_gpr);
2326 o += print_swizzle(tex->src_sel_x);
2327 o += print_swizzle(tex->src_sel_y);
2328 o += print_swizzle(tex->src_sel_z);
2329 o += print_swizzle(tex->src_sel_w);
2330
2331 o += fprintf(stderr, ", RID:%d", tex->resource_id);
2332 o += fprintf(stderr, ", SID:%d ", tex->sampler_id);
2333
2334 if (tex->sampler_index_mode)
2335 fprintf(stderr, "SQ_%s ", index_mode[tex->sampler_index_mode]);
2336
2337 if (tex->lod_bias)
2338 fprintf(stderr, "LB:%d ", tex->lod_bias);
2339
2340 fprintf(stderr, "CT:%c%c%c%c ",
2341 tex->coord_type_x ? 'N' : 'U',
2342 tex->coord_type_y ? 'N' : 'U',
2343 tex->coord_type_z ? 'N' : 'U',
2344 tex->coord_type_w ? 'N' : 'U');
2345
2346 if (tex->offset_x)
2347 fprintf(stderr, "OX:%d ", tex->offset_x);
2348 if (tex->offset_y)
2349 fprintf(stderr, "OY:%d ", tex->offset_y);
2350 if (tex->offset_z)
2351 fprintf(stderr, "OZ:%d ", tex->offset_z);
2352
2353 id += 4;
2354 fprintf(stderr, "\n");
2355 }
2356
2357 LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
2358 int o = 0;
2359 const char * fetch_type[] = {"VERTEX", "INSTANCE", ""};
2360 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2361 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2362
2363 o += fprintf(stderr, "%s ", r600_isa_fetch(vtx->op)->name);
2364
2365 o += print_indent(o, 50);
2366
2367 o += fprintf(stderr, "R%d.", vtx->dst_gpr);
2368 o += print_swizzle(vtx->dst_sel_x);
2369 o += print_swizzle(vtx->dst_sel_y);
2370 o += print_swizzle(vtx->dst_sel_z);
2371 o += print_swizzle(vtx->dst_sel_w);
2372
2373 o += fprintf(stderr, ", R%d.", vtx->src_gpr);
2374 o += print_swizzle(vtx->src_sel_x);
2375 if (r600_isa_fetch(vtx->op)->flags & FF_MEM)
2376 o += print_swizzle(vtx->src_sel_y);
2377
2378 if (vtx->offset)
2379 fprintf(stderr, " +%db", vtx->offset);
2380
2381 o += print_indent(o, 55);
2382
2383 fprintf(stderr, ", RID:%d ", vtx->buffer_id);
2384
2385 fprintf(stderr, "%s ", fetch_type[vtx->fetch_type]);
2386
2387 if (bc->chip_class < CAYMAN && vtx->mega_fetch_count)
2388 fprintf(stderr, "MFC:%d ", vtx->mega_fetch_count);
2389
2390 if (bc->chip_class >= EVERGREEN && vtx->buffer_index_mode)
2391 fprintf(stderr, "SQ_%s ", index_mode[vtx->buffer_index_mode]);
2392
2393 if (r600_isa_fetch(vtx->op)->flags & FF_MEM) {
2394 if (vtx->uncached)
2395 fprintf(stderr, "UNCACHED ");
2396 if (vtx->indexed)
2397 fprintf(stderr, "INDEXED:%d ", vtx->indexed);
2398
2399 fprintf(stderr, "ELEM_SIZE:%d ", vtx->elem_size);
2400 if (vtx->burst_count)
2401 fprintf(stderr, "BURST_COUNT:%d ", vtx->burst_count);
2402 fprintf(stderr, "ARRAY_BASE:%d ", vtx->array_base);
2403 fprintf(stderr, "ARRAY_SIZE:%d ", vtx->array_size);
2404 }
2405
2406 fprintf(stderr, "UCF:%d ", vtx->use_const_fields);
2407 fprintf(stderr, "FMT(DTA:%d ", vtx->data_format);
2408 fprintf(stderr, "NUM:%d ", vtx->num_format_all);
2409 fprintf(stderr, "COMP:%d ", vtx->format_comp_all);
2410 fprintf(stderr, "MODE:%d)\n", vtx->srf_mode_all);
2411
2412 id += 4;
2413 }
2414
2415 LIST_FOR_EACH_ENTRY(gds, &cf->gds, list) {
2416 int o = 0;
2417 o += fprintf(stderr, " %04d %08X %08X %08X ", id, bc->bytecode[id],
2418 bc->bytecode[id + 1], bc->bytecode[id + 2]);
2419
2420 o += fprintf(stderr, "%s ", r600_isa_fetch(gds->op)->name);
2421
2422 if (gds->op != FETCH_OP_TF_WRITE) {
2423 o += fprintf(stderr, "R%d.", gds->dst_gpr);
2424 o += print_swizzle(gds->dst_sel_x);
2425 o += print_swizzle(gds->dst_sel_y);
2426 o += print_swizzle(gds->dst_sel_z);
2427 o += print_swizzle(gds->dst_sel_w);
2428 }
2429
2430 o += fprintf(stderr, ", R%d.", gds->src_gpr);
2431 o += print_swizzle(gds->src_sel_x);
2432 o += print_swizzle(gds->src_sel_y);
2433 o += print_swizzle(gds->src_sel_z);
2434
2435 if (gds->op != FETCH_OP_TF_WRITE) {
2436 o += fprintf(stderr, ", R%d.", gds->src_gpr2);
2437 }
2438 if (gds->alloc_consume) {
2439 o += fprintf(stderr, " UAV: %d", gds->uav_id);
2440 if (gds->uav_index_mode)
2441 o += fprintf(stderr, "[%s]", index_mode[gds->uav_index_mode]);
2442 }
2443 fprintf(stderr, "\n");
2444 id += 4;
2445 }
2446 }
2447
2448 fprintf(stderr, "--------------------------------------\n");
2449 }
2450
2451 void r600_vertex_data_type(enum pipe_format pformat,
2452 unsigned *format,
2453 unsigned *num_format, unsigned *format_comp, unsigned *endian)
2454 {
2455 const struct util_format_description *desc;
2456 unsigned i;
2457
2458 *format = 0;
2459 *num_format = 0;
2460 *format_comp = 0;
2461 *endian = ENDIAN_NONE;
2462
2463 if (pformat == PIPE_FORMAT_R11G11B10_FLOAT) {
2464 *format = FMT_10_11_11_FLOAT;
2465 *endian = r600_endian_swap(32);
2466 return;
2467 }
2468
2469 if (pformat == PIPE_FORMAT_B5G6R5_UNORM) {
2470 *format = FMT_5_6_5;
2471 *endian = r600_endian_swap(16);
2472 return;
2473 }
2474
2475 if (pformat == PIPE_FORMAT_B5G5R5A1_UNORM) {
2476 *format = FMT_1_5_5_5;
2477 *endian = r600_endian_swap(16);
2478 return;
2479 }
2480
2481 if (pformat == PIPE_FORMAT_A1B5G5R5_UNORM) {
2482 *format = FMT_5_5_5_1;
2483 return;
2484 }
2485
2486 desc = util_format_description(pformat);
2487 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
2488 goto out_unknown;
2489 }
2490
2491 /* Find the first non-VOID channel. */
2492 for (i = 0; i < 4; i++) {
2493 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2494 break;
2495 }
2496 }
2497
2498 *endian = r600_endian_swap(desc->channel[i].size);
2499
2500 switch (desc->channel[i].type) {
2501 /* Half-floats, floats, ints */
2502 case UTIL_FORMAT_TYPE_FLOAT:
2503 switch (desc->channel[i].size) {
2504 case 16:
2505 switch (desc->nr_channels) {
2506 case 1:
2507 *format = FMT_16_FLOAT;
2508 break;
2509 case 2:
2510 *format = FMT_16_16_FLOAT;
2511 break;
2512 case 3:
2513 case 4:
2514 *format = FMT_16_16_16_16_FLOAT;
2515 break;
2516 }
2517 break;
2518 case 32:
2519 switch (desc->nr_channels) {
2520 case 1:
2521 *format = FMT_32_FLOAT;
2522 break;
2523 case 2:
2524 *format = FMT_32_32_FLOAT;
2525 break;
2526 case 3:
2527 *format = FMT_32_32_32_FLOAT;
2528 break;
2529 case 4:
2530 *format = FMT_32_32_32_32_FLOAT;
2531 break;
2532 }
2533 break;
2534 default:
2535 goto out_unknown;
2536 }
2537 break;
2538 /* Unsigned ints */
2539 case UTIL_FORMAT_TYPE_UNSIGNED:
2540 /* Signed ints */
2541 case UTIL_FORMAT_TYPE_SIGNED:
2542 switch (desc->channel[i].size) {
2543 case 4:
2544 switch (desc->nr_channels) {
2545 case 2:
2546 *format = FMT_4_4;
2547 break;
2548 case 4:
2549 *format = FMT_4_4_4_4;
2550 break;
2551 }
2552 break;
2553 case 8:
2554 switch (desc->nr_channels) {
2555 case 1:
2556 *format = FMT_8;
2557 break;
2558 case 2:
2559 *format = FMT_8_8;
2560 break;
2561 case 3:
2562 case 4:
2563 *format = FMT_8_8_8_8;
2564 break;
2565 }
2566 break;
2567 case 10:
2568 if (desc->nr_channels != 4)
2569 goto out_unknown;
2570
2571 *format = FMT_2_10_10_10;
2572 break;
2573 case 16:
2574 switch (desc->nr_channels) {
2575 case 1:
2576 *format = FMT_16;
2577 break;
2578 case 2:
2579 *format = FMT_16_16;
2580 break;
2581 case 3:
2582 case 4:
2583 *format = FMT_16_16_16_16;
2584 break;
2585 }
2586 break;
2587 case 32:
2588 switch (desc->nr_channels) {
2589 case 1:
2590 *format = FMT_32;
2591 break;
2592 case 2:
2593 *format = FMT_32_32;
2594 break;
2595 case 3:
2596 *format = FMT_32_32_32;
2597 break;
2598 case 4:
2599 *format = FMT_32_32_32_32;
2600 break;
2601 }
2602 break;
2603 default:
2604 goto out_unknown;
2605 }
2606 break;
2607 default:
2608 goto out_unknown;
2609 }
2610
2611 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2612 *format_comp = 1;
2613 }
2614
2615 *num_format = 0;
2616 if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2617 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2618 if (!desc->channel[i].normalized) {
2619 if (desc->channel[i].pure_integer)
2620 *num_format = 1;
2621 else
2622 *num_format = 2;
2623 }
2624 }
2625 return;
2626 out_unknown:
2627 R600_ERR("unsupported vertex format %s\n", util_format_name(pformat));
2628 }
2629
2630 void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,
2631 unsigned count,
2632 const struct pipe_vertex_element *elements)
2633 {
2634 struct r600_context *rctx = (struct r600_context *)ctx;
2635 struct r600_bytecode bc;
2636 struct r600_bytecode_vtx vtx;
2637 const struct util_format_description *desc;
2638 unsigned fetch_resource_start = rctx->b.chip_class >= EVERGREEN ? 0 : 160;
2639 unsigned format, num_format, format_comp, endian;
2640 uint32_t *bytecode;
2641 int i, j, r, fs_size;
2642 struct r600_fetch_shader *shader;
2643 unsigned no_sb = rctx->screen->b.debug_flags & DBG_NO_SB;
2644 unsigned sb_disasm = !no_sb || (rctx->screen->b.debug_flags & DBG_SB_DISASM);
2645
2646 assert(count < 32);
2647
2648 memset(&bc, 0, sizeof(bc));
2649 r600_bytecode_init(&bc, rctx->b.chip_class, rctx->b.family,
2650 rctx->screen->has_compressed_msaa_texturing);
2651
2652 bc.isa = rctx->isa;
2653
2654 for (i = 0; i < count; i++) {
2655 if (elements[i].instance_divisor > 1) {
2656 if (rctx->b.chip_class == CAYMAN) {
2657 for (j = 0; j < 4; j++) {
2658 struct r600_bytecode_alu alu;
2659 memset(&alu, 0, sizeof(alu));
2660 alu.op = ALU_OP2_MULHI_UINT;
2661 alu.src[0].sel = 0;
2662 alu.src[0].chan = 3;
2663 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2664 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2665 alu.dst.sel = i + 1;
2666 alu.dst.chan = j;
2667 alu.dst.write = j == 3;
2668 alu.last = j == 3;
2669 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2670 r600_bytecode_clear(&bc);
2671 return NULL;
2672 }
2673 }
2674 } else {
2675 struct r600_bytecode_alu alu;
2676 memset(&alu, 0, sizeof(alu));
2677 alu.op = ALU_OP2_MULHI_UINT;
2678 alu.src[0].sel = 0;
2679 alu.src[0].chan = 3;
2680 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
2681 alu.src[1].value = (1ll << 32) / elements[i].instance_divisor + 1;
2682 alu.dst.sel = i + 1;
2683 alu.dst.chan = 3;
2684 alu.dst.write = 1;
2685 alu.last = 1;
2686 if ((r = r600_bytecode_add_alu(&bc, &alu))) {
2687 r600_bytecode_clear(&bc);
2688 return NULL;
2689 }
2690 }
2691 }
2692 }
2693
2694 for (i = 0; i < count; i++) {
2695 r600_vertex_data_type(elements[i].src_format,
2696 &format, &num_format, &format_comp, &endian);
2697
2698 desc = util_format_description(elements[i].src_format);
2699 if (!desc) {
2700 r600_bytecode_clear(&bc);
2701 R600_ERR("unknown format %d\n", elements[i].src_format);
2702 return NULL;
2703 }
2704
2705 if (elements[i].src_offset > 65535) {
2706 r600_bytecode_clear(&bc);
2707 R600_ERR("too big src_offset: %u\n", elements[i].src_offset);
2708 return NULL;
2709 }
2710
2711 memset(&vtx, 0, sizeof(vtx));
2712 vtx.buffer_id = elements[i].vertex_buffer_index + fetch_resource_start;
2713 vtx.fetch_type = elements[i].instance_divisor ? SQ_VTX_FETCH_INSTANCE_DATA : SQ_VTX_FETCH_VERTEX_DATA;
2714 vtx.src_gpr = elements[i].instance_divisor > 1 ? i + 1 : 0;
2715 vtx.src_sel_x = elements[i].instance_divisor ? 3 : 0;
2716 vtx.mega_fetch_count = 0x1F;
2717 vtx.dst_gpr = i + 1;
2718 vtx.dst_sel_x = desc->swizzle[0];
2719 vtx.dst_sel_y = desc->swizzle[1];
2720 vtx.dst_sel_z = desc->swizzle[2];
2721 vtx.dst_sel_w = desc->swizzle[3];
2722 vtx.data_format = format;
2723 vtx.num_format_all = num_format;
2724 vtx.format_comp_all = format_comp;
2725 vtx.offset = elements[i].src_offset;
2726 vtx.endian = endian;
2727
2728 if ((r = r600_bytecode_add_vtx(&bc, &vtx))) {
2729 r600_bytecode_clear(&bc);
2730 return NULL;
2731 }
2732 }
2733
2734 r600_bytecode_add_cfinst(&bc, CF_OP_RET);
2735
2736 if ((r = r600_bytecode_build(&bc))) {
2737 r600_bytecode_clear(&bc);
2738 return NULL;
2739 }
2740
2741 if (rctx->screen->b.debug_flags & DBG_FS) {
2742 fprintf(stderr, "--------------------------------------------------------------\n");
2743 fprintf(stderr, "Vertex elements state:\n");
2744 for (i = 0; i < count; i++) {
2745 fprintf(stderr, " ");
2746 util_dump_vertex_element(stderr, elements+i);
2747 fprintf(stderr, "\n");
2748 }
2749
2750 if (!sb_disasm) {
2751 r600_bytecode_disasm(&bc);
2752
2753 fprintf(stderr, "______________________________________________________________\n");
2754 } else {
2755 r600_sb_bytecode_process(rctx, &bc, NULL, 1 /*dump*/, 0 /*optimize*/);
2756 }
2757 }
2758
2759 fs_size = bc.ndw*4;
2760
2761 /* Allocate the CSO. */
2762 shader = CALLOC_STRUCT(r600_fetch_shader);
2763 if (!shader) {
2764 r600_bytecode_clear(&bc);
2765 return NULL;
2766 }
2767
2768 u_suballocator_alloc(rctx->allocator_fetch_shader, fs_size, 256,
2769 &shader->offset,
2770 (struct pipe_resource**)&shader->buffer);
2771 if (!shader->buffer) {
2772 r600_bytecode_clear(&bc);
2773 FREE(shader);
2774 return NULL;
2775 }
2776
2777 bytecode = r600_buffer_map_sync_with_rings
2778 (&rctx->b, shader->buffer,
2779 PIPE_TRANSFER_WRITE | PIPE_TRANSFER_UNSYNCHRONIZED | RADEON_TRANSFER_TEMPORARY);
2780 bytecode += shader->offset / 4;
2781
2782 if (R600_BIG_ENDIAN) {
2783 for (i = 0; i < fs_size / 4; ++i) {
2784 bytecode[i] = util_cpu_to_le32(bc.bytecode[i]);
2785 }
2786 } else {
2787 memcpy(bytecode, bc.bytecode, fs_size);
2788 }
2789 rctx->b.ws->buffer_unmap(shader->buffer->buf);
2790
2791 r600_bytecode_clear(&bc);
2792 return shader;
2793 }
2794
2795 void r600_bytecode_alu_read(struct r600_bytecode *bc,
2796 struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1)
2797 {
2798 /* WORD0 */
2799 alu->src[0].sel = G_SQ_ALU_WORD0_SRC0_SEL(word0);
2800 alu->src[0].rel = G_SQ_ALU_WORD0_SRC0_REL(word0);
2801 alu->src[0].chan = G_SQ_ALU_WORD0_SRC0_CHAN(word0);
2802 alu->src[0].neg = G_SQ_ALU_WORD0_SRC0_NEG(word0);
2803 alu->src[1].sel = G_SQ_ALU_WORD0_SRC1_SEL(word0);
2804 alu->src[1].rel = G_SQ_ALU_WORD0_SRC1_REL(word0);
2805 alu->src[1].chan = G_SQ_ALU_WORD0_SRC1_CHAN(word0);
2806 alu->src[1].neg = G_SQ_ALU_WORD0_SRC1_NEG(word0);
2807 alu->index_mode = G_SQ_ALU_WORD0_INDEX_MODE(word0);
2808 alu->pred_sel = G_SQ_ALU_WORD0_PRED_SEL(word0);
2809 alu->last = G_SQ_ALU_WORD0_LAST(word0);
2810
2811 /* WORD1 */
2812 alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
2813 if (alu->bank_swizzle)
2814 alu->bank_swizzle_force = alu->bank_swizzle;
2815 alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
2816 alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
2817 alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
2818 alu->dst.clamp = G_SQ_ALU_WORD1_CLAMP(word1);
2819 if (G_SQ_ALU_WORD1_ENCODING(word1)) /*ALU_DWORD1_OP3*/
2820 {
2821 alu->is_op3 = 1;
2822 alu->src[2].sel = G_SQ_ALU_WORD1_OP3_SRC2_SEL(word1);
2823 alu->src[2].rel = G_SQ_ALU_WORD1_OP3_SRC2_REL(word1);
2824 alu->src[2].chan = G_SQ_ALU_WORD1_OP3_SRC2_CHAN(word1);
2825 alu->src[2].neg = G_SQ_ALU_WORD1_OP3_SRC2_NEG(word1);
2826 alu->op = r600_isa_alu_by_opcode(bc->isa,
2827 G_SQ_ALU_WORD1_OP3_ALU_INST(word1), /* is_op3 = */ 1);
2828
2829 }
2830 else /*ALU_DWORD1_OP2*/
2831 {
2832 alu->src[0].abs = G_SQ_ALU_WORD1_OP2_SRC0_ABS(word1);
2833 alu->src[1].abs = G_SQ_ALU_WORD1_OP2_SRC1_ABS(word1);
2834 alu->op = r600_isa_alu_by_opcode(bc->isa,
2835 G_SQ_ALU_WORD1_OP2_ALU_INST(word1), /* is_op3 = */ 0);
2836 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1);
2837 alu->dst.write = G_SQ_ALU_WORD1_OP2_WRITE_MASK(word1);
2838 alu->update_pred = G_SQ_ALU_WORD1_OP2_UPDATE_PRED(word1);
2839 alu->execute_mask =
2840 G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
2841 }
2842 }
2843
2844 #if 0
2845 void r600_bytecode_export_read(struct r600_bytecode *bc,
2846 struct r600_bytecode_output *output, uint32_t word0, uint32_t word1)
2847 {
2848 output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
2849 output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
2850 output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
2851 output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
2852
2853 output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
2854 output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
2855 output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
2856 output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
2857 output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
2858 output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
2859 output->op = r600_isa_cf_by_opcode(bc->isa,
2860 G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1), 0);
2861 output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
2862 output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
2863 output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
2864 }
2865 #endif