src/gallium/drivers/r600/r600_draw.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include <pipe/p_screen.h>
  30 #include <util/u_format.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "radeon.h"
  35 #include "r600_screen.h"
  36 #include "r600_context.h"
  37 #include "r600_resource.h"
  38 #include "r600_state_inlines.h"
  39
  40 struct r600_draw {
  41         struct pipe_context     *ctx;
  42         struct radeon_state     draw;
  43         struct radeon_state     vgt;
  44         unsigned                mode;
  45         unsigned                start;
  46         unsigned                count;
  47         unsigned                index_size;
  48         struct pipe_resource    *index_buffer;
  49 };
  50
  51 static int r600_draw_common(struct r600_draw *draw)
  52 {
  53         struct r600_context *rctx = r600_context(draw->ctx);
  54         struct r600_screen *rscreen = rctx->screen;
  55         /* FIXME vs_resource */
  56         struct radeon_state *vs_resource;
  57         struct r600_resource *rbuffer;
  58         unsigned i, j, offset, format, prim;
  59         u32 vgt_dma_index_type, vgt_draw_initiator;
  60         struct pipe_vertex_buffer *vertex_buffer;
  61         int r;
  62
  63         r = r600_context_hw_states(draw->ctx);
  64         if (r)
  65                 return r;
  66         switch (draw->index_size) {
  67         case 2:
  68                 vgt_draw_initiator = 0;
  69                 vgt_dma_index_type = 0;
  70                 break;
  71         case 4:
  72                 vgt_draw_initiator = 0;
  73                 vgt_dma_index_type = 1;
  74                 break;
  75         case 0:
  76                 vgt_draw_initiator = 2;
  77                 vgt_dma_index_type = 0;
  78                 break;
  79         default:
  80                 fprintf(stderr, "%s %d unsupported index size %d\n", __func__, __LINE__, draw->index_size);
  81                 return -EINVAL;
  82         }
  83         r = r600_conv_pipe_prim(draw->mode, &prim);
  84         if (r)
  85                 return r;
  86
  87         /* rebuild vertex shader if input format changed */
  88         r = r600_pipe_shader_update(draw->ctx, rctx->vs_shader);
  89         if (r)
  90                 return r;
  91         r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
  92         if (r)
  93                 return r;
  94         radeon_draw_bind(&rctx->draw, &rctx->vs_shader->rstate[0]);
  95         radeon_draw_bind(&rctx->draw, &rctx->ps_shader->rstate[0]);
  96
  97         for (i = 0 ; i < rctx->vs_nresource; i++) {
  98                 radeon_state_fini(&rctx->vs_resource[i]);
  99         }
 100         for (i = 0 ; i < rctx->vertex_elements->count; i++) {
 101                 vs_resource = &rctx->vs_resource[i];
 102                 j = rctx->vertex_elements->elements[i].vertex_buffer_index;
 103                 vertex_buffer = &rctx->vertex_buffer[j];
 104                 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 105                 offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 106                 format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
 107                 radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, i, R600_SHADER_VS);
 108                 vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 109                 vs_resource->nbo = 1;
 110                 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
 111                 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
 112                 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
 113                                                                 S_038008_DATA_FORMAT(format);
 114                 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
 115                 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
 116                 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
 117                 vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
 118                 vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
 119                 vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
 120                 r = radeon_state_pm4(vs_resource);
 121                 if (r) {
 122                         return r;
 123                 }
 124                 radeon_draw_bind(&rctx->draw, vs_resource);
 125         }
 126         rctx->vs_nresource = rctx->vertex_elements->count;
 127         /* FIXME start need to change winsys */
 128         radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
 129         draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
 130         draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 131         if (draw->index_buffer) {
 132                 rbuffer = (struct r600_resource*)draw->index_buffer;
 133                 draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 134                 draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
 135                 draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
 136                 draw->draw.nbo = 1;
 137         }
 138         r = radeon_state_pm4(&draw->draw);
 139         if (r) {
 140                 return r;
 141         }
 142         radeon_draw_bind(&rctx->draw, &draw->draw);
 143
 144         radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
 145         draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
 146         draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
 147         draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
 148         draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
 149         draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
 150         draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
 151         draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
 152         draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
 153         draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
 154         draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
 155         draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
 156         r = radeon_state_pm4(&draw->vgt);
 157         if (r) {
 158                 return r;
 159         }
 160         radeon_draw_bind(&rctx->draw, &draw->vgt);
 161
 162         r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
 163         if (r == -EBUSY) {
 164                 r600_flush(draw->ctx, 0, NULL);
 165                 r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
 166         }
 167         return r;
 168 }
 169
 170 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 171 {
 172         struct r600_context *rctx = r600_context(ctx);
 173         struct r600_draw draw;
 174         int r;
 175
 176         assert(info->index_bias == 0);
 177
 178         draw.ctx = ctx;
 179         draw.mode = info->mode;
 180         draw.start = info->start;
 181         draw.count = info->count;
 182         if (info->indexed && rctx->index_buffer.buffer) {
 183                 draw.index_size = rctx->index_buffer.index_size;
 184                 draw.index_buffer = rctx->index_buffer.buffer;
 185
 186                 assert(rctx->index_buffer.offset %
 187                                 rctx->index_buffer.index_size == 0);
 188                 draw.start += rctx->index_buffer.offset /
 189                         rctx->index_buffer.index_size;
 190         }
 191         else {
 192                 draw.index_size = 0;
 193                 draw.index_buffer = NULL;
 194         }
 195         r = r600_draw_common(&draw);
 196         if (r)
 197           fprintf(stderr,"draw common failed %d\n", r);
 198 }