projects / mesa.git / blob
? search:


d65b2841613d2d986077b87ed1b110c9f8b4417c
[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include <errno.h>
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_screen.h"
36 #include "util/u_simple_shaders.h"
37 #include "util/u_upload_mgr.h"
38 #include "util/u_math.h"
39 #include "vl/vl_decoder.h"
40 #include "vl/vl_video_buffer.h"
41 #include "radeon_video.h"
42 #include "radeon_uvd.h"
43 #include "util/os_time.h"
44
45 static const struct debug_named_value r600_debug_options[] = {
46 /* features */
47 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
48
49 /* shader backend */
50 { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
51 { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
52 { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
53 { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
54 { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
55 { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
56 { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
57 { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
58
59 DEBUG_NAMED_VALUE_END /* must be last */
60 };
61
62 /*
63 * pipe_context
64 */
65
66 static void r600_destroy_context(struct pipe_context *context)
67 {
68 struct r600_context *rctx = (struct r600_context *)context;
69 unsigned sh, i;
70
71 r600_isa_destroy(rctx->isa);
72
73 r600_sb_context_destroy(rctx->sb_context);
74
75 for (sh = 0; sh < (rctx->b.chip_class < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) {
76 r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL);
77 }
78 r600_resource_reference(&rctx->dummy_cmask, NULL);
79 r600_resource_reference(&rctx->dummy_fmask, NULL);
80
81 if (rctx->append_fence)
82 pipe_resource_reference((struct pipe_resource**)&rctx->append_fence, NULL);
83 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
84 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
85 free(rctx->driver_consts[sh].constants);
86 }
87
88 if (rctx->fixed_func_tcs_shader)
89 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
90
91 if (rctx->dummy_pixel_shader) {
92 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
93 }
94 if (rctx->custom_dsa_flush) {
95 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
96 }
97 if (rctx->custom_blend_resolve) {
98 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
99 }
100 if (rctx->custom_blend_decompress) {
101 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
102 }
103 if (rctx->custom_blend_fastclear) {
104 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
105 }
106 util_unreference_framebuffer_state(&rctx->framebuffer.state);
107
108 if (rctx->gs_rings.gsvs_ring.buffer)
109 pipe_resource_reference(&rctx->gs_rings.gsvs_ring.buffer, NULL);
110
111 if (rctx->gs_rings.esgs_ring.buffer)
112 pipe_resource_reference(&rctx->gs_rings.esgs_ring.buffer, NULL);
113
114 for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh)
115 for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i)
116 rctx->b.b.set_constant_buffer(context, sh, i, NULL);
117
118 if (rctx->blitter) {
119 util_blitter_destroy(rctx->blitter);
120 }
121 if (rctx->allocator_fetch_shader) {
122 u_suballocator_destroy(rctx->allocator_fetch_shader);
123 }
124
125 r600_release_command_buffer(&rctx->start_cs_cmd);
126
127 FREE(rctx->start_compute_cs_cmd.buf);
128
129 r600_common_context_cleanup(&rctx->b);
130
131 r600_resource_reference(&rctx->trace_buf, NULL);
132 r600_resource_reference(&rctx->last_trace_buf, NULL);
133 radeon_clear_saved_cs(&rctx->last_gfx);
134
135 FREE(rctx);
136 }
137
138 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
139 void *priv, unsigned flags)
140 {
141 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
142 struct r600_screen* rscreen = (struct r600_screen *)screen;
143 struct radeon_winsys *ws = rscreen->b.ws;
144
145 if (!rctx)
146 return NULL;
147
148 rctx->b.b.screen = screen;
149 assert(!priv);
150 rctx->b.b.priv = NULL; /* for threaded_context_unwrap_sync */
151 rctx->b.b.destroy = r600_destroy_context;
152 rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
153
154 if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
155 goto fail;
156
157 rctx->screen = rscreen;
158 list_inithead(&rctx->texture_buffers);
159
160 r600_init_blit_functions(rctx);
161
162 if (rscreen->b.info.has_hw_decode) {
163 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
164 rctx->b.b.create_video_buffer = r600_video_buffer_create;
165 } else {
166 rctx->b.b.create_video_codec = vl_create_decoder;
167 rctx->b.b.create_video_buffer = vl_video_buffer_create;
168 }
169
170 if (getenv("R600_TRACE"))
171 rctx->is_debug = true;
172 r600_init_common_state_functions(rctx);
173
174 switch (rctx->b.chip_class) {
175 case R600:
176 case R700:
177 r600_init_state_functions(rctx);
178 r600_init_atom_start_cs(rctx);
179 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
180 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
181 : r600_create_resolve_blend(rctx);
182 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
183 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
184 rctx->b.family == CHIP_RV620 ||
185 rctx->b.family == CHIP_RS780 ||
186 rctx->b.family == CHIP_RS880 ||
187 rctx->b.family == CHIP_RV710);
188 break;
189 case EVERGREEN:
190 case CAYMAN:
191 evergreen_init_state_functions(rctx);
192 evergreen_init_atom_start_cs(rctx);
193 evergreen_init_atom_start_compute_cs(rctx);
194 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
195 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
196 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
197 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
198 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
199 rctx->b.family == CHIP_PALM ||
200 rctx->b.family == CHIP_SUMO ||
201 rctx->b.family == CHIP_SUMO2 ||
202 rctx->b.family == CHIP_CAICOS ||
203 rctx->b.family == CHIP_CAYMAN ||
204 rctx->b.family == CHIP_ARUBA);
205
206 rctx->append_fence = pipe_buffer_create(rctx->b.b.screen, PIPE_BIND_CUSTOM,
207 PIPE_USAGE_DEFAULT, 32);
208 break;
209 default:
210 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
211 goto fail;
212 }
213
214 rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
215 r600_context_gfx_flush, rctx, false);
216 rctx->b.gfx.flush = r600_context_gfx_flush;
217
218 rctx->allocator_fetch_shader =
219 u_suballocator_create(&rctx->b.b, 64 * 1024,
220 0, PIPE_USAGE_DEFAULT, 0, FALSE);
221 if (!rctx->allocator_fetch_shader)
222 goto fail;
223
224 rctx->isa = calloc(1, sizeof(struct r600_isa));
225 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
226 goto fail;
227
228 if (rscreen->b.debug_flags & DBG_FORCE_DMA)
229 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
230
231 rctx->blitter = util_blitter_create(&rctx->b.b);
232 if (rctx->blitter == NULL)
233 goto fail;
234 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
235 rctx->blitter->draw_rectangle = r600_draw_rectangle;
236
237 r600_begin_new_cs(rctx);
238
239 rctx->dummy_pixel_shader =
240 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
241 TGSI_SEMANTIC_GENERIC,
242 TGSI_INTERPOLATE_CONSTANT);
243 rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
244
245 return &rctx->b.b;
246
247 fail:
248 r600_destroy_context(&rctx->b.b);
249 return NULL;
250 }
251
252 static bool is_nir_enabled(struct r600_common_screen *screen) {
253 return (screen->debug_flags & DBG_NIR &&
254 screen->family >= CHIP_CEDAR &&
255 screen->family < CHIP_CAYMAN);
256 }
257
258 /*
259 * pipe_screen
260 */
261
262 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
263 {
264 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
265 enum radeon_family family = rscreen->b.family;
266
267 switch (param) {
268 /* Supported features (boolean caps). */
269 case PIPE_CAP_NPOT_TEXTURES:
270 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
271 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
272 case PIPE_CAP_ANISOTROPIC_FILTER:
273 case PIPE_CAP_POINT_SPRITE:
274 case PIPE_CAP_OCCLUSION_QUERY:
275 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
276 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
277 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
278 case PIPE_CAP_TEXTURE_SWIZZLE:
279 case PIPE_CAP_DEPTH_CLIP_DISABLE:
280 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
281 case PIPE_CAP_SHADER_STENCIL_EXPORT:
282 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
283 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
284 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
285 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
286 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
287 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
288 case PIPE_CAP_VERTEX_SHADER_SATURATE:
289 case PIPE_CAP_SEAMLESS_CUBE_MAP:
290 case PIPE_CAP_PRIMITIVE_RESTART:
291 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
292 case PIPE_CAP_CONDITIONAL_RENDER:
293 case PIPE_CAP_TEXTURE_BARRIER:
294 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
295 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
296 case PIPE_CAP_TGSI_INSTANCEID:
297 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
298 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
299 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
300 case PIPE_CAP_START_INSTANCE:
301 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
302 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
303 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
304 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
305 case PIPE_CAP_TEXTURE_MULTISAMPLE:
306 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
307 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
308 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
309 case PIPE_CAP_SAMPLE_SHADING:
310 case PIPE_CAP_CLIP_HALFZ:
311 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
312 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
313 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
314 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
315 case PIPE_CAP_TGSI_TXQS:
316 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
317 case PIPE_CAP_INVALIDATE_BUFFER:
318 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
319 case PIPE_CAP_QUERY_MEMORY_INFO:
320 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
321 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
322 case PIPE_CAP_CLEAR_TEXTURE:
323 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
324 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
325 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
326 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
327 return 1;
328
329 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
330 /* Optimal number for good TexSubImage performance on Polaris10. */
331 return 64 * 1024 * 1024;
332
333 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
334 return rscreen->b.info.drm_minor >= 43;
335
336 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
337 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
338
339 case PIPE_CAP_COMPUTE:
340 return rscreen->b.chip_class > R700;
341
342 case PIPE_CAP_TGSI_TEXCOORD:
343 return 1;
344
345 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
346 case PIPE_CAP_FAKE_SW_MSAA:
347 return 0;
348
349 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
350 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
351
352 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
353 return R600_MAP_BUFFER_ALIGNMENT;
354
355 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
356 return 256;
357
358 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
359 return 1;
360
361 case PIPE_CAP_GLSL_FEATURE_LEVEL:
362 if (family >= CHIP_CEDAR)
363 return 430;
364 /* pre-evergreen geom shaders need newer kernel */
365 if (rscreen->b.info.drm_minor >= 37)
366 return 330;
367 return 140;
368
369 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
370 return 140;
371
372 /* Supported except the original R600. */
373 case PIPE_CAP_INDEP_BLEND_ENABLE:
374 case PIPE_CAP_INDEP_BLEND_FUNC:
375 /* R600 doesn't support per-MRT blends */
376 return family == CHIP_R600 ? 0 : 1;
377
378 /* Supported on Evergreen. */
379 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
380 case PIPE_CAP_CUBE_MAP_ARRAY:
381 case PIPE_CAP_TEXTURE_GATHER_SM5:
382 case PIPE_CAP_TEXTURE_QUERY_LOD:
383 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
384 case PIPE_CAP_SAMPLER_VIEW_TARGET:
385 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
386 case PIPE_CAP_TGSI_CLOCK:
387 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
388 case PIPE_CAP_QUERY_BUFFER_OBJECT:
389 return family >= CHIP_CEDAR ? 1 : 0;
390 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
391 return family >= CHIP_CEDAR ? 4 : 0;
392 case PIPE_CAP_DRAW_INDIRECT:
393 /* kernel command checker support is also required */
394 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
395
396 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
397 return family >= CHIP_CEDAR ? 0 : 1;
398
399 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
400 return 8;
401
402 case PIPE_CAP_MAX_GS_INVOCATIONS:
403 return 32;
404
405 /* shader buffer objects */
406 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
407 return 1 << 27;
408 case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
409 return 8;
410
411 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
412 return 0;
413
414 case PIPE_CAP_DOUBLES:
415 if (rscreen->b.family == CHIP_ARUBA ||
416 rscreen->b.family == CHIP_CAYMAN ||
417 rscreen->b.family == CHIP_CYPRESS ||
418 rscreen->b.family == CHIP_HEMLOCK)
419 return 1;
420 return 0;
421 case PIPE_CAP_CULL_DISTANCE:
422 return 1;
423
424 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
425 if (family >= CHIP_CEDAR)
426 return 256;
427 return 0;
428
429 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
430 if (family >= CHIP_CEDAR)
431 return 30;
432 else
433 return 0;
434 /* Stream output. */
435 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
436 return rscreen->b.has_streamout ? 4 : 0;
437 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
438 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
439 return rscreen->b.has_streamout ? 1 : 0;
440 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
441 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
442 return 32*4;
443
444 /* Geometry shader output. */
445 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
446 return 1024;
447 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
448 return 16384;
449 case PIPE_CAP_MAX_VERTEX_STREAMS:
450 return family >= CHIP_CEDAR ? 4 : 1;
451
452 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
453 /* Should be 2047, but 2048 is a requirement for GL 4.4 */
454 return 2048;
455
456 /* Texturing. */
457 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
458 if (family >= CHIP_CEDAR)
459 return 16384;
460 else
461 return 8192;
462 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
463 if (family >= CHIP_CEDAR)
464 return 15;
465 else
466 return 14;
467 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
468 /* textures support 8192, but layered rendering supports 2048 */
469 return 12;
470 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
471 /* textures support 8192, but layered rendering supports 2048 */
472 return 2048;
473
474 /* Render targets. */
475 case PIPE_CAP_MAX_RENDER_TARGETS:
476 /* XXX some r6xx are buggy and can only do 4 */
477 return 8;
478
479 case PIPE_CAP_MAX_VIEWPORTS:
480 return R600_MAX_VIEWPORTS;
481 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
482 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
483 return 8;
484
485 /* Timer queries, present when the clock frequency is non zero. */
486 case PIPE_CAP_QUERY_TIME_ELAPSED:
487 return rscreen->b.info.clock_crystal_freq != 0;
488 case PIPE_CAP_QUERY_TIMESTAMP:
489 return rscreen->b.info.drm_minor >= 20 &&
490 rscreen->b.info.clock_crystal_freq != 0;
491
492 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
493 case PIPE_CAP_MIN_TEXEL_OFFSET:
494 return -8;
495
496 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
497 case PIPE_CAP_MAX_TEXEL_OFFSET:
498 return 7;
499
500 case PIPE_CAP_MAX_VARYINGS:
501 return 32;
502
503 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
504 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
505 case PIPE_CAP_ENDIANNESS:
506 return PIPE_ENDIAN_LITTLE;
507
508 case PIPE_CAP_VENDOR_ID:
509 return ATI_VENDOR_ID;
510 case PIPE_CAP_DEVICE_ID:
511 return rscreen->b.info.pci_id;
512 case PIPE_CAP_ACCELERATED:
513 return 1;
514 case PIPE_CAP_VIDEO_MEMORY:
515 return rscreen->b.info.vram_size >> 20;
516 case PIPE_CAP_UMA:
517 return 0;
518 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
519 return rscreen->b.chip_class >= R700;
520 case PIPE_CAP_PCI_GROUP:
521 return rscreen->b.info.pci_domain;
522 case PIPE_CAP_PCI_BUS:
523 return rscreen->b.info.pci_bus;
524 case PIPE_CAP_PCI_DEVICE:
525 return rscreen->b.info.pci_dev;
526 case PIPE_CAP_PCI_FUNCTION:
527 return rscreen->b.info.pci_func;
528
529 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
530 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
531 return 8;
532 return 0;
533 case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
534 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
535 return EG_MAX_ATOMIC_BUFFERS;
536 return 0;
537
538 default:
539 return u_pipe_screen_get_param_defaults(pscreen, param);
540 }
541 }
542
543 static int r600_get_shader_param(struct pipe_screen* pscreen,
544 enum pipe_shader_type shader,
545 enum pipe_shader_cap param)
546 {
547 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
548
549 switch(shader)
550 {
551 case PIPE_SHADER_FRAGMENT:
552 case PIPE_SHADER_VERTEX:
553 break;
554 case PIPE_SHADER_GEOMETRY:
555 if (rscreen->b.family >= CHIP_CEDAR)
556 break;
557 /* pre-evergreen geom shaders need newer kernel */
558 if (rscreen->b.info.drm_minor >= 37)
559 break;
560 return 0;
561 /* With NIR we currently disable TES, TCS and COMP shaders */
562 case PIPE_SHADER_TESS_CTRL:
563 case PIPE_SHADER_TESS_EVAL:
564 if (rscreen->b.family >= CHIP_CEDAR)
565 break;
566 /* fallthrough */
567 case PIPE_SHADER_COMPUTE:
568 if (!is_nir_enabled(&rscreen->b))
569 break;
570 /* fallthrough */
571 default:
572 return 0;
573 }
574
575 switch (param) {
576 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
577 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
578 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
579 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
580 return 16384;
581 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
582 return 32;
583 case PIPE_SHADER_CAP_MAX_INPUTS:
584 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
585 case PIPE_SHADER_CAP_MAX_OUTPUTS:
586 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
587 case PIPE_SHADER_CAP_MAX_TEMPS:
588 return 256; /* Max native temporaries. */
589 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
590 if (shader == PIPE_SHADER_COMPUTE) {
591 uint64_t max_const_buffer_size;
592 enum pipe_shader_ir ir_type = is_nir_enabled(&rscreen->b) ?
593 PIPE_SHADER_IR_NIR: PIPE_SHADER_IR_TGSI;
594 pscreen->get_compute_param(pscreen, ir_type,
595 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
596 &max_const_buffer_size);
597 return MIN2(max_const_buffer_size, INT_MAX);
598
599 } else {
600 return R600_MAX_CONST_BUFFER_SIZE;
601 }
602 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
603 return R600_MAX_USER_CONST_BUFFERS;
604 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
605 return 1;
606 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
607 return 1;
608 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
609 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
610 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
611 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
612 return 1;
613 case PIPE_SHADER_CAP_SUBROUTINES:
614 case PIPE_SHADER_CAP_INT64_ATOMICS:
615 case PIPE_SHADER_CAP_FP16:
616 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
617 case PIPE_SHADER_CAP_INT16:
618 case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS:
619 return 0;
620 case PIPE_SHADER_CAP_INTEGERS:
621 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
622 return 1;
623 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
624 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
625 return 16;
626 case PIPE_SHADER_CAP_PREFERRED_IR:
627 if (is_nir_enabled(&rscreen->b))
628 return PIPE_SHADER_IR_NIR;
629 return PIPE_SHADER_IR_TGSI;
630 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
631 int ir = 0;
632 if (shader == PIPE_SHADER_COMPUTE)
633 ir = 1 << PIPE_SHADER_IR_NATIVE;
634 if (rscreen->b.family >= CHIP_CEDAR) {
635 ir |= 1 << PIPE_SHADER_IR_TGSI;
636 if (is_nir_enabled(&rscreen->b))
637 ir |= 1 << PIPE_SHADER_IR_NIR;
638 }
639 return ir;
640 }
641 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
642 if (rscreen->b.family == CHIP_ARUBA ||
643 rscreen->b.family == CHIP_CAYMAN ||
644 rscreen->b.family == CHIP_CYPRESS ||
645 rscreen->b.family == CHIP_HEMLOCK)
646 return 1;
647 return 0;
648 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
649 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
650 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
651 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
652 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
653 return 0;
654 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
655 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
656 if (rscreen->b.family >= CHIP_CEDAR &&
657 (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE))
658 return 8;
659 return 0;
660 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
661 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics)
662 return 8;
663 return 0;
664 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
665 /* having to allocate the atomics out amongst shaders stages is messy,
666 so give compute 8 buffers and all the others one */
667 if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) {
668 return EG_MAX_ATOMIC_BUFFERS;
669 }
670 return 0;
671 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
672 /* due to a bug in the shader compiler, some loops hang
673 * if they are not unrolled, see:
674 * https://bugs.freedesktop.org/show_bug.cgi?id=86720
675 */
676 return 255;
677 }
678 return 0;
679 }
680
681 static void r600_destroy_screen(struct pipe_screen* pscreen)
682 {
683 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
684
685 if (!rscreen)
686 return;
687
688 if (!rscreen->b.ws->unref(rscreen->b.ws))
689 return;
690
691 if (rscreen->global_pool) {
692 compute_memory_pool_delete(rscreen->global_pool);
693 }
694
695 r600_destroy_common_screen(&rscreen->b);
696 }
697
698 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
699 const struct pipe_resource *templ)
700 {
701 if (templ->target == PIPE_BUFFER &&
702 (templ->bind & PIPE_BIND_GLOBAL))
703 return r600_compute_global_buffer_create(screen, templ);
704
705 return r600_resource_create_common(screen, templ);
706 }
707
708 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws,
709 const struct pipe_screen_config *config)
710 {
711 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
712
713 if (!rscreen) {
714 return NULL;
715 }
716
717 /* Set functions first. */
718 rscreen->b.b.context_create = r600_create_context;
719 rscreen->b.b.destroy = r600_destroy_screen;
720 rscreen->b.b.get_param = r600_get_param;
721 rscreen->b.b.get_shader_param = r600_get_shader_param;
722 rscreen->b.b.resource_create = r600_resource_create;
723
724 if (!r600_common_screen_init(&rscreen->b, ws)) {
725 FREE(rscreen);
726 return NULL;
727 }
728
729 if (rscreen->b.info.chip_class >= EVERGREEN) {
730 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
731 } else {
732 rscreen->b.b.is_format_supported = r600_is_format_supported;
733 }
734
735 rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
736 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
737 rscreen->b.debug_flags |= DBG_COMPUTE;
738 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
739 rscreen->b.debug_flags |= DBG_ALL_SHADERS | DBG_FS;
740 if (!debug_get_bool_option("R600_HYPERZ", TRUE))
741 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
742
743 if (rscreen->b.family == CHIP_UNKNOWN) {
744 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
745 FREE(rscreen);
746 return NULL;
747 }
748
749 /* Figure out streamout kernel support. */
750 switch (rscreen->b.chip_class) {
751 case R600:
752 if (rscreen->b.family < CHIP_RS780) {
753 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
754 } else {
755 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
756 }
757 break;
758 case R700:
759 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
760 break;
761 case EVERGREEN:
762 case CAYMAN:
763 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
764 break;
765 default:
766 rscreen->b.has_streamout = FALSE;
767 break;
768 }
769
770 /* MSAA support. */
771 switch (rscreen->b.chip_class) {
772 case R600:
773 case R700:
774 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
775 rscreen->has_compressed_msaa_texturing = false;
776 break;
777 case EVERGREEN:
778 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
779 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
780 break;
781 case CAYMAN:
782 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
783 rscreen->has_compressed_msaa_texturing = true;
784 break;
785 default:
786 rscreen->has_msaa = FALSE;
787 rscreen->has_compressed_msaa_texturing = false;
788 }
789
790 rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
791 !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
792
793 rscreen->b.barrier_flags.cp_to_L2 =
794 R600_CONTEXT_INV_VERTEX_CACHE |
795 R600_CONTEXT_INV_TEX_CACHE |
796 R600_CONTEXT_INV_CONST_CACHE;
797 rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV;
798
799 rscreen->global_pool = compute_memory_pool_new(rscreen);
800
801 /* Create the auxiliary context. This must be done last. */
802 rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
803
804 rscreen->has_atomics = rscreen->b.info.drm_minor >= 44;
805 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
806 struct pipe_resource templ = {};
807
808 templ.width0 = 4;
809 templ.height0 = 2048;
810 templ.depth0 = 1;
811 templ.array_size = 1;
812 templ.target = PIPE_TEXTURE_2D;
813 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
814 templ.usage = PIPE_USAGE_DEFAULT;
815
816 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
817 unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
818
819 memset(map, 0, 256);
820
821 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
822 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
823 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
824 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
825 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
826
827 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
828
829 int i;
830 for (i = 0; i < 256; i++) {
831 printf("%02X", map[i]);
832 if (i % 16 == 15)
833 printf("\n");
834 }
835 #endif
836
837 if (rscreen->b.debug_flags & DBG_TEST_DMA)
838 r600_test_dma(&rscreen->b);
839
840 r600_query_fix_enabled_rb_mask(&rscreen->b);
841 return &rscreen->b.b;
842 }