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[mesa.git] / src / gallium / drivers / r600 / r600_pipe_common.c
1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon_video.h"
39 #include <inttypes.h>
40 #include <sys/utsname.h>
41
42 #ifndef HAVE_LLVM
43 #define HAVE_LLVM 0
44 #endif
45
46 #if HAVE_LLVM
47 #include <llvm-c/TargetMachine.h>
48 #endif
49
50 #ifndef MESA_LLVM_VERSION_PATCH
51 #define MESA_LLVM_VERSION_PATCH 0
52 #endif
53
54 struct r600_multi_fence {
55 struct pipe_reference reference;
56 struct pipe_fence_handle *gfx;
57 struct pipe_fence_handle *sdma;
58
59 /* If the context wasn't flushed at fence creation, this is non-NULL. */
60 struct {
61 struct r600_common_context *ctx;
62 unsigned ib_index;
63 } gfx_unflushed;
64 };
65
66 /*
67 * shader binary helpers.
68 */
69 void radeon_shader_binary_init(struct ac_shader_binary *b)
70 {
71 memset(b, 0, sizeof(*b));
72 }
73
74 void radeon_shader_binary_clean(struct ac_shader_binary *b)
75 {
76 if (!b)
77 return;
78 FREE(b->code);
79 FREE(b->config);
80 FREE(b->rodata);
81 FREE(b->global_symbol_offsets);
82 FREE(b->relocs);
83 FREE(b->disasm_string);
84 FREE(b->llvm_ir_string);
85 }
86
87 /*
88 * pipe_context
89 */
90
91 /**
92 * Write an EOP event.
93 *
94 * \param event EVENT_TYPE_*
95 * \param event_flags Optional cache flush flags (TC)
96 * \param data_sel 1 = fence, 3 = timestamp
97 * \param buf Buffer
98 * \param va GPU address
99 * \param old_value Previous fence value (for a bug workaround)
100 * \param new_value Fence value to write for this event.
101 */
102 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
103 unsigned event, unsigned event_flags,
104 unsigned data_sel,
105 struct r600_resource *buf, uint64_t va,
106 uint32_t new_fence, unsigned query_type)
107 {
108 struct radeon_winsys_cs *cs = ctx->gfx.cs;
109 unsigned op = EVENT_TYPE(event) |
110 EVENT_INDEX(5) |
111 event_flags;
112 unsigned sel = EOP_DATA_SEL(data_sel);
113
114 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
115 radeon_emit(cs, op);
116 radeon_emit(cs, va);
117 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
118 radeon_emit(cs, new_fence); /* immediate data */
119 radeon_emit(cs, 0); /* unused */
120
121 if (buf)
122 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_WRITE,
123 RADEON_PRIO_QUERY);
124 }
125
126 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
127 {
128 unsigned dwords = 6;
129
130 if (!screen->info.has_virtual_memory)
131 dwords += 2;
132
133 return dwords;
134 }
135
136 void r600_gfx_wait_fence(struct r600_common_context *ctx,
137 uint64_t va, uint32_t ref, uint32_t mask)
138 {
139 struct radeon_winsys_cs *cs = ctx->gfx.cs;
140
141 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
142 radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
143 radeon_emit(cs, va);
144 radeon_emit(cs, va >> 32);
145 radeon_emit(cs, ref); /* reference value */
146 radeon_emit(cs, mask); /* mask */
147 radeon_emit(cs, 4); /* poll interval */
148 }
149
150 void r600_draw_rectangle(struct blitter_context *blitter,
151 void *vertex_elements_cso,
152 blitter_get_vs_func get_vs,
153 int x1, int y1, int x2, int y2,
154 float depth, unsigned num_instances,
155 enum blitter_attrib_type type,
156 const union blitter_attrib *attrib)
157 {
158 struct r600_common_context *rctx =
159 (struct r600_common_context*)util_blitter_get_pipe(blitter);
160 struct pipe_viewport_state viewport;
161 struct pipe_resource *buf = NULL;
162 unsigned offset = 0;
163 float *vb;
164
165 rctx->b.bind_vertex_elements_state(&rctx->b, vertex_elements_cso);
166 rctx->b.bind_vs_state(&rctx->b, get_vs(blitter));
167
168 /* Some operations (like color resolve on r6xx) don't work
169 * with the conventional primitive types.
170 * One that works is PT_RECTLIST, which we use here. */
171
172 /* setup viewport */
173 viewport.scale[0] = 1.0f;
174 viewport.scale[1] = 1.0f;
175 viewport.scale[2] = 1.0f;
176 viewport.translate[0] = 0.0f;
177 viewport.translate[1] = 0.0f;
178 viewport.translate[2] = 0.0f;
179 rctx->b.set_viewport_states(&rctx->b, 0, 1, &viewport);
180
181 /* Upload vertices. The hw rectangle has only 3 vertices,
182 * The 4th one is derived from the first 3.
183 * The vertex specification should match u_blitter's vertex element state. */
184 u_upload_alloc(rctx->b.stream_uploader, 0, sizeof(float) * 24,
185 rctx->screen->info.tcc_cache_line_size,
186 &offset, &buf, (void**)&vb);
187 if (!buf)
188 return;
189
190 vb[0] = x1;
191 vb[1] = y1;
192 vb[2] = depth;
193 vb[3] = 1;
194
195 vb[8] = x1;
196 vb[9] = y2;
197 vb[10] = depth;
198 vb[11] = 1;
199
200 vb[16] = x2;
201 vb[17] = y1;
202 vb[18] = depth;
203 vb[19] = 1;
204
205 switch (type) {
206 case UTIL_BLITTER_ATTRIB_COLOR:
207 memcpy(vb+4, attrib->color, sizeof(float)*4);
208 memcpy(vb+12, attrib->color, sizeof(float)*4);
209 memcpy(vb+20, attrib->color, sizeof(float)*4);
210 break;
211 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
212 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
213 vb[6] = vb[14] = vb[22] = attrib->texcoord.z;
214 vb[7] = vb[15] = vb[23] = attrib->texcoord.w;
215 /* fall through */
216 vb[4] = attrib->texcoord.x1;
217 vb[5] = attrib->texcoord.y1;
218 vb[12] = attrib->texcoord.x1;
219 vb[13] = attrib->texcoord.y2;
220 vb[20] = attrib->texcoord.x2;
221 vb[21] = attrib->texcoord.y1;
222 break;
223 default:; /* Nothing to do. */
224 }
225
226 /* draw */
227 struct pipe_vertex_buffer vbuffer = {};
228 vbuffer.buffer.resource = buf;
229 vbuffer.stride = 2 * 4 * sizeof(float); /* vertex size */
230 vbuffer.buffer_offset = offset;
231
232 rctx->b.set_vertex_buffers(&rctx->b, blitter->vb_slot, 1, &vbuffer);
233 util_draw_arrays_instanced(&rctx->b, R600_PRIM_RECTANGLE_LIST, 0, 3,
234 0, num_instances);
235 pipe_resource_reference(&buf, NULL);
236 }
237
238 static void r600_dma_emit_wait_idle(struct r600_common_context *rctx)
239 {
240 struct radeon_winsys_cs *cs = rctx->dma.cs;
241
242 if (rctx->chip_class >= EVERGREEN)
243 radeon_emit(cs, 0xf0000000); /* NOP */
244 else {
245 /* TODO: R600-R700 should use the FENCE packet.
246 * CS checker support is required. */
247 }
248 }
249
250 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
251 struct r600_resource *dst, struct r600_resource *src)
252 {
253 uint64_t vram = ctx->dma.cs->used_vram;
254 uint64_t gtt = ctx->dma.cs->used_gart;
255
256 if (dst) {
257 vram += dst->vram_usage;
258 gtt += dst->gart_usage;
259 }
260 if (src) {
261 vram += src->vram_usage;
262 gtt += src->gart_usage;
263 }
264
265 /* Flush the GFX IB if DMA depends on it. */
266 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
267 ((dst &&
268 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, dst->buf,
269 RADEON_USAGE_READWRITE)) ||
270 (src &&
271 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, src->buf,
272 RADEON_USAGE_WRITE))))
273 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
274
275 /* Flush if there's not enough space, or if the memory usage per IB
276 * is too large.
277 *
278 * IBs using too little memory are limited by the IB submission overhead.
279 * IBs using too much memory are limited by the kernel/TTM overhead.
280 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
281 *
282 * This heuristic makes sure that DMA requests are executed
283 * very soon after the call is made and lowers memory usage.
284 * It improves texture upload performance by keeping the DMA
285 * engine busy while uploads are being submitted.
286 */
287 num_dw++; /* for emit_wait_idle below */
288 if (!ctx->ws->cs_check_space(ctx->dma.cs, num_dw) ||
289 ctx->dma.cs->used_vram + ctx->dma.cs->used_gart > 64 * 1024 * 1024 ||
290 !radeon_cs_memory_below_limit(ctx->screen, ctx->dma.cs, vram, gtt)) {
291 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
292 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw);
293 }
294
295 /* Wait for idle if either buffer has been used in the IB before to
296 * prevent read-after-write hazards.
297 */
298 if ((dst &&
299 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, dst->buf,
300 RADEON_USAGE_READWRITE)) ||
301 (src &&
302 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, src->buf,
303 RADEON_USAGE_WRITE)))
304 r600_dma_emit_wait_idle(ctx);
305
306 /* If GPUVM is not supported, the CS checker needs 2 entries
307 * in the buffer list per packet, which has to be done manually.
308 */
309 if (ctx->screen->info.has_virtual_memory) {
310 if (dst)
311 radeon_add_to_buffer_list(ctx, &ctx->dma, dst,
312 RADEON_USAGE_WRITE,
313 RADEON_PRIO_SDMA_BUFFER);
314 if (src)
315 radeon_add_to_buffer_list(ctx, &ctx->dma, src,
316 RADEON_USAGE_READ,
317 RADEON_PRIO_SDMA_BUFFER);
318 }
319
320 /* this function is called before all DMA calls, so increment this. */
321 ctx->num_dma_calls++;
322 }
323
324 static void r600_memory_barrier(struct pipe_context *ctx, unsigned flags)
325 {
326 }
327
328 void r600_preflush_suspend_features(struct r600_common_context *ctx)
329 {
330 /* suspend queries */
331 if (!LIST_IS_EMPTY(&ctx->active_queries))
332 r600_suspend_queries(ctx);
333
334 ctx->streamout.suspended = false;
335 if (ctx->streamout.begin_emitted) {
336 r600_emit_streamout_end(ctx);
337 ctx->streamout.suspended = true;
338 }
339 }
340
341 void r600_postflush_resume_features(struct r600_common_context *ctx)
342 {
343 if (ctx->streamout.suspended) {
344 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
345 r600_streamout_buffers_dirty(ctx);
346 }
347
348 /* resume queries */
349 if (!LIST_IS_EMPTY(&ctx->active_queries))
350 r600_resume_queries(ctx);
351 }
352
353 static void r600_add_fence_dependency(struct r600_common_context *rctx,
354 struct pipe_fence_handle *fence)
355 {
356 struct radeon_winsys *ws = rctx->ws;
357
358 if (rctx->dma.cs)
359 ws->cs_add_fence_dependency(rctx->dma.cs, fence);
360 ws->cs_add_fence_dependency(rctx->gfx.cs, fence);
361 }
362
363 static void r600_fence_server_sync(struct pipe_context *ctx,
364 struct pipe_fence_handle *fence)
365 {
366 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
367 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
368
369 /* Only amdgpu needs to handle fence dependencies (for fence imports).
370 * radeon synchronizes all rings by default and will not implement
371 * fence imports.
372 */
373 if (rctx->screen->info.drm_major == 2)
374 return;
375
376 /* Only imported fences need to be handled by fence_server_sync,
377 * because the winsys handles synchronizations automatically for BOs
378 * within the process.
379 *
380 * Simply skip unflushed fences here, and the winsys will drop no-op
381 * dependencies (i.e. dependencies within the same ring).
382 */
383 if (rfence->gfx_unflushed.ctx)
384 return;
385
386 /* All unflushed commands will not start execution before
387 * this fence dependency is signalled.
388 *
389 * Should we flush the context to allow more GPU parallelism?
390 */
391 if (rfence->sdma)
392 r600_add_fence_dependency(rctx, rfence->sdma);
393 if (rfence->gfx)
394 r600_add_fence_dependency(rctx, rfence->gfx);
395 }
396
397 static void r600_flush_from_st(struct pipe_context *ctx,
398 struct pipe_fence_handle **fence,
399 unsigned flags)
400 {
401 struct pipe_screen *screen = ctx->screen;
402 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
403 struct radeon_winsys *ws = rctx->ws;
404 struct pipe_fence_handle *gfx_fence = NULL;
405 struct pipe_fence_handle *sdma_fence = NULL;
406 bool deferred_fence = false;
407 unsigned rflags = RADEON_FLUSH_ASYNC;
408
409 if (flags & PIPE_FLUSH_END_OF_FRAME)
410 rflags |= RADEON_FLUSH_END_OF_FRAME;
411
412 /* DMA IBs are preambles to gfx IBs, therefore must be flushed first. */
413 if (rctx->dma.cs)
414 rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
415
416 if (!radeon_emitted(rctx->gfx.cs, rctx->initial_gfx_cs_size)) {
417 if (fence)
418 ws->fence_reference(&gfx_fence, rctx->last_gfx_fence);
419 if (!(flags & PIPE_FLUSH_DEFERRED))
420 ws->cs_sync_flush(rctx->gfx.cs);
421 } else {
422 /* Instead of flushing, create a deferred fence. Constraints:
423 * - The state tracker must allow a deferred flush.
424 * - The state tracker must request a fence.
425 * Thread safety in fence_finish must be ensured by the state tracker.
426 */
427 if (flags & PIPE_FLUSH_DEFERRED && fence) {
428 gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
429 deferred_fence = true;
430 } else {
431 rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
432 }
433 }
434
435 /* Both engines can signal out of order, so we need to keep both fences. */
436 if (fence) {
437 struct r600_multi_fence *multi_fence =
438 CALLOC_STRUCT(r600_multi_fence);
439 if (!multi_fence) {
440 ws->fence_reference(&sdma_fence, NULL);
441 ws->fence_reference(&gfx_fence, NULL);
442 goto finish;
443 }
444
445 multi_fence->reference.count = 1;
446 /* If both fences are NULL, fence_finish will always return true. */
447 multi_fence->gfx = gfx_fence;
448 multi_fence->sdma = sdma_fence;
449
450 if (deferred_fence) {
451 multi_fence->gfx_unflushed.ctx = rctx;
452 multi_fence->gfx_unflushed.ib_index = rctx->num_gfx_cs_flushes;
453 }
454
455 screen->fence_reference(screen, fence, NULL);
456 *fence = (struct pipe_fence_handle*)multi_fence;
457 }
458 finish:
459 if (!(flags & PIPE_FLUSH_DEFERRED)) {
460 if (rctx->dma.cs)
461 ws->cs_sync_flush(rctx->dma.cs);
462 ws->cs_sync_flush(rctx->gfx.cs);
463 }
464 }
465
466 static void r600_flush_dma_ring(void *ctx, unsigned flags,
467 struct pipe_fence_handle **fence)
468 {
469 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
470 struct radeon_winsys_cs *cs = rctx->dma.cs;
471 struct radeon_saved_cs saved;
472 bool check_vm =
473 (rctx->screen->debug_flags & DBG_CHECK_VM) &&
474 rctx->check_vm_faults;
475
476 if (!radeon_emitted(cs, 0)) {
477 if (fence)
478 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
479 return;
480 }
481
482 if (check_vm)
483 radeon_save_cs(rctx->ws, cs, &saved, true);
484
485 rctx->ws->cs_flush(cs, flags, &rctx->last_sdma_fence);
486 if (fence)
487 rctx->ws->fence_reference(fence, rctx->last_sdma_fence);
488
489 if (check_vm) {
490 /* Use conservative timeout 800ms, after which we won't wait any
491 * longer and assume the GPU is hung.
492 */
493 rctx->ws->fence_wait(rctx->ws, rctx->last_sdma_fence, 800*1000*1000);
494
495 rctx->check_vm_faults(rctx, &saved, RING_DMA);
496 radeon_clear_saved_cs(&saved);
497 }
498 }
499
500 /**
501 * Store a linearized copy of all chunks of \p cs together with the buffer
502 * list in \p saved.
503 */
504 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
505 struct radeon_saved_cs *saved, bool get_buffer_list)
506 {
507 uint32_t *buf;
508 unsigned i;
509
510 /* Save the IB chunks. */
511 saved->num_dw = cs->prev_dw + cs->current.cdw;
512 saved->ib = MALLOC(4 * saved->num_dw);
513 if (!saved->ib)
514 goto oom;
515
516 buf = saved->ib;
517 for (i = 0; i < cs->num_prev; ++i) {
518 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4);
519 buf += cs->prev[i].cdw;
520 }
521 memcpy(buf, cs->current.buf, cs->current.cdw * 4);
522
523 if (!get_buffer_list)
524 return;
525
526 /* Save the buffer list. */
527 saved->bo_count = ws->cs_get_buffer_list(cs, NULL);
528 saved->bo_list = CALLOC(saved->bo_count,
529 sizeof(saved->bo_list[0]));
530 if (!saved->bo_list) {
531 FREE(saved->ib);
532 goto oom;
533 }
534 ws->cs_get_buffer_list(cs, saved->bo_list);
535
536 return;
537
538 oom:
539 fprintf(stderr, "%s: out of memory\n", __func__);
540 memset(saved, 0, sizeof(*saved));
541 }
542
543 void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
544 {
545 FREE(saved->ib);
546 FREE(saved->bo_list);
547
548 memset(saved, 0, sizeof(*saved));
549 }
550
551 static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
552 {
553 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
554 unsigned latest = rctx->ws->query_value(rctx->ws,
555 RADEON_GPU_RESET_COUNTER);
556
557 if (rctx->gpu_reset_counter == latest)
558 return PIPE_NO_RESET;
559
560 rctx->gpu_reset_counter = latest;
561 return PIPE_UNKNOWN_CONTEXT_RESET;
562 }
563
564 static void r600_set_debug_callback(struct pipe_context *ctx,
565 const struct pipe_debug_callback *cb)
566 {
567 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
568
569 if (cb)
570 rctx->debug = *cb;
571 else
572 memset(&rctx->debug, 0, sizeof(rctx->debug));
573 }
574
575 static void r600_set_device_reset_callback(struct pipe_context *ctx,
576 const struct pipe_device_reset_callback *cb)
577 {
578 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
579
580 if (cb)
581 rctx->device_reset_callback = *cb;
582 else
583 memset(&rctx->device_reset_callback, 0,
584 sizeof(rctx->device_reset_callback));
585 }
586
587 bool r600_check_device_reset(struct r600_common_context *rctx)
588 {
589 enum pipe_reset_status status;
590
591 if (!rctx->device_reset_callback.reset)
592 return false;
593
594 if (!rctx->b.get_device_reset_status)
595 return false;
596
597 status = rctx->b.get_device_reset_status(&rctx->b);
598 if (status == PIPE_NO_RESET)
599 return false;
600
601 rctx->device_reset_callback.reset(rctx->device_reset_callback.data, status);
602 return true;
603 }
604
605 static void r600_dma_clear_buffer_fallback(struct pipe_context *ctx,
606 struct pipe_resource *dst,
607 uint64_t offset, uint64_t size,
608 unsigned value)
609 {
610 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
611
612 rctx->clear_buffer(ctx, dst, offset, size, value, R600_COHERENCY_NONE);
613 }
614
615 static bool r600_resource_commit(struct pipe_context *pctx,
616 struct pipe_resource *resource,
617 unsigned level, struct pipe_box *box,
618 bool commit)
619 {
620 struct r600_common_context *ctx = (struct r600_common_context *)pctx;
621 struct r600_resource *res = r600_resource(resource);
622
623 /*
624 * Since buffer commitment changes cannot be pipelined, we need to
625 * (a) flush any pending commands that refer to the buffer we're about
626 * to change, and
627 * (b) wait for threaded submit to finish, including those that were
628 * triggered by some other, earlier operation.
629 */
630 if (radeon_emitted(ctx->gfx.cs, ctx->initial_gfx_cs_size) &&
631 ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs,
632 res->buf, RADEON_USAGE_READWRITE)) {
633 ctx->gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
634 }
635 if (radeon_emitted(ctx->dma.cs, 0) &&
636 ctx->ws->cs_is_buffer_referenced(ctx->dma.cs,
637 res->buf, RADEON_USAGE_READWRITE)) {
638 ctx->dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
639 }
640
641 ctx->ws->cs_sync_flush(ctx->dma.cs);
642 ctx->ws->cs_sync_flush(ctx->gfx.cs);
643
644 assert(resource->target == PIPE_BUFFER);
645
646 return ctx->ws->buffer_commit(res->buf, box->x, box->width, commit);
647 }
648
649 bool r600_common_context_init(struct r600_common_context *rctx,
650 struct r600_common_screen *rscreen,
651 unsigned context_flags)
652 {
653 slab_create_child(&rctx->pool_transfers, &rscreen->pool_transfers);
654 slab_create_child(&rctx->pool_transfers_unsync, &rscreen->pool_transfers);
655
656 rctx->screen = rscreen;
657 rctx->ws = rscreen->ws;
658 rctx->family = rscreen->family;
659 rctx->chip_class = rscreen->chip_class;
660
661 rctx->b.invalidate_resource = r600_invalidate_resource;
662 rctx->b.resource_commit = r600_resource_commit;
663 rctx->b.transfer_map = u_transfer_map_vtbl;
664 rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
665 rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
666 rctx->b.texture_subdata = u_default_texture_subdata;
667 rctx->b.memory_barrier = r600_memory_barrier;
668 rctx->b.flush = r600_flush_from_st;
669 rctx->b.set_debug_callback = r600_set_debug_callback;
670 rctx->b.fence_server_sync = r600_fence_server_sync;
671 rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
672
673 /* evergreen_compute.c has a special codepath for global buffers.
674 * Everything else can use the direct path.
675 */
676 if ((rscreen->chip_class == EVERGREEN || rscreen->chip_class == CAYMAN) &&
677 (context_flags & PIPE_CONTEXT_COMPUTE_ONLY))
678 rctx->b.buffer_subdata = u_default_buffer_subdata;
679 else
680 rctx->b.buffer_subdata = r600_buffer_subdata;
681
682 if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
683 rctx->b.get_device_reset_status = r600_get_reset_status;
684 rctx->gpu_reset_counter =
685 rctx->ws->query_value(rctx->ws,
686 RADEON_GPU_RESET_COUNTER);
687 }
688
689 rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
690
691 r600_init_context_texture_functions(rctx);
692 r600_init_viewport_functions(rctx);
693 r600_streamout_init(rctx);
694 r600_query_init(rctx);
695 cayman_init_msaa(&rctx->b);
696
697 rctx->allocator_zeroed_memory =
698 u_suballocator_create(&rctx->b, rscreen->info.gart_page_size,
699 0, PIPE_USAGE_DEFAULT, 0, true);
700 if (!rctx->allocator_zeroed_memory)
701 return false;
702
703 rctx->b.stream_uploader = u_upload_create(&rctx->b, 1024 * 1024,
704 0, PIPE_USAGE_STREAM);
705 if (!rctx->b.stream_uploader)
706 return false;
707
708 rctx->b.const_uploader = u_upload_create(&rctx->b, 128 * 1024,
709 0, PIPE_USAGE_DEFAULT);
710 if (!rctx->b.const_uploader)
711 return false;
712
713 rctx->ctx = rctx->ws->ctx_create(rctx->ws);
714 if (!rctx->ctx)
715 return false;
716
717 if (rscreen->info.num_sdma_rings && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
718 rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
719 r600_flush_dma_ring,
720 rctx);
721 rctx->dma.flush = r600_flush_dma_ring;
722 }
723
724 return true;
725 }
726
727 void r600_common_context_cleanup(struct r600_common_context *rctx)
728 {
729 if (rctx->query_result_shader)
730 rctx->b.delete_compute_state(&rctx->b, rctx->query_result_shader);
731
732 if (rctx->gfx.cs)
733 rctx->ws->cs_destroy(rctx->gfx.cs);
734 if (rctx->dma.cs)
735 rctx->ws->cs_destroy(rctx->dma.cs);
736 if (rctx->ctx)
737 rctx->ws->ctx_destroy(rctx->ctx);
738
739 if (rctx->b.stream_uploader)
740 u_upload_destroy(rctx->b.stream_uploader);
741 if (rctx->b.const_uploader)
742 u_upload_destroy(rctx->b.const_uploader);
743
744 slab_destroy_child(&rctx->pool_transfers);
745 slab_destroy_child(&rctx->pool_transfers_unsync);
746
747 if (rctx->allocator_zeroed_memory) {
748 u_suballocator_destroy(rctx->allocator_zeroed_memory);
749 }
750 rctx->ws->fence_reference(&rctx->last_gfx_fence, NULL);
751 rctx->ws->fence_reference(&rctx->last_sdma_fence, NULL);
752 r600_resource_reference(&rctx->eop_bug_scratch, NULL);
753 }
754
755 /*
756 * pipe_screen
757 */
758
759 static const struct debug_named_value common_debug_options[] = {
760 /* logging */
761 { "tex", DBG_TEX, "Print texture info" },
762 { "nir", DBG_NIR, "Enable experimental NIR shaders" },
763 { "compute", DBG_COMPUTE, "Print compute info" },
764 { "vm", DBG_VM, "Print virtual addresses when creating resources" },
765 { "info", DBG_INFO, "Print driver information" },
766
767 /* shaders */
768 { "fs", DBG_FS, "Print fetch shaders" },
769 { "vs", DBG_VS, "Print vertex shaders" },
770 { "gs", DBG_GS, "Print geometry shaders" },
771 { "ps", DBG_PS, "Print pixel shaders" },
772 { "cs", DBG_CS, "Print compute shaders" },
773 { "tcs", DBG_TCS, "Print tessellation control shaders" },
774 { "tes", DBG_TES, "Print tessellation evaluation shaders" },
775 { "noir", DBG_NO_IR, "Don't print the LLVM IR"},
776 { "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
777 { "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
778 { "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
779 { "checkir", DBG_CHECK_IR, "Enable additional sanity checks on shader IR" },
780 { "nooptvariant", DBG_NO_OPT_VARIANT, "Disable compiling optimized shader variants." },
781
782 { "testdma", DBG_TEST_DMA, "Invoke SDMA tests and exit." },
783 { "testvmfaultcp", DBG_TEST_VMFAULT_CP, "Invoke a CP VM fault test and exit." },
784 { "testvmfaultsdma", DBG_TEST_VMFAULT_SDMA, "Invoke a SDMA VM fault test and exit." },
785 { "testvmfaultshader", DBG_TEST_VMFAULT_SHADER, "Invoke a shader VM fault test and exit." },
786
787 /* features */
788 { "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },
789 { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
790 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
791 { "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of INVALIDATE_RANGE map flags" },
792 { "no2d", DBG_NO_2D_TILING, "Disable 2D tiling" },
793 { "notiling", DBG_NO_TILING, "Disable tiling" },
794 { "switch_on_eop", DBG_SWITCH_ON_EOP, "Program WD/IA to switch on end-of-packet." },
795 { "forcedma", DBG_FORCE_DMA, "Use asynchronous DMA for all operations when possible." },
796 { "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader creation." },
797 { "nowc", DBG_NO_WC, "Disable GTT write combining" },
798 { "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
799 { "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader optimizations" },
800
801 DEBUG_NAMED_VALUE_END /* must be last */
802 };
803
804 static const char* r600_get_vendor(struct pipe_screen* pscreen)
805 {
806 return "X.Org";
807 }
808
809 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
810 {
811 return "AMD";
812 }
813
814 static const char *r600_get_marketing_name(struct radeon_winsys *ws)
815 {
816 if (!ws->get_chip_name)
817 return NULL;
818 return ws->get_chip_name(ws);
819 }
820
821 static const char *r600_get_family_name(const struct r600_common_screen *rscreen)
822 {
823 switch (rscreen->info.family) {
824 case CHIP_R600: return "AMD R600";
825 case CHIP_RV610: return "AMD RV610";
826 case CHIP_RV630: return "AMD RV630";
827 case CHIP_RV670: return "AMD RV670";
828 case CHIP_RV620: return "AMD RV620";
829 case CHIP_RV635: return "AMD RV635";
830 case CHIP_RS780: return "AMD RS780";
831 case CHIP_RS880: return "AMD RS880";
832 case CHIP_RV770: return "AMD RV770";
833 case CHIP_RV730: return "AMD RV730";
834 case CHIP_RV710: return "AMD RV710";
835 case CHIP_RV740: return "AMD RV740";
836 case CHIP_CEDAR: return "AMD CEDAR";
837 case CHIP_REDWOOD: return "AMD REDWOOD";
838 case CHIP_JUNIPER: return "AMD JUNIPER";
839 case CHIP_CYPRESS: return "AMD CYPRESS";
840 case CHIP_HEMLOCK: return "AMD HEMLOCK";
841 case CHIP_PALM: return "AMD PALM";
842 case CHIP_SUMO: return "AMD SUMO";
843 case CHIP_SUMO2: return "AMD SUMO2";
844 case CHIP_BARTS: return "AMD BARTS";
845 case CHIP_TURKS: return "AMD TURKS";
846 case CHIP_CAICOS: return "AMD CAICOS";
847 case CHIP_CAYMAN: return "AMD CAYMAN";
848 case CHIP_ARUBA: return "AMD ARUBA";
849 default: return "AMD unknown";
850 }
851 }
852
853 static void r600_disk_cache_create(struct r600_common_screen *rscreen)
854 {
855 /* Don't use the cache if shader dumping is enabled. */
856 if (rscreen->debug_flags & DBG_ALL_SHADERS)
857 return;
858
859 uint32_t mesa_timestamp;
860 if (disk_cache_get_function_timestamp(r600_disk_cache_create,
861 &mesa_timestamp)) {
862 char *timestamp_str;
863 int res = -1;
864
865 res = asprintf(&timestamp_str, "%u",mesa_timestamp);
866 if (res != -1) {
867 /* These flags affect shader compilation. */
868 uint64_t shader_debug_flags =
869 rscreen->debug_flags &
870 (DBG_FS_CORRECT_DERIVS_AFTER_KILL |
871 DBG_UNSAFE_MATH);
872
873 rscreen->disk_shader_cache =
874 disk_cache_create(r600_get_family_name(rscreen),
875 timestamp_str,
876 shader_debug_flags);
877 free(timestamp_str);
878 }
879 }
880 }
881
882 static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
883 {
884 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
885 return rscreen->disk_shader_cache;
886 }
887
888 static const char* r600_get_name(struct pipe_screen* pscreen)
889 {
890 struct r600_common_screen *rscreen = (struct r600_common_screen*)pscreen;
891
892 return rscreen->renderer_string;
893 }
894
895 static float r600_get_paramf(struct pipe_screen* pscreen,
896 enum pipe_capf param)
897 {
898 struct r600_common_screen *rscreen = (struct r600_common_screen *)pscreen;
899
900 switch (param) {
901 case PIPE_CAPF_MAX_LINE_WIDTH:
902 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
903 case PIPE_CAPF_MAX_POINT_WIDTH:
904 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
905 if (rscreen->family >= CHIP_CEDAR)
906 return 16384.0f;
907 else
908 return 8192.0f;
909 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
910 return 16.0f;
911 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
912 return 16.0f;
913 case PIPE_CAPF_GUARD_BAND_LEFT:
914 case PIPE_CAPF_GUARD_BAND_TOP:
915 case PIPE_CAPF_GUARD_BAND_RIGHT:
916 case PIPE_CAPF_GUARD_BAND_BOTTOM:
917 return 0.0f;
918 }
919 return 0.0f;
920 }
921
922 static int r600_get_video_param(struct pipe_screen *screen,
923 enum pipe_video_profile profile,
924 enum pipe_video_entrypoint entrypoint,
925 enum pipe_video_cap param)
926 {
927 switch (param) {
928 case PIPE_VIDEO_CAP_SUPPORTED:
929 return vl_profile_supported(screen, profile, entrypoint);
930 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
931 return 1;
932 case PIPE_VIDEO_CAP_MAX_WIDTH:
933 case PIPE_VIDEO_CAP_MAX_HEIGHT:
934 return vl_video_buffer_max_size(screen);
935 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
936 return PIPE_FORMAT_NV12;
937 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
938 return false;
939 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
940 return false;
941 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
942 return true;
943 case PIPE_VIDEO_CAP_MAX_LEVEL:
944 return vl_level_supported(screen, profile);
945 default:
946 return 0;
947 }
948 }
949
950 const char *r600_get_llvm_processor_name(enum radeon_family family)
951 {
952 switch (family) {
953 case CHIP_R600:
954 case CHIP_RV630:
955 case CHIP_RV635:
956 case CHIP_RV670:
957 return "r600";
958 case CHIP_RV610:
959 case CHIP_RV620:
960 case CHIP_RS780:
961 case CHIP_RS880:
962 return "rs880";
963 case CHIP_RV710:
964 return "rv710";
965 case CHIP_RV730:
966 return "rv730";
967 case CHIP_RV740:
968 case CHIP_RV770:
969 return "rv770";
970 case CHIP_PALM:
971 case CHIP_CEDAR:
972 return "cedar";
973 case CHIP_SUMO:
974 case CHIP_SUMO2:
975 return "sumo";
976 case CHIP_REDWOOD:
977 return "redwood";
978 case CHIP_JUNIPER:
979 return "juniper";
980 case CHIP_HEMLOCK:
981 case CHIP_CYPRESS:
982 return "cypress";
983 case CHIP_BARTS:
984 return "barts";
985 case CHIP_TURKS:
986 return "turks";
987 case CHIP_CAICOS:
988 return "caicos";
989 case CHIP_CAYMAN:
990 case CHIP_ARUBA:
991 return "cayman";
992
993 default:
994 return "";
995 }
996 }
997
998 static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
999 enum pipe_shader_ir ir_type)
1000 {
1001 return 256;
1002 }
1003
1004 static int r600_get_compute_param(struct pipe_screen *screen,
1005 enum pipe_shader_ir ir_type,
1006 enum pipe_compute_cap param,
1007 void *ret)
1008 {
1009 struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
1010
1011 //TODO: select these params by asic
1012 switch (param) {
1013 case PIPE_COMPUTE_CAP_IR_TARGET: {
1014 const char *gpu;
1015 const char *triple = "r600--";
1016 gpu = r600_get_llvm_processor_name(rscreen->family);
1017 if (ret) {
1018 sprintf(ret, "%s-%s", gpu, triple);
1019 }
1020 /* +2 for dash and terminating NIL byte */
1021 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
1022 }
1023 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
1024 if (ret) {
1025 uint64_t *grid_dimension = ret;
1026 grid_dimension[0] = 3;
1027 }
1028 return 1 * sizeof(uint64_t);
1029
1030 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
1031 if (ret) {
1032 uint64_t *grid_size = ret;
1033 grid_size[0] = 65535;
1034 grid_size[1] = 65535;
1035 grid_size[2] = 65535;
1036 }
1037 return 3 * sizeof(uint64_t) ;
1038
1039 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
1040 if (ret) {
1041 uint64_t *block_size = ret;
1042 unsigned threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1043 block_size[0] = threads_per_block;
1044 block_size[1] = threads_per_block;
1045 block_size[2] = threads_per_block;
1046 }
1047 return 3 * sizeof(uint64_t);
1048
1049 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
1050 if (ret) {
1051 uint64_t *max_threads_per_block = ret;
1052 *max_threads_per_block = get_max_threads_per_block(rscreen, ir_type);
1053 }
1054 return sizeof(uint64_t);
1055 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
1056 if (ret) {
1057 uint32_t *address_bits = ret;
1058 address_bits[0] = 32;
1059 }
1060 return 1 * sizeof(uint32_t);
1061
1062 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
1063 if (ret) {
1064 uint64_t *max_global_size = ret;
1065 uint64_t max_mem_alloc_size;
1066
1067 r600_get_compute_param(screen, ir_type,
1068 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
1069 &max_mem_alloc_size);
1070
1071 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
1072 * 1/4 of the MAX_GLOBAL_SIZE. Since the
1073 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
1074 * make sure we never report more than
1075 * 4 * MAX_MEM_ALLOC_SIZE.
1076 */
1077 *max_global_size = MIN2(4 * max_mem_alloc_size,
1078 MAX2(rscreen->info.gart_size,
1079 rscreen->info.vram_size));
1080 }
1081 return sizeof(uint64_t);
1082
1083 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
1084 if (ret) {
1085 uint64_t *max_local_size = ret;
1086 /* Value reported by the closed source driver. */
1087 *max_local_size = 32768;
1088 }
1089 return sizeof(uint64_t);
1090
1091 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
1092 if (ret) {
1093 uint64_t *max_input_size = ret;
1094 /* Value reported by the closed source driver. */
1095 *max_input_size = 1024;
1096 }
1097 return sizeof(uint64_t);
1098
1099 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
1100 if (ret) {
1101 uint64_t *max_mem_alloc_size = ret;
1102
1103 *max_mem_alloc_size = rscreen->info.max_alloc_size;
1104 }
1105 return sizeof(uint64_t);
1106
1107 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
1108 if (ret) {
1109 uint32_t *max_clock_frequency = ret;
1110 *max_clock_frequency = rscreen->info.max_shader_clock;
1111 }
1112 return sizeof(uint32_t);
1113
1114 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
1115 if (ret) {
1116 uint32_t *max_compute_units = ret;
1117 *max_compute_units = rscreen->info.num_good_compute_units;
1118 }
1119 return sizeof(uint32_t);
1120
1121 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
1122 if (ret) {
1123 uint32_t *images_supported = ret;
1124 *images_supported = 0;
1125 }
1126 return sizeof(uint32_t);
1127 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
1128 break; /* unused */
1129 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
1130 if (ret) {
1131 uint32_t *subgroup_size = ret;
1132 *subgroup_size = r600_wavefront_size(rscreen->family);
1133 }
1134 return sizeof(uint32_t);
1135 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
1136 if (ret) {
1137 uint64_t *max_variable_threads_per_block = ret;
1138 *max_variable_threads_per_block = 0;
1139 }
1140 return sizeof(uint64_t);
1141 }
1142
1143 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
1144 return 0;
1145 }
1146
1147 static uint64_t r600_get_timestamp(struct pipe_screen *screen)
1148 {
1149 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1150
1151 return 1000000 * rscreen->ws->query_value(rscreen->ws, RADEON_TIMESTAMP) /
1152 rscreen->info.clock_crystal_freq;
1153 }
1154
1155 static void r600_fence_reference(struct pipe_screen *screen,
1156 struct pipe_fence_handle **dst,
1157 struct pipe_fence_handle *src)
1158 {
1159 struct radeon_winsys *ws = ((struct r600_common_screen*)screen)->ws;
1160 struct r600_multi_fence **rdst = (struct r600_multi_fence **)dst;
1161 struct r600_multi_fence *rsrc = (struct r600_multi_fence *)src;
1162
1163 if (pipe_reference(&(*rdst)->reference, &rsrc->reference)) {
1164 ws->fence_reference(&(*rdst)->gfx, NULL);
1165 ws->fence_reference(&(*rdst)->sdma, NULL);
1166 FREE(*rdst);
1167 }
1168 *rdst = rsrc;
1169 }
1170
1171 static boolean r600_fence_finish(struct pipe_screen *screen,
1172 struct pipe_context *ctx,
1173 struct pipe_fence_handle *fence,
1174 uint64_t timeout)
1175 {
1176 struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
1177 struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
1178 struct r600_common_context *rctx;
1179 int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
1180
1181 ctx = threaded_context_unwrap_sync(ctx);
1182 rctx = ctx ? (struct r600_common_context*)ctx : NULL;
1183
1184 if (rfence->sdma) {
1185 if (!rws->fence_wait(rws, rfence->sdma, timeout))
1186 return false;
1187
1188 /* Recompute the timeout after waiting. */
1189 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1190 int64_t time = os_time_get_nano();
1191 timeout = abs_timeout > time ? abs_timeout - time : 0;
1192 }
1193 }
1194
1195 if (!rfence->gfx)
1196 return true;
1197
1198 /* Flush the gfx IB if it hasn't been flushed yet. */
1199 if (rctx &&
1200 rfence->gfx_unflushed.ctx == rctx &&
1201 rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
1202 rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
1203 rfence->gfx_unflushed.ctx = NULL;
1204
1205 if (!timeout)
1206 return false;
1207
1208 /* Recompute the timeout after all that. */
1209 if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
1210 int64_t time = os_time_get_nano();
1211 timeout = abs_timeout > time ? abs_timeout - time : 0;
1212 }
1213 }
1214
1215 return rws->fence_wait(rws, rfence->gfx, timeout);
1216 }
1217
1218 static void r600_query_memory_info(struct pipe_screen *screen,
1219 struct pipe_memory_info *info)
1220 {
1221 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1222 struct radeon_winsys *ws = rscreen->ws;
1223 unsigned vram_usage, gtt_usage;
1224
1225 info->total_device_memory = rscreen->info.vram_size / 1024;
1226 info->total_staging_memory = rscreen->info.gart_size / 1024;
1227
1228 /* The real TTM memory usage is somewhat random, because:
1229 *
1230 * 1) TTM delays freeing memory, because it can only free it after
1231 * fences expire.
1232 *
1233 * 2) The memory usage can be really low if big VRAM evictions are
1234 * taking place, but the real usage is well above the size of VRAM.
1235 *
1236 * Instead, return statistics of this process.
1237 */
1238 vram_usage = ws->query_value(ws, RADEON_REQUESTED_VRAM_MEMORY) / 1024;
1239 gtt_usage = ws->query_value(ws, RADEON_REQUESTED_GTT_MEMORY) / 1024;
1240
1241 info->avail_device_memory =
1242 vram_usage <= info->total_device_memory ?
1243 info->total_device_memory - vram_usage : 0;
1244 info->avail_staging_memory =
1245 gtt_usage <= info->total_staging_memory ?
1246 info->total_staging_memory - gtt_usage : 0;
1247
1248 info->device_memory_evicted =
1249 ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
1250
1251 if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
1252 info->nr_device_memory_evictions =
1253 ws->query_value(ws, RADEON_NUM_EVICTIONS);
1254 else
1255 /* Just return the number of evicted 64KB pages. */
1256 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
1257 }
1258
1259 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
1260 const struct pipe_resource *templ)
1261 {
1262 if (templ->target == PIPE_BUFFER) {
1263 return r600_buffer_create(screen, templ, 256);
1264 } else {
1265 return r600_texture_create(screen, templ);
1266 }
1267 }
1268
1269 bool r600_common_screen_init(struct r600_common_screen *rscreen,
1270 struct radeon_winsys *ws)
1271 {
1272 char family_name[32] = {}, llvm_string[32] = {}, kernel_version[128] = {};
1273 struct utsname uname_data;
1274 const char *chip_name;
1275
1276 ws->query_info(ws, &rscreen->info);
1277 rscreen->ws = ws;
1278
1279 if ((chip_name = r600_get_marketing_name(ws)))
1280 snprintf(family_name, sizeof(family_name), "%s / ",
1281 r600_get_family_name(rscreen) + 4);
1282 else
1283 chip_name = r600_get_family_name(rscreen);
1284
1285 if (uname(&uname_data) == 0)
1286 snprintf(kernel_version, sizeof(kernel_version),
1287 " / %s", uname_data.release);
1288
1289 if (HAVE_LLVM > 0) {
1290 snprintf(llvm_string, sizeof(llvm_string),
1291 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
1292 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
1293 }
1294
1295 snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
1296 "%s (%sDRM %i.%i.%i%s%s)",
1297 chip_name, family_name, rscreen->info.drm_major,
1298 rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
1299 kernel_version, llvm_string);
1300
1301 rscreen->b.get_name = r600_get_name;
1302 rscreen->b.get_vendor = r600_get_vendor;
1303 rscreen->b.get_device_vendor = r600_get_device_vendor;
1304 rscreen->b.get_disk_shader_cache = r600_get_disk_shader_cache;
1305 rscreen->b.get_compute_param = r600_get_compute_param;
1306 rscreen->b.get_paramf = r600_get_paramf;
1307 rscreen->b.get_timestamp = r600_get_timestamp;
1308 rscreen->b.fence_finish = r600_fence_finish;
1309 rscreen->b.fence_reference = r600_fence_reference;
1310 rscreen->b.resource_destroy = u_resource_destroy_vtbl;
1311 rscreen->b.resource_from_user_memory = r600_buffer_from_user_memory;
1312 rscreen->b.query_memory_info = r600_query_memory_info;
1313
1314 if (rscreen->info.has_hw_decode) {
1315 rscreen->b.get_video_param = rvid_get_video_param;
1316 rscreen->b.is_video_format_supported = rvid_is_format_supported;
1317 } else {
1318 rscreen->b.get_video_param = r600_get_video_param;
1319 rscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1320 }
1321
1322 r600_init_screen_texture_functions(rscreen);
1323 r600_init_screen_query_functions(rscreen);
1324
1325 rscreen->family = rscreen->info.family;
1326 rscreen->chip_class = rscreen->info.chip_class;
1327 rscreen->debug_flags |= debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
1328
1329 r600_disk_cache_create(rscreen);
1330
1331 slab_create_parent(&rscreen->pool_transfers, sizeof(struct r600_transfer), 64);
1332
1333 rscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1334 if (rscreen->force_aniso >= 0) {
1335 printf("radeon: Forcing anisotropy filter to %ix\n",
1336 /* round down to a power of two */
1337 1 << util_logbase2(rscreen->force_aniso));
1338 }
1339
1340 (void) mtx_init(&rscreen->aux_context_lock, mtx_plain);
1341 (void) mtx_init(&rscreen->gpu_load_mutex, mtx_plain);
1342
1343 if (rscreen->debug_flags & DBG_INFO) {
1344 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
1345 rscreen->info.pci_domain, rscreen->info.pci_bus,
1346 rscreen->info.pci_dev, rscreen->info.pci_func);
1347 printf("pci_id = 0x%x\n", rscreen->info.pci_id);
1348 printf("family = %i (%s)\n", rscreen->info.family,
1349 r600_get_family_name(rscreen));
1350 printf("chip_class = %i\n", rscreen->info.chip_class);
1351 printf("pte_fragment_size = %u\n", rscreen->info.pte_fragment_size);
1352 printf("gart_page_size = %u\n", rscreen->info.gart_page_size);
1353 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.gart_size, 1024*1024));
1354 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_size, 1024*1024));
1355 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(rscreen->info.vram_vis_size, 1024*1024));
1356 printf("max_alloc_size = %i MB\n",
1357 (int)DIV_ROUND_UP(rscreen->info.max_alloc_size, 1024*1024));
1358 printf("min_alloc_size = %u\n", rscreen->info.min_alloc_size);
1359 printf("has_dedicated_vram = %u\n", rscreen->info.has_dedicated_vram);
1360 printf("has_virtual_memory = %i\n", rscreen->info.has_virtual_memory);
1361 printf("gfx_ib_pad_with_type2 = %i\n", rscreen->info.gfx_ib_pad_with_type2);
1362 printf("has_hw_decode = %u\n", rscreen->info.has_hw_decode);
1363 printf("num_sdma_rings = %i\n", rscreen->info.num_sdma_rings);
1364 printf("num_compute_rings = %u\n", rscreen->info.num_compute_rings);
1365 printf("uvd_fw_version = %u\n", rscreen->info.uvd_fw_version);
1366 printf("vce_fw_version = %u\n", rscreen->info.vce_fw_version);
1367 printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
1368 printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
1369 printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
1370 printf("vce_harvest_config = %i\n", rscreen->info.vce_harvest_config);
1371 printf("clock_crystal_freq = %i\n", rscreen->info.clock_crystal_freq);
1372 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
1373 printf("drm = %i.%i.%i\n", rscreen->info.drm_major,
1374 rscreen->info.drm_minor, rscreen->info.drm_patchlevel);
1375 printf("has_userptr = %i\n", rscreen->info.has_userptr);
1376 printf("has_syncobj = %u\n", rscreen->info.has_syncobj);
1377
1378 printf("r600_max_quad_pipes = %i\n", rscreen->info.r600_max_quad_pipes);
1379 printf("max_shader_clock = %i\n", rscreen->info.max_shader_clock);
1380 printf("num_good_compute_units = %i\n", rscreen->info.num_good_compute_units);
1381 printf("max_se = %i\n", rscreen->info.max_se);
1382 printf("max_sh_per_se = %i\n", rscreen->info.max_sh_per_se);
1383
1384 printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
1385 printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
1386 printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
1387 printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
1388 printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
1389 printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
1390 printf("enabled_rb_mask = 0x%x\n", rscreen->info.enabled_rb_mask);
1391 printf("max_alignment = %u\n", (unsigned)rscreen->info.max_alignment);
1392 }
1393 return true;
1394 }
1395
1396 void r600_destroy_common_screen(struct r600_common_screen *rscreen)
1397 {
1398 r600_perfcounters_destroy(rscreen);
1399 r600_gpu_load_kill_thread(rscreen);
1400
1401 mtx_destroy(&rscreen->gpu_load_mutex);
1402 mtx_destroy(&rscreen->aux_context_lock);
1403 rscreen->aux_context->destroy(rscreen->aux_context);
1404
1405 slab_destroy_parent(&rscreen->pool_transfers);
1406
1407 disk_cache_destroy(rscreen->disk_shader_cache);
1408 rscreen->ws->destroy(rscreen->ws);
1409 FREE(rscreen);
1410 }
1411
1412 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
1413 unsigned processor)
1414 {
1415 return rscreen->debug_flags & (1 << processor);
1416 }
1417
1418 bool r600_extra_shader_checks(struct r600_common_screen *rscreen, unsigned processor)
1419 {
1420 return (rscreen->debug_flags & DBG_CHECK_IR) ||
1421 r600_can_dump_shader(rscreen, processor);
1422 }
1423
1424 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
1425 uint64_t offset, uint64_t size, unsigned value)
1426 {
1427 struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
1428
1429 mtx_lock(&rscreen->aux_context_lock);
1430 rctx->dma_clear_buffer(&rctx->b, dst, offset, size, value);
1431 rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
1432 mtx_unlock(&rscreen->aux_context_lock);
1433 }