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Merge remote branch 'origin/master' into pipe-video
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_opcodes.h"
32 #include "r600d.h"
33 #include <stdio.h>
34 #include <errno.h>
35
36 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
37 {
38 struct r600_pipe_state *rstate = &shader->rstate;
39 struct r600_shader *rshader = &shader->shader;
40 unsigned spi_vs_out_id[10];
41 unsigned i, tmp;
42
43 /* clear previous register */
44 rstate->nregs = 0;
45
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
49 */
50 for (i = 0; i < 10; i++) {
51 spi_vs_out_id[i] = 0;
52 }
53 for (i = 0; i < 32; i++) {
54 tmp = i << ((i & 3) * 8);
55 spi_vs_out_id[i / 4] |= tmp;
56 }
57 for (i = 0; i < 10; i++) {
58 r600_pipe_state_add_reg(rstate,
59 R_028614_SPI_VS_OUT_ID_0 + i * 4,
60 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
61 }
62
63 r600_pipe_state_add_reg(rstate,
64 R_0286C4_SPI_VS_OUT_CONFIG,
65 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
66 0xFFFFFFFF, NULL);
67 r600_pipe_state_add_reg(rstate,
68 R_028868_SQ_PGM_RESOURCES_VS,
69 S_028868_NUM_GPRS(rshader->bc.ngpr) |
70 S_028868_STACK_SIZE(rshader->bc.nstack),
71 0xFFFFFFFF, NULL);
72 r600_pipe_state_add_reg(rstate,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS,
74 0x00000000, 0xFFFFFFFF, NULL);
75 r600_pipe_state_add_reg(rstate,
76 R_028858_SQ_PGM_START_VS,
77 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
78
79 r600_pipe_state_add_reg(rstate,
80 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
81 0xFFFFFFFF, NULL);
82
83 }
84
85 int r600_find_vs_semantic_index(struct r600_shader *vs,
86 struct r600_shader *ps, int id)
87 {
88 struct r600_shader_io *input = &ps->input[id];
89
90 for (int i = 0; i < vs->noutput; i++) {
91 if (input->name == vs->output[i].name &&
92 input->sid == vs->output[i].sid) {
93 return i - 1;
94 }
95 }
96 return 0;
97 }
98
99 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
100 {
101 struct r600_pipe_state *rstate = &shader->rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
104 int pos_index = -1, face_index = -1;
105
106 rstate->nregs = 0;
107
108 for (i = 0; i < rshader->ninput; i++) {
109 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
110 pos_index = i;
111 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
112 face_index = i;
113 }
114
115 for (i = 0; i < rshader->noutput; i++) {
116 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
117 r600_pipe_state_add_reg(rstate,
118 R_02880C_DB_SHADER_CONTROL,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL);
121 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
122 r600_pipe_state_add_reg(rstate,
123 R_02880C_DB_SHADER_CONTROL,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
126 }
127
128 exports_ps = 0;
129 num_cout = 0;
130 for (i = 0; i < rshader->noutput; i++) {
131 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
132 exports_ps |= 1;
133 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
134 num_cout++;
135 }
136 }
137 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
138 if (!exports_ps) {
139 /* always at least export 1 component per pixel */
140 exports_ps = 2;
141 }
142
143 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
145 spi_input_z = 0;
146 if (pos_index != -1) {
147 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
149 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
151 spi_input_z |= 1;
152 }
153
154 spi_ps_in_control_1 = 0;
155 if (face_index != -1) {
156 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
158 }
159
160 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
161 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate,
164 R_028840_SQ_PGM_START_PS,
165 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
166 r600_pipe_state_add_reg(rstate,
167 R_028850_SQ_PGM_RESOURCES_PS,
168 S_028868_NUM_GPRS(rshader->bc.ngpr) |
169 S_028868_STACK_SIZE(rshader->bc.nstack),
170 0xFFFFFFFF, NULL);
171 r600_pipe_state_add_reg(rstate,
172 R_028854_SQ_PGM_EXPORTS_PS,
173 exports_ps, 0xFFFFFFFF, NULL);
174 r600_pipe_state_add_reg(rstate,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS,
176 0x00000000, 0xFFFFFFFF, NULL);
177
178 if (rshader->uses_kill) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate,
181 R_02880C_DB_SHADER_CONTROL,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL);
184 }
185 r600_pipe_state_add_reg(rstate,
186 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
187 0xFFFFFFFF, NULL);
188 }
189
190 int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
191 {
192 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
193 struct r600_shader *rshader = &shader->shader;
194 void *ptr;
195
196 /* copy new shader */
197 if (shader->bo == NULL) {
198 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
199 if (shader->bo == NULL) {
200 return -ENOMEM;
201 }
202 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
203 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
204 r600_bo_unmap(rctx->radeon, shader->bo);
205 }
206 /* build state */
207 switch (rshader->processor_type) {
208 case TGSI_PROCESSOR_VERTEX:
209 if (rshader->family >= CHIP_CEDAR) {
210 evergreen_pipe_shader_vs(ctx, shader);
211 } else {
212 r600_pipe_shader_vs(ctx, shader);
213 }
214 break;
215 case TGSI_PROCESSOR_FRAGMENT:
216 if (rshader->family >= CHIP_CEDAR) {
217 evergreen_pipe_shader_ps(ctx, shader);
218 } else {
219 r600_pipe_shader_ps(ctx, shader);
220 }
221 break;
222 default:
223 return -EINVAL;
224 }
225 return 0;
226 }
227
228 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader, u32 **literals);
229 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
230 {
231 static int dump_shaders = -1;
232 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
233 u32 *literals;
234 int r;
235
236 /* Would like some magic "get_bool_option_once" routine.
237 */
238 if (dump_shaders == -1)
239 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
240
241 if (dump_shaders) {
242 fprintf(stderr, "--------------------------------------------------------------\n");
243 tgsi_dump(tokens, 0);
244 }
245 shader->shader.family = r600_get_family(rctx->radeon);
246 r = r600_shader_from_tgsi(tokens, &shader->shader, &literals);
247 if (r) {
248 R600_ERR("translation from TGSI failed !\n");
249 return r;
250 }
251 r = r600_bc_build(&shader->shader.bc);
252 free(literals);
253 if (r) {
254 R600_ERR("building bytecode failed !\n");
255 return r;
256 }
257 if (dump_shaders) {
258 r600_bc_dump(&shader->shader.bc);
259 fprintf(stderr, "______________________________________________________________\n");
260 }
261 return r600_pipe_shader(ctx, shader);
262 }
263
264 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
265 {
266 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
267
268 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
269 r600_bc_clear(&shader->shader.bc);
270 }
271
272 /*
273 * tgsi -> r600 shader
274 */
275 struct r600_shader_tgsi_instruction;
276
277 struct r600_shader_ctx {
278 struct tgsi_shader_info info;
279 struct tgsi_parse_context parse;
280 const struct tgsi_token *tokens;
281 unsigned type;
282 unsigned file_offset[TGSI_FILE_COUNT];
283 unsigned temp_reg;
284 struct r600_shader_tgsi_instruction *inst_info;
285 struct r600_bc *bc;
286 struct r600_shader *shader;
287 u32 *literals;
288 u32 nliterals;
289 u32 max_driver_temp_used;
290 /* needed for evergreen interpolation */
291 boolean input_centroid;
292 boolean input_linear;
293 boolean input_perspective;
294 int num_interp_gpr;
295 };
296
297 struct r600_shader_tgsi_instruction {
298 unsigned tgsi_opcode;
299 unsigned is_op3;
300 unsigned r600_opcode;
301 int (*process)(struct r600_shader_ctx *ctx);
302 };
303
304 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
305 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
306
307 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
308 {
309 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
310 int j;
311
312 if (i->Instruction.NumDstRegs > 1) {
313 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
314 return -EINVAL;
315 }
316 if (i->Instruction.Predicate) {
317 R600_ERR("predicate unsupported\n");
318 return -EINVAL;
319 }
320 #if 0
321 if (i->Instruction.Label) {
322 R600_ERR("label unsupported\n");
323 return -EINVAL;
324 }
325 #endif
326 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
327 if (i->Src[j].Register.Dimension) {
328 R600_ERR("unsupported src %d (dimension %d)\n", j,
329 i->Src[j].Register.Dimension);
330 return -EINVAL;
331 }
332 }
333 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
334 if (i->Dst[j].Register.Dimension) {
335 R600_ERR("unsupported dst (dimension)\n");
336 return -EINVAL;
337 }
338 }
339 return 0;
340 }
341
342 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
343 {
344 int i, r;
345 struct r600_bc_alu alu;
346 int gpr = 0, base_chan = 0;
347 int ij_index = 0;
348
349 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
350 ij_index = 0;
351 if (ctx->shader->input[input].centroid)
352 ij_index++;
353 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
354 ij_index = 0;
355 /* if we have perspective add one */
356 if (ctx->input_perspective) {
357 ij_index++;
358 /* if we have perspective centroid */
359 if (ctx->input_centroid)
360 ij_index++;
361 }
362 if (ctx->shader->input[input].centroid)
363 ij_index++;
364 }
365
366 /* work out gpr and base_chan from index */
367 gpr = ij_index / 2;
368 base_chan = (2 * (ij_index % 2)) + 1;
369
370 for (i = 0; i < 8; i++) {
371 memset(&alu, 0, sizeof(struct r600_bc_alu));
372
373 if (i < 4)
374 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
375 else
376 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
377
378 if ((i > 1) && (i < 6)) {
379 alu.dst.sel = ctx->shader->input[input].gpr;
380 alu.dst.write = 1;
381 }
382
383 alu.dst.chan = i % 4;
384
385 alu.src[0].sel = gpr;
386 alu.src[0].chan = (base_chan - (i % 2));
387
388 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
389
390 alu.bank_swizzle_force = SQ_ALU_VEC_210;
391 if ((i % 4) == 3)
392 alu.last = 1;
393 r = r600_bc_add_alu(ctx->bc, &alu);
394 if (r)
395 return r;
396 }
397 return 0;
398 }
399
400
401 static int tgsi_declaration(struct r600_shader_ctx *ctx)
402 {
403 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
404 unsigned i;
405
406 switch (d->Declaration.File) {
407 case TGSI_FILE_INPUT:
408 i = ctx->shader->ninput++;
409 ctx->shader->input[i].name = d->Semantic.Name;
410 ctx->shader->input[i].sid = d->Semantic.Index;
411 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
412 ctx->shader->input[i].centroid = d->Declaration.Centroid;
413 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
414 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
415 /* turn input into interpolate on EG */
416 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
417 if (ctx->shader->input[i].interpolate > 0) {
418 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
419 evergreen_interp_alu(ctx, i);
420 }
421 }
422 }
423 break;
424 case TGSI_FILE_OUTPUT:
425 i = ctx->shader->noutput++;
426 ctx->shader->output[i].name = d->Semantic.Name;
427 ctx->shader->output[i].sid = d->Semantic.Index;
428 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
429 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
430 break;
431 case TGSI_FILE_CONSTANT:
432 case TGSI_FILE_TEMPORARY:
433 case TGSI_FILE_SAMPLER:
434 case TGSI_FILE_ADDRESS:
435 break;
436 default:
437 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
438 return -EINVAL;
439 }
440 return 0;
441 }
442
443 static int r600_get_temp(struct r600_shader_ctx *ctx)
444 {
445 return ctx->temp_reg + ctx->max_driver_temp_used++;
446 }
447
448 /*
449 * for evergreen we need to scan the shader to find the number of GPRs we need to
450 * reserve for interpolation.
451 *
452 * we need to know if we are going to emit
453 * any centroid inputs
454 * if perspective and linear are required
455 */
456 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
457 {
458 int i;
459 int num_baryc;
460
461 ctx->input_linear = FALSE;
462 ctx->input_perspective = FALSE;
463 ctx->input_centroid = FALSE;
464 ctx->num_interp_gpr = 1;
465
466 /* any centroid inputs */
467 for (i = 0; i < ctx->info.num_inputs; i++) {
468 /* skip position/face */
469 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
470 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
471 continue;
472 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
473 ctx->input_linear = TRUE;
474 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
475 ctx->input_perspective = TRUE;
476 if (ctx->info.input_centroid[i])
477 ctx->input_centroid = TRUE;
478 }
479
480 num_baryc = 0;
481 /* ignoring sample for now */
482 if (ctx->input_perspective)
483 num_baryc++;
484 if (ctx->input_linear)
485 num_baryc++;
486 if (ctx->input_centroid)
487 num_baryc *= 2;
488
489 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
490
491 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
492 return ctx->num_interp_gpr;
493 }
494
495 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader, u32 **literals)
496 {
497 struct tgsi_full_immediate *immediate;
498 struct r600_shader_ctx ctx;
499 struct r600_bc_output output[32];
500 unsigned noutput;
501 unsigned opcode;
502 int i, r = 0, pos0;
503
504 ctx.bc = &shader->bc;
505 ctx.shader = shader;
506 r = r600_bc_init(ctx.bc, shader->family);
507 if (r)
508 return r;
509 ctx.tokens = tokens;
510 tgsi_scan_shader(tokens, &ctx.info);
511 tgsi_parse_init(&ctx.parse, tokens);
512 ctx.type = ctx.parse.FullHeader.Processor.Processor;
513 shader->processor_type = ctx.type;
514 ctx.bc->type = shader->processor_type;
515
516 /* register allocations */
517 /* Values [0,127] correspond to GPR[0..127].
518 * Values [128,159] correspond to constant buffer bank 0
519 * Values [160,191] correspond to constant buffer bank 1
520 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
521 * Values [256,287] correspond to constant buffer bank 2 (EG)
522 * Values [288,319] correspond to constant buffer bank 3 (EG)
523 * Other special values are shown in the list below.
524 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
525 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
526 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
527 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
528 * 248 SQ_ALU_SRC_0: special constant 0.0.
529 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
530 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
531 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
532 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
533 * 253 SQ_ALU_SRC_LITERAL: literal constant.
534 * 254 SQ_ALU_SRC_PV: previous vector result.
535 * 255 SQ_ALU_SRC_PS: previous scalar result.
536 */
537 for (i = 0; i < TGSI_FILE_COUNT; i++) {
538 ctx.file_offset[i] = 0;
539 }
540 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
541 ctx.file_offset[TGSI_FILE_INPUT] = 1;
542 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
543 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
544 } else {
545 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
546 }
547 }
548 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
549 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
550 }
551 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
552 ctx.info.file_count[TGSI_FILE_INPUT];
553 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
554 ctx.info.file_count[TGSI_FILE_OUTPUT];
555
556 /* Outside the GPR range. This will be translated to one of the
557 * kcache banks later. */
558 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
559
560 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
561 ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
562 ctx.info.file_count[TGSI_FILE_TEMPORARY];
563
564 ctx.nliterals = 0;
565 ctx.literals = NULL;
566
567 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
568 tgsi_parse_token(&ctx.parse);
569 switch (ctx.parse.FullToken.Token.Type) {
570 case TGSI_TOKEN_TYPE_IMMEDIATE:
571 immediate = &ctx.parse.FullToken.FullImmediate;
572 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
573 if(ctx.literals == NULL) {
574 r = -ENOMEM;
575 goto out_err;
576 }
577 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
578 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
579 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
580 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
581 ctx.nliterals++;
582 break;
583 case TGSI_TOKEN_TYPE_DECLARATION:
584 r = tgsi_declaration(&ctx);
585 if (r)
586 goto out_err;
587 break;
588 case TGSI_TOKEN_TYPE_INSTRUCTION:
589 r = tgsi_is_supported(&ctx);
590 if (r)
591 goto out_err;
592 ctx.max_driver_temp_used = 0;
593 /* reserve first tmp for everyone */
594 r600_get_temp(&ctx);
595 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
596 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
597 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
598 else
599 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
600 r = ctx.inst_info->process(&ctx);
601 if (r)
602 goto out_err;
603 break;
604 case TGSI_TOKEN_TYPE_PROPERTY:
605 break;
606 default:
607 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
608 r = -EINVAL;
609 goto out_err;
610 }
611 }
612 /* export output */
613 noutput = shader->noutput;
614 for (i = 0, pos0 = 0; i < noutput; i++) {
615 memset(&output[i], 0, sizeof(struct r600_bc_output));
616 output[i].gpr = shader->output[i].gpr;
617 output[i].elem_size = 3;
618 output[i].swizzle_x = 0;
619 output[i].swizzle_y = 1;
620 output[i].swizzle_z = 2;
621 output[i].swizzle_w = 3;
622 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
623 output[i].array_base = i - pos0;
624 switch (ctx.type) {
625 case TGSI_PROCESSOR_VERTEX:
626 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
627 output[i].array_base = 60;
628 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
629 /* position doesn't count in array_base */
630 pos0++;
631 }
632 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
633 output[i].array_base = 61;
634 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
635 /* position doesn't count in array_base */
636 pos0++;
637 }
638 break;
639 case TGSI_PROCESSOR_FRAGMENT:
640 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
641 output[i].array_base = shader->output[i].sid;
642 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
643 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
644 output[i].array_base = 61;
645 output[i].swizzle_x = 2;
646 output[i].swizzle_y = 7;
647 output[i].swizzle_z = output[i].swizzle_w = 7;
648 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
649 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
650 output[i].array_base = 61;
651 output[i].swizzle_x = 7;
652 output[i].swizzle_y = 1;
653 output[i].swizzle_z = output[i].swizzle_w = 7;
654 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
655 } else {
656 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
657 r = -EINVAL;
658 goto out_err;
659 }
660 break;
661 default:
662 R600_ERR("unsupported processor type %d\n", ctx.type);
663 r = -EINVAL;
664 goto out_err;
665 }
666 }
667 /* add fake param output for vertex shader if no param is exported */
668 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
669 for (i = 0, pos0 = 0; i < noutput; i++) {
670 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
671 pos0 = 1;
672 break;
673 }
674 }
675 if (!pos0) {
676 memset(&output[i], 0, sizeof(struct r600_bc_output));
677 output[i].gpr = 0;
678 output[i].elem_size = 3;
679 output[i].swizzle_x = 0;
680 output[i].swizzle_y = 1;
681 output[i].swizzle_z = 2;
682 output[i].swizzle_w = 3;
683 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
684 output[i].array_base = 0;
685 noutput++;
686 }
687 }
688 /* add fake pixel export */
689 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
690 memset(&output[0], 0, sizeof(struct r600_bc_output));
691 output[0].gpr = 0;
692 output[0].elem_size = 3;
693 output[0].swizzle_x = 7;
694 output[0].swizzle_y = 7;
695 output[0].swizzle_z = 7;
696 output[0].swizzle_w = 7;
697 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
698 output[0].array_base = 0;
699 noutput++;
700 }
701 /* add output to bytecode */
702 for (i = 0; i < noutput; i++) {
703 r = r600_bc_add_output(ctx.bc, &output[i]);
704 if (r)
705 goto out_err;
706 }
707 *literals = ctx.literals;
708 tgsi_parse_free(&ctx.parse);
709 return 0;
710 out_err:
711 free(ctx.literals);
712 tgsi_parse_free(&ctx.parse);
713 return r;
714 }
715
716 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
717 {
718 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
719 return -EINVAL;
720 }
721
722 static int tgsi_end(struct r600_shader_ctx *ctx)
723 {
724 return 0;
725 }
726
727 static int tgsi_src(struct r600_shader_ctx *ctx,
728 const struct tgsi_full_src_register *tgsi_src,
729 struct r600_bc_alu_src *r600_src)
730 {
731 memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
732 r600_src->neg = tgsi_src->Register.Negate;
733 r600_src->abs = tgsi_src->Register.Absolute;
734 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
735 int index;
736 if((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
737 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
738 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
739
740 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
741 r600_bc_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
742 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
743 return 0;
744 }
745 index = tgsi_src->Register.Index;
746 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
747 r600_src->value = ctx->literals + index * 4;
748 } else {
749 if (tgsi_src->Register.Indirect)
750 r600_src->rel = V_SQ_REL_RELATIVE;
751 r600_src->sel = tgsi_src->Register.Index;
752 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
753 }
754 return 0;
755 }
756
757 static int tgsi_dst(struct r600_shader_ctx *ctx,
758 const struct tgsi_full_dst_register *tgsi_dst,
759 unsigned swizzle,
760 struct r600_bc_alu_dst *r600_dst)
761 {
762 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
763
764 r600_dst->sel = tgsi_dst->Register.Index;
765 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
766 r600_dst->chan = swizzle;
767 r600_dst->write = 1;
768 if (tgsi_dst->Register.Indirect)
769 r600_dst->rel = V_SQ_REL_RELATIVE;
770 if (inst->Instruction.Saturate) {
771 r600_dst->clamp = 1;
772 }
773 return 0;
774 }
775
776 static unsigned tgsi_chan(const struct tgsi_full_src_register *tgsi_src, unsigned swizzle)
777 {
778 switch (swizzle) {
779 case 0:
780 return tgsi_src->Register.SwizzleX;
781 case 1:
782 return tgsi_src->Register.SwizzleY;
783 case 2:
784 return tgsi_src->Register.SwizzleZ;
785 case 3:
786 return tgsi_src->Register.SwizzleW;
787 default:
788 return 0;
789 }
790 }
791
792 static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
793 {
794 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
795 struct r600_bc_alu alu;
796 int i, j, k, nconst, r;
797
798 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
799 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
800 nconst++;
801 }
802 r = tgsi_src(ctx, &inst->Src[i], &r600_src[i]);
803 if (r) {
804 return r;
805 }
806 }
807 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
808 if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
809 int treg = r600_get_temp(ctx);
810 for (k = 0; k < 4; k++) {
811 memset(&alu, 0, sizeof(struct r600_bc_alu));
812 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
813 alu.src[0].sel = r600_src[i].sel;
814 alu.src[0].chan = k;
815 alu.src[0].rel = r600_src[i].rel;
816 alu.dst.sel = treg;
817 alu.dst.chan = k;
818 alu.dst.write = 1;
819 if (k == 3)
820 alu.last = 1;
821 r = r600_bc_add_alu(ctx->bc, &alu);
822 if (r)
823 return r;
824 }
825 r600_src[i].sel = treg;
826 r600_src[i].rel =0;
827 j--;
828 }
829 }
830 return 0;
831 }
832
833 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
834 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
835 {
836 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
837 struct r600_bc_alu alu;
838 int i, j, k, nliteral, r;
839
840 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
841 if (r600_src[i].sel == V_SQ_ALU_SRC_LITERAL) {
842 nliteral++;
843 }
844 }
845 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
846 if (j > 0 && r600_src[i].sel == V_SQ_ALU_SRC_LITERAL) {
847 int treg = r600_get_temp(ctx);
848 for (k = 0; k < 4; k++) {
849 memset(&alu, 0, sizeof(struct r600_bc_alu));
850 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
851 alu.src[0].sel = r600_src[i].sel;
852 alu.src[0].chan = k;
853 alu.src[0].value = r600_src[i].value;
854 alu.dst.sel = treg;
855 alu.dst.chan = k;
856 alu.dst.write = 1;
857 if (k == 3)
858 alu.last = 1;
859 r = r600_bc_add_alu(ctx->bc, &alu);
860 if (r)
861 return r;
862 }
863 r600_src[i].sel = treg;
864 j--;
865 }
866 }
867 return 0;
868 }
869
870 static int tgsi_last_instruction(unsigned writemask)
871 {
872 int i, lasti = 0;
873
874 for (i = 0; i < 4; i++) {
875 if (writemask & (1 << i)) {
876 lasti = i;
877 }
878 }
879 return lasti;
880 }
881
882 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
883 {
884 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
885 struct r600_bc_alu_src r600_src[3];
886 struct r600_bc_alu alu;
887 int i, j, r;
888 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
889
890 r = tgsi_split_constant(ctx, r600_src);
891 if (r)
892 return r;
893 r = tgsi_split_literal_constant(ctx, r600_src);
894 if (r)
895 return r;
896 for (i = 0; i < lasti + 1; i++) {
897 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
898 continue;
899
900 memset(&alu, 0, sizeof(struct r600_bc_alu));
901 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
902 if (r)
903 return r;
904
905 alu.inst = ctx->inst_info->r600_opcode;
906 if (!swap) {
907 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
908 alu.src[j] = r600_src[j];
909 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
910 }
911 } else {
912 alu.src[0] = r600_src[1];
913 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
914
915 alu.src[1] = r600_src[0];
916 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
917 }
918 /* handle some special cases */
919 switch (ctx->inst_info->tgsi_opcode) {
920 case TGSI_OPCODE_SUB:
921 alu.src[1].neg = 1;
922 break;
923 case TGSI_OPCODE_ABS:
924 alu.src[0].abs = 1;
925 break;
926 default:
927 break;
928 }
929 if (i == lasti) {
930 alu.last = 1;
931 }
932 r = r600_bc_add_alu(ctx->bc, &alu);
933 if (r)
934 return r;
935 }
936 return 0;
937 }
938
939 static int tgsi_op2(struct r600_shader_ctx *ctx)
940 {
941 return tgsi_op2_s(ctx, 0);
942 }
943
944 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
945 {
946 return tgsi_op2_s(ctx, 1);
947 }
948
949 /*
950 * r600 - trunc to -PI..PI range
951 * r700 - normalize by dividing by 2PI
952 * see fdo bug 27901
953 */
954 static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
955 struct r600_bc_alu_src r600_src[3])
956 {
957 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
958 static float double_pi = 3.1415926535 * 2;
959 static float neg_pi = -3.1415926535;
960
961 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
962 int r;
963 struct r600_bc_alu alu;
964
965 r = tgsi_split_constant(ctx, r600_src);
966 if (r)
967 return r;
968 r = tgsi_split_literal_constant(ctx, r600_src);
969 if (r)
970 return r;
971
972 memset(&alu, 0, sizeof(struct r600_bc_alu));
973 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
974 alu.is_op3 = 1;
975
976 alu.dst.chan = 0;
977 alu.dst.sel = ctx->temp_reg;
978 alu.dst.write = 1;
979
980 alu.src[0] = r600_src[0];
981 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
982
983 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
984 alu.src[1].chan = 0;
985 alu.src[1].value = (uint32_t *)&half_inv_pi;
986 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
987 alu.src[2].chan = 0;
988 alu.last = 1;
989 r = r600_bc_add_alu(ctx->bc, &alu);
990 if (r)
991 return r;
992
993 memset(&alu, 0, sizeof(struct r600_bc_alu));
994 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
995
996 alu.dst.chan = 0;
997 alu.dst.sel = ctx->temp_reg;
998 alu.dst.write = 1;
999
1000 alu.src[0].sel = ctx->temp_reg;
1001 alu.src[0].chan = 0;
1002 alu.last = 1;
1003 r = r600_bc_add_alu(ctx->bc, &alu);
1004 if (r)
1005 return r;
1006
1007 memset(&alu, 0, sizeof(struct r600_bc_alu));
1008 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1009 alu.is_op3 = 1;
1010
1011 alu.dst.chan = 0;
1012 alu.dst.sel = ctx->temp_reg;
1013 alu.dst.write = 1;
1014
1015 alu.src[0].sel = ctx->temp_reg;
1016 alu.src[0].chan = 0;
1017
1018 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1019 alu.src[1].chan = 0;
1020 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1021 alu.src[2].chan = 0;
1022
1023 if (ctx->bc->chiprev == CHIPREV_R600) {
1024 alu.src[1].value = (uint32_t *)&double_pi;
1025 alu.src[2].value = (uint32_t *)&neg_pi;
1026 } else {
1027 alu.src[1].sel = V_SQ_ALU_SRC_1;
1028 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1029 alu.src[2].neg = 1;
1030 }
1031
1032 alu.last = 1;
1033 r = r600_bc_add_alu(ctx->bc, &alu);
1034 if (r)
1035 return r;
1036 return 0;
1037 }
1038
1039 static int tgsi_trig(struct r600_shader_ctx *ctx)
1040 {
1041 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1042 struct r600_bc_alu_src r600_src[3];
1043 struct r600_bc_alu alu;
1044 int i, r;
1045 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1046
1047 r = tgsi_setup_trig(ctx, r600_src);
1048 if (r)
1049 return r;
1050
1051 memset(&alu, 0, sizeof(struct r600_bc_alu));
1052 alu.inst = ctx->inst_info->r600_opcode;
1053 alu.dst.chan = 0;
1054 alu.dst.sel = ctx->temp_reg;
1055 alu.dst.write = 1;
1056
1057 alu.src[0].sel = ctx->temp_reg;
1058 alu.src[0].chan = 0;
1059 alu.last = 1;
1060 r = r600_bc_add_alu(ctx->bc, &alu);
1061 if (r)
1062 return r;
1063
1064 /* replicate result */
1065 for (i = 0; i < lasti + 1; i++) {
1066 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1067 continue;
1068
1069 memset(&alu, 0, sizeof(struct r600_bc_alu));
1070 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1071
1072 alu.src[0].sel = ctx->temp_reg;
1073 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1074 if (r)
1075 return r;
1076 if (i == lasti)
1077 alu.last = 1;
1078 r = r600_bc_add_alu(ctx->bc, &alu);
1079 if (r)
1080 return r;
1081 }
1082 return 0;
1083 }
1084
1085 static int tgsi_scs(struct r600_shader_ctx *ctx)
1086 {
1087 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1088 struct r600_bc_alu_src r600_src[3];
1089 struct r600_bc_alu alu;
1090 int r;
1091
1092 /* We'll only need the trig stuff if we are going to write to the
1093 * X or Y components of the destination vector.
1094 */
1095 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1096 r = tgsi_setup_trig(ctx, r600_src);
1097 if (r)
1098 return r;
1099 }
1100
1101 /* dst.x = COS */
1102 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1103 memset(&alu, 0, sizeof(struct r600_bc_alu));
1104 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1105 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1106 if (r)
1107 return r;
1108
1109 alu.src[0].sel = ctx->temp_reg;
1110 alu.src[0].chan = 0;
1111 alu.last = 1;
1112 r = r600_bc_add_alu(ctx->bc, &alu);
1113 if (r)
1114 return r;
1115 }
1116
1117 /* dst.y = SIN */
1118 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1119 memset(&alu, 0, sizeof(struct r600_bc_alu));
1120 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1121 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1122 if (r)
1123 return r;
1124
1125 alu.src[0].sel = ctx->temp_reg;
1126 alu.src[0].chan = 0;
1127 alu.last = 1;
1128 r = r600_bc_add_alu(ctx->bc, &alu);
1129 if (r)
1130 return r;
1131 }
1132
1133 /* dst.z = 0.0; */
1134 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1135 memset(&alu, 0, sizeof(struct r600_bc_alu));
1136
1137 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1138
1139 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1140 if (r)
1141 return r;
1142
1143 alu.src[0].sel = V_SQ_ALU_SRC_0;
1144 alu.src[0].chan = 0;
1145
1146 alu.last = 1;
1147
1148 r = r600_bc_add_alu(ctx->bc, &alu);
1149 if (r)
1150 return r;
1151 }
1152
1153 /* dst.w = 1.0; */
1154 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1155 memset(&alu, 0, sizeof(struct r600_bc_alu));
1156
1157 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1158
1159 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1160 if (r)
1161 return r;
1162
1163 alu.src[0].sel = V_SQ_ALU_SRC_1;
1164 alu.src[0].chan = 0;
1165
1166 alu.last = 1;
1167
1168 r = r600_bc_add_alu(ctx->bc, &alu);
1169 if (r)
1170 return r;
1171 }
1172
1173 return 0;
1174 }
1175
1176 static int tgsi_kill(struct r600_shader_ctx *ctx)
1177 {
1178 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1179 struct r600_bc_alu alu;
1180 int i, r;
1181
1182 for (i = 0; i < 4; i++) {
1183 memset(&alu, 0, sizeof(struct r600_bc_alu));
1184 alu.inst = ctx->inst_info->r600_opcode;
1185
1186 alu.dst.chan = i;
1187
1188 alu.src[0].sel = V_SQ_ALU_SRC_0;
1189
1190 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1191 alu.src[1].sel = V_SQ_ALU_SRC_1;
1192 alu.src[1].neg = 1;
1193 } else {
1194 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1195 if (r)
1196 return r;
1197 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1198 }
1199 if (i == 3) {
1200 alu.last = 1;
1201 }
1202 r = r600_bc_add_alu(ctx->bc, &alu);
1203 if (r)
1204 return r;
1205 }
1206
1207 /* kill must be last in ALU */
1208 ctx->bc->force_add_cf = 1;
1209 ctx->shader->uses_kill = TRUE;
1210 return 0;
1211 }
1212
1213 static int tgsi_lit(struct r600_shader_ctx *ctx)
1214 {
1215 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1216 struct r600_bc_alu alu;
1217 struct r600_bc_alu_src r600_src[3];
1218 int r;
1219
1220 r = tgsi_split_constant(ctx, r600_src);
1221 if (r)
1222 return r;
1223 r = tgsi_split_literal_constant(ctx, r600_src);
1224 if (r)
1225 return r;
1226
1227 /* dst.x, <- 1.0 */
1228 memset(&alu, 0, sizeof(struct r600_bc_alu));
1229 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1230 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1231 alu.src[0].chan = 0;
1232 r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1233 if (r)
1234 return r;
1235 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1236 r = r600_bc_add_alu(ctx->bc, &alu);
1237 if (r)
1238 return r;
1239
1240 /* dst.y = max(src.x, 0.0) */
1241 memset(&alu, 0, sizeof(struct r600_bc_alu));
1242 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1243 alu.src[0] = r600_src[0];
1244 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1245 alu.src[1].chan = 0;
1246 r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1247 if (r)
1248 return r;
1249 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1250 r = r600_bc_add_alu(ctx->bc, &alu);
1251 if (r)
1252 return r;
1253
1254 /* dst.w, <- 1.0 */
1255 memset(&alu, 0, sizeof(struct r600_bc_alu));
1256 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1257 alu.src[0].sel = V_SQ_ALU_SRC_1;
1258 alu.src[0].chan = 0;
1259 r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1260 if (r)
1261 return r;
1262 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1263 alu.last = 1;
1264 r = r600_bc_add_alu(ctx->bc, &alu);
1265 if (r)
1266 return r;
1267
1268 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1269 {
1270 int chan;
1271 int sel;
1272
1273 /* dst.z = log(src.y) */
1274 memset(&alu, 0, sizeof(struct r600_bc_alu));
1275 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1276 alu.src[0] = r600_src[0];
1277 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
1278 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1279 if (r)
1280 return r;
1281 alu.last = 1;
1282 r = r600_bc_add_alu(ctx->bc, &alu);
1283 if (r)
1284 return r;
1285
1286 chan = alu.dst.chan;
1287 sel = alu.dst.sel;
1288
1289 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1290 memset(&alu, 0, sizeof(struct r600_bc_alu));
1291 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1292 alu.src[0] = r600_src[0];
1293 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1294 alu.src[1].sel = sel;
1295 alu.src[1].chan = chan;
1296
1297 alu.src[2] = r600_src[0];
1298 alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
1299 alu.dst.sel = ctx->temp_reg;
1300 alu.dst.chan = 0;
1301 alu.dst.write = 1;
1302 alu.is_op3 = 1;
1303 alu.last = 1;
1304 r = r600_bc_add_alu(ctx->bc, &alu);
1305 if (r)
1306 return r;
1307
1308 /* dst.z = exp(tmp.x) */
1309 memset(&alu, 0, sizeof(struct r600_bc_alu));
1310 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1311 alu.src[0].sel = ctx->temp_reg;
1312 alu.src[0].chan = 0;
1313 r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1314 if (r)
1315 return r;
1316 alu.last = 1;
1317 r = r600_bc_add_alu(ctx->bc, &alu);
1318 if (r)
1319 return r;
1320 }
1321 return 0;
1322 }
1323
1324 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1325 {
1326 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1327 struct r600_bc_alu alu;
1328 int i, r;
1329
1330 memset(&alu, 0, sizeof(struct r600_bc_alu));
1331
1332 /* FIXME:
1333 * For state trackers other than OpenGL, we'll want to use
1334 * _RECIPSQRT_IEEE instead.
1335 */
1336 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1337
1338 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1339 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1340 if (r)
1341 return r;
1342 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1343 alu.src[i].abs = 1;
1344 }
1345 alu.dst.sel = ctx->temp_reg;
1346 alu.dst.write = 1;
1347 alu.last = 1;
1348 r = r600_bc_add_alu(ctx->bc, &alu);
1349 if (r)
1350 return r;
1351 /* replicate result */
1352 return tgsi_helper_tempx_replicate(ctx);
1353 }
1354
1355 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1356 {
1357 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1358 struct r600_bc_alu alu;
1359 int i, r;
1360
1361 for (i = 0; i < 4; i++) {
1362 memset(&alu, 0, sizeof(struct r600_bc_alu));
1363 alu.src[0].sel = ctx->temp_reg;
1364 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1365 alu.dst.chan = i;
1366 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1367 if (r)
1368 return r;
1369 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1370 if (i == 3)
1371 alu.last = 1;
1372 r = r600_bc_add_alu(ctx->bc, &alu);
1373 if (r)
1374 return r;
1375 }
1376 return 0;
1377 }
1378
1379 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1380 {
1381 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1382 struct r600_bc_alu alu;
1383 int i, r;
1384
1385 memset(&alu, 0, sizeof(struct r600_bc_alu));
1386 alu.inst = ctx->inst_info->r600_opcode;
1387 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1388 r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
1389 if (r)
1390 return r;
1391 alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
1392 }
1393 alu.dst.sel = ctx->temp_reg;
1394 alu.dst.write = 1;
1395 alu.last = 1;
1396 r = r600_bc_add_alu(ctx->bc, &alu);
1397 if (r)
1398 return r;
1399 /* replicate result */
1400 return tgsi_helper_tempx_replicate(ctx);
1401 }
1402
1403 static int tgsi_pow(struct r600_shader_ctx *ctx)
1404 {
1405 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1406 struct r600_bc_alu alu;
1407 int r;
1408
1409 /* LOG2(a) */
1410 memset(&alu, 0, sizeof(struct r600_bc_alu));
1411 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1412 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1413 if (r)
1414 return r;
1415 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
1416 alu.dst.sel = ctx->temp_reg;
1417 alu.dst.write = 1;
1418 alu.last = 1;
1419 r = r600_bc_add_alu(ctx->bc, &alu);
1420 if (r)
1421 return r;
1422 /* b * LOG2(a) */
1423 memset(&alu, 0, sizeof(struct r600_bc_alu));
1424 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1425 r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
1426 if (r)
1427 return r;
1428 alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
1429 alu.src[1].sel = ctx->temp_reg;
1430 alu.dst.sel = ctx->temp_reg;
1431 alu.dst.write = 1;
1432 alu.last = 1;
1433 r = r600_bc_add_alu(ctx->bc, &alu);
1434 if (r)
1435 return r;
1436 /* POW(a,b) = EXP2(b * LOG2(a))*/
1437 memset(&alu, 0, sizeof(struct r600_bc_alu));
1438 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1439 alu.src[0].sel = ctx->temp_reg;
1440 alu.dst.sel = ctx->temp_reg;
1441 alu.dst.write = 1;
1442 alu.last = 1;
1443 r = r600_bc_add_alu(ctx->bc, &alu);
1444 if (r)
1445 return r;
1446 return tgsi_helper_tempx_replicate(ctx);
1447 }
1448
1449 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1450 {
1451 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1452 struct r600_bc_alu alu;
1453 struct r600_bc_alu_src r600_src[3];
1454 int i, r;
1455
1456 r = tgsi_split_constant(ctx, r600_src);
1457 if (r)
1458 return r;
1459 r = tgsi_split_literal_constant(ctx, r600_src);
1460 if (r)
1461 return r;
1462
1463 /* tmp = (src > 0 ? 1 : src) */
1464 for (i = 0; i < 4; i++) {
1465 memset(&alu, 0, sizeof(struct r600_bc_alu));
1466 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1467 alu.is_op3 = 1;
1468
1469 alu.dst.sel = ctx->temp_reg;
1470 alu.dst.chan = i;
1471
1472 alu.src[0] = r600_src[0];
1473 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1474
1475 alu.src[1].sel = V_SQ_ALU_SRC_1;
1476
1477 alu.src[2] = r600_src[0];
1478 alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
1479 if (i == 3)
1480 alu.last = 1;
1481 r = r600_bc_add_alu(ctx->bc, &alu);
1482 if (r)
1483 return r;
1484 }
1485
1486 /* dst = (-tmp > 0 ? -1 : tmp) */
1487 for (i = 0; i < 4; i++) {
1488 memset(&alu, 0, sizeof(struct r600_bc_alu));
1489 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1490 alu.is_op3 = 1;
1491 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1492 if (r)
1493 return r;
1494
1495 alu.src[0].sel = ctx->temp_reg;
1496 alu.src[0].chan = i;
1497 alu.src[0].neg = 1;
1498
1499 alu.src[1].sel = V_SQ_ALU_SRC_1;
1500 alu.src[1].neg = 1;
1501
1502 alu.src[2].sel = ctx->temp_reg;
1503 alu.src[2].chan = i;
1504
1505 if (i == 3)
1506 alu.last = 1;
1507 r = r600_bc_add_alu(ctx->bc, &alu);
1508 if (r)
1509 return r;
1510 }
1511 return 0;
1512 }
1513
1514 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1515 {
1516 struct r600_bc_alu alu;
1517 int i, r;
1518
1519 for (i = 0; i < 4; i++) {
1520 memset(&alu, 0, sizeof(struct r600_bc_alu));
1521 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1522 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1523 alu.dst.chan = i;
1524 } else {
1525 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1526 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1527 if (r)
1528 return r;
1529 alu.src[0].sel = ctx->temp_reg;
1530 alu.src[0].chan = i;
1531 }
1532 if (i == 3) {
1533 alu.last = 1;
1534 }
1535 r = r600_bc_add_alu(ctx->bc, &alu);
1536 if (r)
1537 return r;
1538 }
1539 return 0;
1540 }
1541
1542 static int tgsi_op3(struct r600_shader_ctx *ctx)
1543 {
1544 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1545 struct r600_bc_alu_src r600_src[3];
1546 struct r600_bc_alu alu;
1547 int i, j, r;
1548 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1549
1550 r = tgsi_split_constant(ctx, r600_src);
1551 if (r)
1552 return r;
1553 r = tgsi_split_literal_constant(ctx, r600_src);
1554 if (r)
1555 return r;
1556 for (i = 0; i < lasti + 1; i++) {
1557 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1558 continue;
1559
1560 memset(&alu, 0, sizeof(struct r600_bc_alu));
1561 alu.inst = ctx->inst_info->r600_opcode;
1562 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1563 alu.src[j] = r600_src[j];
1564 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1565 }
1566
1567 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1568 if (r)
1569 return r;
1570
1571 alu.dst.chan = i;
1572 alu.dst.write = 1;
1573 alu.is_op3 = 1;
1574 if (i == lasti) {
1575 alu.last = 1;
1576 }
1577 r = r600_bc_add_alu(ctx->bc, &alu);
1578 if (r)
1579 return r;
1580 }
1581 return 0;
1582 }
1583
1584 static int tgsi_dp(struct r600_shader_ctx *ctx)
1585 {
1586 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1587 struct r600_bc_alu_src r600_src[3];
1588 struct r600_bc_alu alu;
1589 int i, j, r;
1590
1591 r = tgsi_split_constant(ctx, r600_src);
1592 if (r)
1593 return r;
1594 r = tgsi_split_literal_constant(ctx, r600_src);
1595 if (r)
1596 return r;
1597 for (i = 0; i < 4; i++) {
1598 memset(&alu, 0, sizeof(struct r600_bc_alu));
1599 alu.inst = ctx->inst_info->r600_opcode;
1600 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1601 alu.src[j] = r600_src[j];
1602 alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
1603 }
1604
1605 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1606 if (r)
1607 return r;
1608
1609 alu.dst.chan = i;
1610 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1611 /* handle some special cases */
1612 switch (ctx->inst_info->tgsi_opcode) {
1613 case TGSI_OPCODE_DP2:
1614 if (i > 1) {
1615 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1616 alu.src[0].chan = alu.src[1].chan = 0;
1617 }
1618 break;
1619 case TGSI_OPCODE_DP3:
1620 if (i > 2) {
1621 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1622 alu.src[0].chan = alu.src[1].chan = 0;
1623 }
1624 break;
1625 case TGSI_OPCODE_DPH:
1626 if (i == 3) {
1627 alu.src[0].sel = V_SQ_ALU_SRC_1;
1628 alu.src[0].chan = 0;
1629 alu.src[0].neg = 0;
1630 }
1631 break;
1632 default:
1633 break;
1634 }
1635 if (i == 3) {
1636 alu.last = 1;
1637 }
1638 r = r600_bc_add_alu(ctx->bc, &alu);
1639 if (r)
1640 return r;
1641 }
1642 return 0;
1643 }
1644
1645 static int tgsi_tex(struct r600_shader_ctx *ctx)
1646 {
1647 static float one_point_five = 1.5f;
1648 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1649 struct r600_bc_tex tex;
1650 struct r600_bc_alu alu;
1651 unsigned src_gpr;
1652 int r, i;
1653 int opcode;
1654 boolean src_not_temp =
1655 inst->Src[0].Register.File != TGSI_FILE_TEMPORARY &&
1656 inst->Src[0].Register.File != TGSI_FILE_INPUT;
1657
1658 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1659
1660 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1661 /* Add perspective divide */
1662 memset(&alu, 0, sizeof(struct r600_bc_alu));
1663 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1664 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1665 if (r)
1666 return r;
1667
1668 alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
1669 alu.dst.sel = ctx->temp_reg;
1670 alu.dst.chan = 3;
1671 alu.last = 1;
1672 alu.dst.write = 1;
1673 r = r600_bc_add_alu(ctx->bc, &alu);
1674 if (r)
1675 return r;
1676
1677 for (i = 0; i < 3; i++) {
1678 memset(&alu, 0, sizeof(struct r600_bc_alu));
1679 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1680 alu.src[0].sel = ctx->temp_reg;
1681 alu.src[0].chan = 3;
1682 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1683 if (r)
1684 return r;
1685 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1686 alu.dst.sel = ctx->temp_reg;
1687 alu.dst.chan = i;
1688 alu.dst.write = 1;
1689 r = r600_bc_add_alu(ctx->bc, &alu);
1690 if (r)
1691 return r;
1692 }
1693 memset(&alu, 0, sizeof(struct r600_bc_alu));
1694 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1695 alu.src[0].sel = V_SQ_ALU_SRC_1;
1696 alu.src[0].chan = 0;
1697 alu.dst.sel = ctx->temp_reg;
1698 alu.dst.chan = 3;
1699 alu.last = 1;
1700 alu.dst.write = 1;
1701 r = r600_bc_add_alu(ctx->bc, &alu);
1702 if (r)
1703 return r;
1704 src_not_temp = FALSE;
1705 src_gpr = ctx->temp_reg;
1706 }
1707
1708 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1709 int src_chan, src2_chan;
1710
1711 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1712 for (i = 0; i < 4; i++) {
1713 memset(&alu, 0, sizeof(struct r600_bc_alu));
1714 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1715 switch (i) {
1716 case 0:
1717 src_chan = 2;
1718 src2_chan = 1;
1719 break;
1720 case 1:
1721 src_chan = 2;
1722 src2_chan = 0;
1723 break;
1724 case 2:
1725 src_chan = 0;
1726 src2_chan = 2;
1727 break;
1728 case 3:
1729 src_chan = 1;
1730 src2_chan = 2;
1731 break;
1732 default:
1733 assert(0);
1734 src_chan = 0;
1735 src2_chan = 0;
1736 break;
1737 }
1738 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
1739 if (r)
1740 return r;
1741 alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
1742 r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
1743 if (r)
1744 return r;
1745 alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
1746 alu.dst.sel = ctx->temp_reg;
1747 alu.dst.chan = i;
1748 if (i == 3)
1749 alu.last = 1;
1750 alu.dst.write = 1;
1751 r = r600_bc_add_alu(ctx->bc, &alu);
1752 if (r)
1753 return r;
1754 }
1755
1756 /* tmp1.z = RCP_e(|tmp1.z|) */
1757 memset(&alu, 0, sizeof(struct r600_bc_alu));
1758 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1759 alu.src[0].sel = ctx->temp_reg;
1760 alu.src[0].chan = 2;
1761 alu.src[0].abs = 1;
1762 alu.dst.sel = ctx->temp_reg;
1763 alu.dst.chan = 2;
1764 alu.dst.write = 1;
1765 alu.last = 1;
1766 r = r600_bc_add_alu(ctx->bc, &alu);
1767 if (r)
1768 return r;
1769
1770 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1771 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1772 * muladd has no writemask, have to use another temp
1773 */
1774 memset(&alu, 0, sizeof(struct r600_bc_alu));
1775 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1776 alu.is_op3 = 1;
1777
1778 alu.src[0].sel = ctx->temp_reg;
1779 alu.src[0].chan = 0;
1780 alu.src[1].sel = ctx->temp_reg;
1781 alu.src[1].chan = 2;
1782
1783 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1784 alu.src[2].chan = 0;
1785 alu.src[2].value = (u32*)&one_point_five;
1786
1787 alu.dst.sel = ctx->temp_reg;
1788 alu.dst.chan = 0;
1789 alu.dst.write = 1;
1790
1791 r = r600_bc_add_alu(ctx->bc, &alu);
1792 if (r)
1793 return r;
1794
1795 memset(&alu, 0, sizeof(struct r600_bc_alu));
1796 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1797 alu.is_op3 = 1;
1798
1799 alu.src[0].sel = ctx->temp_reg;
1800 alu.src[0].chan = 1;
1801 alu.src[1].sel = ctx->temp_reg;
1802 alu.src[1].chan = 2;
1803
1804 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1805 alu.src[2].chan = 0;
1806 alu.src[2].value = (u32*)&one_point_five;
1807
1808 alu.dst.sel = ctx->temp_reg;
1809 alu.dst.chan = 1;
1810 alu.dst.write = 1;
1811
1812 alu.last = 1;
1813 r = r600_bc_add_alu(ctx->bc, &alu);
1814 if (r)
1815 return r;
1816
1817 src_not_temp = FALSE;
1818 src_gpr = ctx->temp_reg;
1819 }
1820
1821 if (src_not_temp) {
1822 for (i = 0; i < 4; i++) {
1823 memset(&alu, 0, sizeof(struct r600_bc_alu));
1824 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1825 alu.src[0].sel = src_gpr;
1826 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1827 alu.dst.sel = ctx->temp_reg;
1828 alu.dst.chan = i;
1829 if (i == 3)
1830 alu.last = 1;
1831 alu.dst.write = 1;
1832 r = r600_bc_add_alu(ctx->bc, &alu);
1833 if (r)
1834 return r;
1835 }
1836 src_gpr = ctx->temp_reg;
1837 }
1838
1839 opcode = ctx->inst_info->r600_opcode;
1840 if (opcode == SQ_TEX_INST_SAMPLE &&
1841 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1842 opcode = SQ_TEX_INST_SAMPLE_C;
1843
1844 memset(&tex, 0, sizeof(struct r600_bc_tex));
1845 tex.inst = opcode;
1846 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1847 tex.resource_id = tex.sampler_id;
1848 tex.src_gpr = src_gpr;
1849 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1850 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1851 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1852 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1853 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1854 tex.src_sel_x = 0;
1855 tex.src_sel_y = 1;
1856 tex.src_sel_z = 2;
1857 tex.src_sel_w = 3;
1858
1859 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1860 tex.src_sel_x = 1;
1861 tex.src_sel_y = 0;
1862 tex.src_sel_z = 3;
1863 tex.src_sel_w = 1;
1864 }
1865
1866 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1867 tex.coord_type_x = 1;
1868 tex.coord_type_y = 1;
1869 tex.coord_type_z = 1;
1870 tex.coord_type_w = 1;
1871 }
1872
1873 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1874 tex.src_sel_w = 2;
1875
1876 r = r600_bc_add_tex(ctx->bc, &tex);
1877 if (r)
1878 return r;
1879
1880 /* add shadow ambient support - gallium doesn't do it yet */
1881 return 0;
1882 }
1883
1884 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1885 {
1886 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1887 struct r600_bc_alu_src r600_src[3];
1888 struct r600_bc_alu alu;
1889 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1890 unsigned i;
1891 int r;
1892
1893 r = tgsi_split_constant(ctx, r600_src);
1894 if (r)
1895 return r;
1896 r = tgsi_split_literal_constant(ctx, r600_src);
1897 if (r)
1898 return r;
1899
1900 /* optimize if it's just an equal balance */
1901 if(r600_src[0].sel == V_SQ_ALU_SRC_0_5) {
1902 for (i = 0; i < lasti + 1; i++) {
1903 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1904 continue;
1905
1906 memset(&alu, 0, sizeof(struct r600_bc_alu));
1907 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1908 alu.src[0] = r600_src[1];
1909 alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
1910 alu.src[1] = r600_src[2];
1911 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1912 alu.omod = 3;
1913 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1914 if (r)
1915 return r;
1916
1917 alu.dst.chan = i;
1918 if (i == lasti) {
1919 alu.last = 1;
1920 }
1921 r = r600_bc_add_alu(ctx->bc, &alu);
1922 if (r)
1923 return r;
1924 }
1925 return 0;
1926 }
1927
1928 /* 1 - src0 */
1929 for (i = 0; i < lasti + 1; i++) {
1930 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1931 continue;
1932
1933 memset(&alu, 0, sizeof(struct r600_bc_alu));
1934 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1935 alu.src[0].sel = V_SQ_ALU_SRC_1;
1936 alu.src[0].chan = 0;
1937 alu.src[1] = r600_src[0];
1938 alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
1939 alu.src[1].neg = 1;
1940 alu.dst.sel = ctx->temp_reg;
1941 alu.dst.chan = i;
1942 if (i == lasti) {
1943 alu.last = 1;
1944 }
1945 alu.dst.write = 1;
1946 r = r600_bc_add_alu(ctx->bc, &alu);
1947 if (r)
1948 return r;
1949 }
1950
1951 /* (1 - src0) * src2 */
1952 for (i = 0; i < lasti + 1; i++) {
1953 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1954 continue;
1955
1956 memset(&alu, 0, sizeof(struct r600_bc_alu));
1957 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1958 alu.src[0].sel = ctx->temp_reg;
1959 alu.src[0].chan = i;
1960 alu.src[1] = r600_src[2];
1961 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
1962 alu.dst.sel = ctx->temp_reg;
1963 alu.dst.chan = i;
1964 if (i == lasti) {
1965 alu.last = 1;
1966 }
1967 alu.dst.write = 1;
1968 r = r600_bc_add_alu(ctx->bc, &alu);
1969 if (r)
1970 return r;
1971 }
1972
1973 /* src0 * src1 + (1 - src0) * src2 */
1974 for (i = 0; i < lasti + 1; i++) {
1975 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1976 continue;
1977
1978 memset(&alu, 0, sizeof(struct r600_bc_alu));
1979 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1980 alu.is_op3 = 1;
1981 alu.src[0] = r600_src[0];
1982 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
1983 alu.src[1] = r600_src[1];
1984 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
1985 alu.src[2].sel = ctx->temp_reg;
1986 alu.src[2].chan = i;
1987
1988 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1989 if (r)
1990 return r;
1991
1992 alu.dst.chan = i;
1993 if (i == lasti) {
1994 alu.last = 1;
1995 }
1996 r = r600_bc_add_alu(ctx->bc, &alu);
1997 if (r)
1998 return r;
1999 }
2000 return 0;
2001 }
2002
2003 static int tgsi_cmp(struct r600_shader_ctx *ctx)
2004 {
2005 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2006 struct r600_bc_alu_src r600_src[3];
2007 struct r600_bc_alu alu;
2008 int i, r;
2009 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
2010
2011 r = tgsi_split_constant(ctx, r600_src);
2012 if (r)
2013 return r;
2014 r = tgsi_split_literal_constant(ctx, r600_src);
2015 if (r)
2016 return r;
2017
2018 for (i = 0; i < lasti + 1; i++) {
2019 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
2020 continue;
2021
2022 memset(&alu, 0, sizeof(struct r600_bc_alu));
2023 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
2024 alu.src[0] = r600_src[0];
2025 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2026
2027 alu.src[1] = r600_src[2];
2028 alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
2029
2030 alu.src[2] = r600_src[1];
2031 alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
2032
2033 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2034 if (r)
2035 return r;
2036
2037 alu.dst.chan = i;
2038 alu.dst.write = 1;
2039 alu.is_op3 = 1;
2040 if (i == lasti)
2041 alu.last = 1;
2042 r = r600_bc_add_alu(ctx->bc, &alu);
2043 if (r)
2044 return r;
2045 }
2046 return 0;
2047 }
2048
2049 static int tgsi_xpd(struct r600_shader_ctx *ctx)
2050 {
2051 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2052 struct r600_bc_alu_src r600_src[3];
2053 struct r600_bc_alu alu;
2054 uint32_t use_temp = 0;
2055 int i, r;
2056
2057 if (inst->Dst[0].Register.WriteMask != 0xf)
2058 use_temp = 1;
2059
2060 r = tgsi_split_constant(ctx, r600_src);
2061 if (r)
2062 return r;
2063 r = tgsi_split_literal_constant(ctx, r600_src);
2064 if (r)
2065 return r;
2066
2067 for (i = 0; i < 4; i++) {
2068 memset(&alu, 0, sizeof(struct r600_bc_alu));
2069 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2070
2071 alu.src[0] = r600_src[0];
2072 switch (i) {
2073 case 0:
2074 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2075 break;
2076 case 1:
2077 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2078 break;
2079 case 2:
2080 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2081 break;
2082 case 3:
2083 alu.src[0].sel = V_SQ_ALU_SRC_0;
2084 alu.src[0].chan = i;
2085 }
2086
2087 alu.src[1] = r600_src[1];
2088 switch (i) {
2089 case 0:
2090 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2091 break;
2092 case 1:
2093 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2094 break;
2095 case 2:
2096 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2097 break;
2098 case 3:
2099 alu.src[1].sel = V_SQ_ALU_SRC_0;
2100 alu.src[1].chan = i;
2101 }
2102
2103 alu.dst.sel = ctx->temp_reg;
2104 alu.dst.chan = i;
2105 alu.dst.write = 1;
2106
2107 if (i == 3)
2108 alu.last = 1;
2109 r = r600_bc_add_alu(ctx->bc, &alu);
2110 if (r)
2111 return r;
2112 }
2113
2114 for (i = 0; i < 4; i++) {
2115 memset(&alu, 0, sizeof(struct r600_bc_alu));
2116 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2117
2118 alu.src[0] = r600_src[0];
2119 switch (i) {
2120 case 0:
2121 alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
2122 break;
2123 case 1:
2124 alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
2125 break;
2126 case 2:
2127 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2128 break;
2129 case 3:
2130 alu.src[0].sel = V_SQ_ALU_SRC_0;
2131 alu.src[0].chan = i;
2132 }
2133
2134 alu.src[1] = r600_src[1];
2135 switch (i) {
2136 case 0:
2137 alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
2138 break;
2139 case 1:
2140 alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
2141 break;
2142 case 2:
2143 alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
2144 break;
2145 case 3:
2146 alu.src[1].sel = V_SQ_ALU_SRC_0;
2147 alu.src[1].chan = i;
2148 }
2149
2150 alu.src[2].sel = ctx->temp_reg;
2151 alu.src[2].neg = 1;
2152 alu.src[2].chan = i;
2153
2154 if (use_temp)
2155 alu.dst.sel = ctx->temp_reg;
2156 else {
2157 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2158 if (r)
2159 return r;
2160 }
2161 alu.dst.chan = i;
2162 alu.dst.write = 1;
2163 alu.is_op3 = 1;
2164 if (i == 3)
2165 alu.last = 1;
2166 r = r600_bc_add_alu(ctx->bc, &alu);
2167 if (r)
2168 return r;
2169 }
2170 if (use_temp)
2171 return tgsi_helper_copy(ctx, inst);
2172 return 0;
2173 }
2174
2175 static int tgsi_exp(struct r600_shader_ctx *ctx)
2176 {
2177 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2178 struct r600_bc_alu_src r600_src[3] = { { 0 } };
2179 struct r600_bc_alu alu;
2180 int r;
2181
2182 /* result.x = 2^floor(src); */
2183 if (inst->Dst[0].Register.WriteMask & 1) {
2184 memset(&alu, 0, sizeof(struct r600_bc_alu));
2185
2186 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2187 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2188 if (r)
2189 return r;
2190
2191 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2192
2193 alu.dst.sel = ctx->temp_reg;
2194 alu.dst.chan = 0;
2195 alu.dst.write = 1;
2196 alu.last = 1;
2197 r = r600_bc_add_alu(ctx->bc, &alu);
2198 if (r)
2199 return r;
2200
2201 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2202 alu.src[0].sel = ctx->temp_reg;
2203 alu.src[0].chan = 0;
2204
2205 alu.dst.sel = ctx->temp_reg;
2206 alu.dst.chan = 0;
2207 alu.dst.write = 1;
2208 alu.last = 1;
2209 r = r600_bc_add_alu(ctx->bc, &alu);
2210 if (r)
2211 return r;
2212 }
2213
2214 /* result.y = tmp - floor(tmp); */
2215 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2216 memset(&alu, 0, sizeof(struct r600_bc_alu));
2217
2218 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2219 alu.src[0] = r600_src[0];
2220 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2221 if (r)
2222 return r;
2223 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2224
2225 alu.dst.sel = ctx->temp_reg;
2226 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2227 // if (r)
2228 // return r;
2229 alu.dst.write = 1;
2230 alu.dst.chan = 1;
2231
2232 alu.last = 1;
2233
2234 r = r600_bc_add_alu(ctx->bc, &alu);
2235 if (r)
2236 return r;
2237 }
2238
2239 /* result.z = RoughApprox2ToX(tmp);*/
2240 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2241 memset(&alu, 0, sizeof(struct r600_bc_alu));
2242 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2243 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2244 if (r)
2245 return r;
2246 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2247
2248 alu.dst.sel = ctx->temp_reg;
2249 alu.dst.write = 1;
2250 alu.dst.chan = 2;
2251
2252 alu.last = 1;
2253
2254 r = r600_bc_add_alu(ctx->bc, &alu);
2255 if (r)
2256 return r;
2257 }
2258
2259 /* result.w = 1.0;*/
2260 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2261 memset(&alu, 0, sizeof(struct r600_bc_alu));
2262
2263 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2264 alu.src[0].sel = V_SQ_ALU_SRC_1;
2265 alu.src[0].chan = 0;
2266
2267 alu.dst.sel = ctx->temp_reg;
2268 alu.dst.chan = 3;
2269 alu.dst.write = 1;
2270 alu.last = 1;
2271 r = r600_bc_add_alu(ctx->bc, &alu);
2272 if (r)
2273 return r;
2274 }
2275 return tgsi_helper_copy(ctx, inst);
2276 }
2277
2278 static int tgsi_log(struct r600_shader_ctx *ctx)
2279 {
2280 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2281 struct r600_bc_alu alu;
2282 int r;
2283
2284 /* result.x = floor(log2(src)); */
2285 if (inst->Dst[0].Register.WriteMask & 1) {
2286 memset(&alu, 0, sizeof(struct r600_bc_alu));
2287
2288 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2289 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2290 if (r)
2291 return r;
2292
2293 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2294
2295 alu.dst.sel = ctx->temp_reg;
2296 alu.dst.chan = 0;
2297 alu.dst.write = 1;
2298 alu.last = 1;
2299 r = r600_bc_add_alu(ctx->bc, &alu);
2300 if (r)
2301 return r;
2302
2303 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2304 alu.src[0].sel = ctx->temp_reg;
2305 alu.src[0].chan = 0;
2306
2307 alu.dst.sel = ctx->temp_reg;
2308 alu.dst.chan = 0;
2309 alu.dst.write = 1;
2310 alu.last = 1;
2311
2312 r = r600_bc_add_alu(ctx->bc, &alu);
2313 if (r)
2314 return r;
2315 }
2316
2317 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2318 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2319 memset(&alu, 0, sizeof(struct r600_bc_alu));
2320
2321 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2322 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2323 if (r)
2324 return r;
2325
2326 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2327
2328 alu.dst.sel = ctx->temp_reg;
2329 alu.dst.chan = 1;
2330 alu.dst.write = 1;
2331 alu.last = 1;
2332
2333 r = r600_bc_add_alu(ctx->bc, &alu);
2334 if (r)
2335 return r;
2336
2337 memset(&alu, 0, sizeof(struct r600_bc_alu));
2338
2339 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2340 alu.src[0].sel = ctx->temp_reg;
2341 alu.src[0].chan = 1;
2342
2343 alu.dst.sel = ctx->temp_reg;
2344 alu.dst.chan = 1;
2345 alu.dst.write = 1;
2346 alu.last = 1;
2347
2348 r = r600_bc_add_alu(ctx->bc, &alu);
2349 if (r)
2350 return r;
2351
2352 memset(&alu, 0, sizeof(struct r600_bc_alu));
2353
2354 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2355 alu.src[0].sel = ctx->temp_reg;
2356 alu.src[0].chan = 1;
2357
2358 alu.dst.sel = ctx->temp_reg;
2359 alu.dst.chan = 1;
2360 alu.dst.write = 1;
2361 alu.last = 1;
2362
2363 r = r600_bc_add_alu(ctx->bc, &alu);
2364 if (r)
2365 return r;
2366
2367 memset(&alu, 0, sizeof(struct r600_bc_alu));
2368
2369 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2370 alu.src[0].sel = ctx->temp_reg;
2371 alu.src[0].chan = 1;
2372
2373 alu.dst.sel = ctx->temp_reg;
2374 alu.dst.chan = 1;
2375 alu.dst.write = 1;
2376 alu.last = 1;
2377
2378 r = r600_bc_add_alu(ctx->bc, &alu);
2379 if (r)
2380 return r;
2381
2382 memset(&alu, 0, sizeof(struct r600_bc_alu));
2383
2384 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2385
2386 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2387 if (r)
2388 return r;
2389
2390 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2391
2392 alu.src[1].sel = ctx->temp_reg;
2393 alu.src[1].chan = 1;
2394
2395 alu.dst.sel = ctx->temp_reg;
2396 alu.dst.chan = 1;
2397 alu.dst.write = 1;
2398 alu.last = 1;
2399
2400 r = r600_bc_add_alu(ctx->bc, &alu);
2401 if (r)
2402 return r;
2403 }
2404
2405 /* result.z = log2(src);*/
2406 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2407 memset(&alu, 0, sizeof(struct r600_bc_alu));
2408
2409 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2410 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2411 if (r)
2412 return r;
2413
2414 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2415
2416 alu.dst.sel = ctx->temp_reg;
2417 alu.dst.write = 1;
2418 alu.dst.chan = 2;
2419 alu.last = 1;
2420
2421 r = r600_bc_add_alu(ctx->bc, &alu);
2422 if (r)
2423 return r;
2424 }
2425
2426 /* result.w = 1.0; */
2427 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2428 memset(&alu, 0, sizeof(struct r600_bc_alu));
2429
2430 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2431 alu.src[0].sel = V_SQ_ALU_SRC_1;
2432 alu.src[0].chan = 0;
2433
2434 alu.dst.sel = ctx->temp_reg;
2435 alu.dst.chan = 3;
2436 alu.dst.write = 1;
2437 alu.last = 1;
2438
2439 r = r600_bc_add_alu(ctx->bc, &alu);
2440 if (r)
2441 return r;
2442 }
2443
2444 return tgsi_helper_copy(ctx, inst);
2445 }
2446
2447 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2448 {
2449 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2450 struct r600_bc_alu alu;
2451 int r;
2452 memset(&alu, 0, sizeof(struct r600_bc_alu));
2453
2454 switch (inst->Instruction.Opcode) {
2455 case TGSI_OPCODE_ARL:
2456 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2457 break;
2458 case TGSI_OPCODE_ARR:
2459 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2460 break;
2461 default:
2462 assert(0);
2463 return -1;
2464 }
2465
2466 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2467 if (r)
2468 return r;
2469 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2470 alu.last = 1;
2471 alu.dst.chan = 0;
2472 alu.dst.sel = ctx->temp_reg;
2473 alu.dst.write = 1;
2474 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2475 if (r)
2476 return r;
2477 memset(&alu, 0, sizeof(struct r600_bc_alu));
2478 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2479 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2480 if (r)
2481 return r;
2482 alu.src[0].sel = ctx->temp_reg;
2483 alu.src[0].chan = 0;
2484 alu.last = 1;
2485 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2486 if (r)
2487 return r;
2488 return 0;
2489 }
2490 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2491 {
2492 /* TODO from r600c, ar values don't persist between clauses */
2493 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2494 struct r600_bc_alu alu;
2495 int r;
2496 memset(&alu, 0, sizeof(struct r600_bc_alu));
2497
2498 switch (inst->Instruction.Opcode) {
2499 case TGSI_OPCODE_ARL:
2500 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
2501 break;
2502 case TGSI_OPCODE_ARR:
2503 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA;
2504 break;
2505 default:
2506 assert(0);
2507 return -1;
2508 }
2509
2510
2511 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2512 if (r)
2513 return r;
2514 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2515
2516 alu.last = 1;
2517
2518 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
2519 if (r)
2520 return r;
2521 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2522 return 0;
2523 }
2524
2525 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2526 {
2527 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2528 struct r600_bc_alu alu;
2529 int i, r = 0;
2530
2531 for (i = 0; i < 4; i++) {
2532 memset(&alu, 0, sizeof(struct r600_bc_alu));
2533
2534 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2535 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2536 if (r)
2537 return r;
2538
2539 if (i == 0 || i == 3) {
2540 alu.src[0].sel = V_SQ_ALU_SRC_1;
2541 } else {
2542 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2543 if (r)
2544 return r;
2545 alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
2546 }
2547
2548 if (i == 0 || i == 2) {
2549 alu.src[1].sel = V_SQ_ALU_SRC_1;
2550 } else {
2551 r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
2552 if (r)
2553 return r;
2554 alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
2555 }
2556 if (i == 3)
2557 alu.last = 1;
2558 r = r600_bc_add_alu(ctx->bc, &alu);
2559 if (r)
2560 return r;
2561 }
2562 return 0;
2563 }
2564
2565 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2566 {
2567 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2568 struct r600_bc_alu alu;
2569 int r;
2570
2571 memset(&alu, 0, sizeof(struct r600_bc_alu));
2572 alu.inst = opcode;
2573 alu.predicate = 1;
2574
2575 alu.dst.sel = ctx->temp_reg;
2576 alu.dst.write = 1;
2577 alu.dst.chan = 0;
2578
2579 r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
2580 if (r)
2581 return r;
2582 alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
2583 alu.src[1].sel = V_SQ_ALU_SRC_0;
2584 alu.src[1].chan = 0;
2585
2586 alu.last = 1;
2587
2588 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2589 if (r)
2590 return r;
2591 return 0;
2592 }
2593
2594 static int pops(struct r600_shader_ctx *ctx, int pops)
2595 {
2596 int alu_pop = 3;
2597 if (ctx->bc->cf_last) {
2598 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) << 3)
2599 alu_pop = 0;
2600 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3)
2601 alu_pop = 1;
2602 }
2603 alu_pop += pops;
2604 if (alu_pop == 1) {
2605 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3;
2606 ctx->bc->force_add_cf = 1;
2607 } else if (alu_pop == 2) {
2608 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER) << 3;
2609 ctx->bc->force_add_cf = 1;
2610 } else {
2611 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2612 ctx->bc->cf_last->pop_count = pops;
2613 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2614 }
2615 return 0;
2616 }
2617
2618 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2619 {
2620 switch(reason) {
2621 case FC_PUSH_VPM:
2622 ctx->bc->callstack[ctx->bc->call_sp].current--;
2623 break;
2624 case FC_PUSH_WQM:
2625 case FC_LOOP:
2626 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2627 break;
2628 case FC_REP:
2629 /* TOODO : for 16 vp asic should -= 2; */
2630 ctx->bc->callstack[ctx->bc->call_sp].current --;
2631 break;
2632 }
2633 }
2634
2635 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2636 {
2637 if (check_max_only) {
2638 int diff;
2639 switch (reason) {
2640 case FC_PUSH_VPM:
2641 diff = 1;
2642 break;
2643 case FC_PUSH_WQM:
2644 diff = 4;
2645 break;
2646 default:
2647 assert(0);
2648 diff = 0;
2649 }
2650 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2651 ctx->bc->callstack[ctx->bc->call_sp].max) {
2652 ctx->bc->callstack[ctx->bc->call_sp].max =
2653 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2654 }
2655 return;
2656 }
2657 switch (reason) {
2658 case FC_PUSH_VPM:
2659 ctx->bc->callstack[ctx->bc->call_sp].current++;
2660 break;
2661 case FC_PUSH_WQM:
2662 case FC_LOOP:
2663 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2664 break;
2665 case FC_REP:
2666 ctx->bc->callstack[ctx->bc->call_sp].current++;
2667 break;
2668 }
2669
2670 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2671 ctx->bc->callstack[ctx->bc->call_sp].max) {
2672 ctx->bc->callstack[ctx->bc->call_sp].max =
2673 ctx->bc->callstack[ctx->bc->call_sp].current;
2674 }
2675 }
2676
2677 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2678 {
2679 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2680
2681 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2682 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2683 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2684 sp->num_mid++;
2685 }
2686
2687 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2688 {
2689 ctx->bc->fc_sp++;
2690 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2691 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2692 }
2693
2694 static void fc_poplevel(struct r600_shader_ctx *ctx)
2695 {
2696 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2697 if (sp->mid) {
2698 free(sp->mid);
2699 sp->mid = NULL;
2700 }
2701 sp->num_mid = 0;
2702 sp->start = NULL;
2703 sp->type = 0;
2704 ctx->bc->fc_sp--;
2705 }
2706
2707 #if 0
2708 static int emit_return(struct r600_shader_ctx *ctx)
2709 {
2710 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2711 return 0;
2712 }
2713
2714 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2715 {
2716
2717 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2718 ctx->bc->cf_last->pop_count = pops;
2719 /* TODO work out offset */
2720 return 0;
2721 }
2722
2723 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2724 {
2725 return 0;
2726 }
2727
2728 static void emit_testflag(struct r600_shader_ctx *ctx)
2729 {
2730
2731 }
2732
2733 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2734 {
2735 emit_testflag(ctx);
2736 emit_jump_to_offset(ctx, 1, 4);
2737 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2738 pops(ctx, ifidx + 1);
2739 emit_return(ctx);
2740 }
2741
2742 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2743 {
2744 emit_testflag(ctx);
2745
2746 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2747 ctx->bc->cf_last->pop_count = 1;
2748
2749 fc_set_mid(ctx, fc_sp);
2750
2751 pops(ctx, 1);
2752 }
2753 #endif
2754
2755 static int tgsi_if(struct r600_shader_ctx *ctx)
2756 {
2757 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2758
2759 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2760
2761 fc_pushlevel(ctx, FC_IF);
2762
2763 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2764 return 0;
2765 }
2766
2767 static int tgsi_else(struct r600_shader_ctx *ctx)
2768 {
2769 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2770 ctx->bc->cf_last->pop_count = 1;
2771
2772 fc_set_mid(ctx, ctx->bc->fc_sp);
2773 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2774 return 0;
2775 }
2776
2777 static int tgsi_endif(struct r600_shader_ctx *ctx)
2778 {
2779 pops(ctx, 1);
2780 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2781 R600_ERR("if/endif unbalanced in shader\n");
2782 return -1;
2783 }
2784
2785 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2786 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2787 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2788 } else {
2789 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2790 }
2791 fc_poplevel(ctx);
2792
2793 callstack_decrease_current(ctx, FC_PUSH_VPM);
2794 return 0;
2795 }
2796
2797 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2798 {
2799 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2800
2801 fc_pushlevel(ctx, FC_LOOP);
2802
2803 /* check stack depth */
2804 callstack_check_depth(ctx, FC_LOOP, 0);
2805 return 0;
2806 }
2807
2808 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2809 {
2810 int i;
2811
2812 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2813
2814 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2815 R600_ERR("loop/endloop in shader code are not paired.\n");
2816 return -EINVAL;
2817 }
2818
2819 /* fixup loop pointers - from r600isa
2820 LOOP END points to CF after LOOP START,
2821 LOOP START point to CF after LOOP END
2822 BRK/CONT point to LOOP END CF
2823 */
2824 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2825
2826 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2827
2828 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2829 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2830 }
2831 /* TODO add LOOPRET support */
2832 fc_poplevel(ctx);
2833 callstack_decrease_current(ctx, FC_LOOP);
2834 return 0;
2835 }
2836
2837 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2838 {
2839 unsigned int fscp;
2840
2841 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2842 {
2843 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2844 break;
2845 }
2846
2847 if (fscp == 0) {
2848 R600_ERR("Break not inside loop/endloop pair\n");
2849 return -EINVAL;
2850 }
2851
2852 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2853 ctx->bc->cf_last->pop_count = 1;
2854
2855 fc_set_mid(ctx, fscp);
2856
2857 pops(ctx, 1);
2858 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2859 return 0;
2860 }
2861
2862 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2863 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2864 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2865 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2866
2867 /* FIXME:
2868 * For state trackers other than OpenGL, we'll want to use
2869 * _RECIP_IEEE instead.
2870 */
2871 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2872
2873 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2874 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2875 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2876 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2877 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2878 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2879 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2880 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2881 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2882 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2883 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2884 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2885 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2886 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2887 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2888 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2889 /* gap */
2890 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2891 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2892 /* gap */
2893 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2894 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2895 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2896 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2897 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2898 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2899 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2900 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2901 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2902 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2903 /* gap */
2904 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2906 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2908 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2909 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2910 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2911 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2912 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2913 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2914 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2917 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2918 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2919 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2920 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2921 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2922 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2923 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2924 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2925 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2926 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2927 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2932 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2934 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2937 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2938 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2939 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2940 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2941 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2942 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2943 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2944 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2945 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2946 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2947 /* gap */
2948 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2949 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2950 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2951 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2952 /* gap */
2953 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2954 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2955 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2956 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2957 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2958 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2959 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2960 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2961 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2962 /* gap */
2963 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2965 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2968 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2969 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2971 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2972 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2973 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2975 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2976 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2977 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2978 /* gap */
2979 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2981 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2983 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2984 /* gap */
2985 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2986 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2987 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2993 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2994 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2995 /* gap */
2996 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2997 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2998 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3000 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3002 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3009 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3010 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3013 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3014 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3015 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3016 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3019 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3020 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3021 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3022 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3023 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 };
3025
3026 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
3027 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3028 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3029 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
3030 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
3031 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
3032 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
3033 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
3035 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3036 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3037 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3038 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
3039 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
3040 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
3041 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
3042 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
3043 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
3044 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
3045 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
3046 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3047 /* gap */
3048 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3049 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3050 /* gap */
3051 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3052 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3053 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
3054 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
3056 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
3058 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
3059 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
3060 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
3061 /* gap */
3062 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
3064 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3066 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
3067 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
3068 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
3069 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
3070 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3071 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3075 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
3076 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3077 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
3078 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
3079 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
3080 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
3081 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3082 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3083 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3085 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3092 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3096 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3097 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3098 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3099 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3100 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3101 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3102 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3103 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3104 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3105 /* gap */
3106 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3107 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3108 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3109 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3110 /* gap */
3111 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3112 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3113 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3114 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3115 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3116 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3117 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3118 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3119 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3120 /* gap */
3121 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3122 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3123 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3124 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3125 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3126 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3127 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3128 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3129 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3130 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3131 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3132 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3133 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3134 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3135 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3136 /* gap */
3137 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3138 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3139 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3140 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3141 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3142 /* gap */
3143 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3144 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3145 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3146 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3147 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3148 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3149 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3150 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3151 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3152 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3153 /* gap */
3154 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3155 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3156 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3157 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3158 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3159 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3160 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3161 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3162 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3163 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3164 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3165 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3166 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3167 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3168 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3169 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3170 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3171 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3172 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3173 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3174 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3175 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3176 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3177 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3178 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3179 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3180 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3181 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3182 };