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intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer
[mesa.git] / src / gallium / drivers / r600 / r600_shader.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
29 #include "r600_asm.h"
30 #include "r600_sq.h"
31 #include "r600_formats.h"
32 #include "r600_opcodes.h"
33 #include "r600d.h"
34 #include <stdio.h>
35 #include <errno.h>
36
37 static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
38 {
39 struct r600_pipe_state *rstate = &shader->rstate;
40 struct r600_shader *rshader = &shader->shader;
41 unsigned spi_vs_out_id[10];
42 unsigned i, tmp;
43
44 /* clear previous register */
45 rstate->nregs = 0;
46
47 /* so far never got proper semantic id from tgsi */
48 /* FIXME better to move this in config things so they get emited
49 * only one time per cs
50 */
51 for (i = 0; i < 10; i++) {
52 spi_vs_out_id[i] = 0;
53 }
54 for (i = 0; i < 32; i++) {
55 tmp = i << ((i & 3) * 8);
56 spi_vs_out_id[i / 4] |= tmp;
57 }
58 for (i = 0; i < 10; i++) {
59 r600_pipe_state_add_reg(rstate,
60 R_028614_SPI_VS_OUT_ID_0 + i * 4,
61 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
62 }
63
64 r600_pipe_state_add_reg(rstate,
65 R_0286C4_SPI_VS_OUT_CONFIG,
66 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
67 0xFFFFFFFF, NULL);
68 r600_pipe_state_add_reg(rstate,
69 R_028868_SQ_PGM_RESOURCES_VS,
70 S_028868_NUM_GPRS(rshader->bc.ngpr) |
71 S_028868_STACK_SIZE(rshader->bc.nstack),
72 0xFFFFFFFF, NULL);
73 r600_pipe_state_add_reg(rstate,
74 R_0288D0_SQ_PGM_CF_OFFSET_VS,
75 0x00000000, 0xFFFFFFFF, NULL);
76 r600_pipe_state_add_reg(rstate,
77 R_028858_SQ_PGM_START_VS,
78 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
79
80 r600_pipe_state_add_reg(rstate,
81 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
82 0xFFFFFFFF, NULL);
83
84 }
85
86 int r600_find_vs_semantic_index(struct r600_shader *vs,
87 struct r600_shader *ps, int id)
88 {
89 struct r600_shader_io *input = &ps->input[id];
90
91 for (int i = 0; i < vs->noutput; i++) {
92 if (input->name == vs->output[i].name &&
93 input->sid == vs->output[i].sid) {
94 return i - 1;
95 }
96 }
97 return 0;
98 }
99
100 static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
101 {
102 struct r600_pipe_state *rstate = &shader->rstate;
103 struct r600_shader *rshader = &shader->shader;
104 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
105 int pos_index = -1, face_index = -1;
106
107 rstate->nregs = 0;
108
109 for (i = 0; i < rshader->ninput; i++) {
110 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
111 pos_index = i;
112 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
113 face_index = i;
114 }
115
116 for (i = 0; i < rshader->noutput; i++) {
117 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
118 r600_pipe_state_add_reg(rstate,
119 R_02880C_DB_SHADER_CONTROL,
120 S_02880C_Z_EXPORT_ENABLE(1),
121 S_02880C_Z_EXPORT_ENABLE(1), NULL);
122 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
123 r600_pipe_state_add_reg(rstate,
124 R_02880C_DB_SHADER_CONTROL,
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
126 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
127 }
128
129 exports_ps = 0;
130 num_cout = 0;
131 for (i = 0; i < rshader->noutput; i++) {
132 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
133 exports_ps |= 1;
134 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
135 num_cout++;
136 }
137 }
138 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
139 if (!exports_ps) {
140 /* always at least export 1 component per pixel */
141 exports_ps = 2;
142 }
143
144 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
145 S_0286CC_PERSP_GRADIENT_ENA(1);
146 spi_input_z = 0;
147 if (pos_index != -1) {
148 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
149 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
150 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
151 S_0286CC_BARYC_SAMPLE_CNTL(1));
152 spi_input_z |= 1;
153 }
154
155 spi_ps_in_control_1 = 0;
156 if (face_index != -1) {
157 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
158 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
159 }
160
161 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
162 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
163 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
164 r600_pipe_state_add_reg(rstate,
165 R_028840_SQ_PGM_START_PS,
166 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
167 r600_pipe_state_add_reg(rstate,
168 R_028850_SQ_PGM_RESOURCES_PS,
169 S_028868_NUM_GPRS(rshader->bc.ngpr) |
170 S_028868_STACK_SIZE(rshader->bc.nstack),
171 0xFFFFFFFF, NULL);
172 r600_pipe_state_add_reg(rstate,
173 R_028854_SQ_PGM_EXPORTS_PS,
174 exports_ps, 0xFFFFFFFF, NULL);
175 r600_pipe_state_add_reg(rstate,
176 R_0288CC_SQ_PGM_CF_OFFSET_PS,
177 0x00000000, 0xFFFFFFFF, NULL);
178
179 if (rshader->fs_write_all) {
180 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
181 S_028808_MULTIWRITE_ENABLE(1),
182 S_028808_MULTIWRITE_ENABLE(1),
183 NULL);
184 }
185
186 if (rshader->uses_kill) {
187 /* only set some bits here, the other bits are set in the dsa state */
188 r600_pipe_state_add_reg(rstate,
189 R_02880C_DB_SHADER_CONTROL,
190 S_02880C_KILL_ENABLE(1),
191 S_02880C_KILL_ENABLE(1), NULL);
192 }
193 r600_pipe_state_add_reg(rstate,
194 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
195 0xFFFFFFFF, NULL);
196 }
197
198 static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
199 {
200 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
201 struct r600_shader *rshader = &shader->shader;
202 void *ptr;
203
204 /* copy new shader */
205 if (shader->bo == NULL) {
206 shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0, 0);
207 if (shader->bo == NULL) {
208 return -ENOMEM;
209 }
210 ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
211 memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
212 r600_bo_unmap(rctx->radeon, shader->bo);
213 }
214 /* build state */
215 switch (rshader->processor_type) {
216 case TGSI_PROCESSOR_VERTEX:
217 if (rshader->family >= CHIP_CEDAR) {
218 evergreen_pipe_shader_vs(ctx, shader);
219 } else {
220 r600_pipe_shader_vs(ctx, shader);
221 }
222 break;
223 case TGSI_PROCESSOR_FRAGMENT:
224 if (rshader->family >= CHIP_CEDAR) {
225 evergreen_pipe_shader_ps(ctx, shader);
226 } else {
227 r600_pipe_shader_ps(ctx, shader);
228 }
229 break;
230 default:
231 return -EINVAL;
232 }
233 return 0;
234 }
235
236 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
237
238 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
239 {
240 static int dump_shaders = -1;
241 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
242 int r;
243
244 /* Would like some magic "get_bool_option_once" routine.
245 */
246 if (dump_shaders == -1)
247 dump_shaders = debug_get_bool_option("R600_DUMP_SHADERS", FALSE);
248
249 if (dump_shaders) {
250 fprintf(stderr, "--------------------------------------------------------------\n");
251 tgsi_dump(tokens, 0);
252 }
253 shader->shader.family = r600_get_family(rctx->radeon);
254 r = r600_shader_from_tgsi(tokens, &shader->shader);
255 if (r) {
256 R600_ERR("translation from TGSI failed !\n");
257 return r;
258 }
259 r = r600_bc_build(&shader->shader.bc);
260 if (r) {
261 R600_ERR("building bytecode failed !\n");
262 return r;
263 }
264 if (dump_shaders) {
265 r600_bc_dump(&shader->shader.bc);
266 fprintf(stderr, "______________________________________________________________\n");
267 }
268 return r600_pipe_shader(ctx, shader);
269 }
270
271 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader)
272 {
273 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
274
275 r600_bo_reference(rctx->radeon, &shader->bo, NULL);
276 r600_bc_clear(&shader->shader.bc);
277 }
278
279 /*
280 * tgsi -> r600 shader
281 */
282 struct r600_shader_tgsi_instruction;
283
284 struct r600_shader_src {
285 unsigned sel;
286 unsigned swizzle[4];
287 unsigned neg;
288 unsigned abs;
289 unsigned rel;
290 uint32_t value[4];
291 };
292
293 struct r600_shader_ctx {
294 struct tgsi_shader_info info;
295 struct tgsi_parse_context parse;
296 const struct tgsi_token *tokens;
297 unsigned type;
298 unsigned file_offset[TGSI_FILE_COUNT];
299 unsigned temp_reg;
300 unsigned ar_reg;
301 struct r600_shader_tgsi_instruction *inst_info;
302 struct r600_bc *bc;
303 struct r600_shader *shader;
304 struct r600_shader_src src[3];
305 u32 *literals;
306 u32 nliterals;
307 u32 max_driver_temp_used;
308 /* needed for evergreen interpolation */
309 boolean input_centroid;
310 boolean input_linear;
311 boolean input_perspective;
312 int num_interp_gpr;
313 };
314
315 struct r600_shader_tgsi_instruction {
316 unsigned tgsi_opcode;
317 unsigned is_op3;
318 unsigned r600_opcode;
319 int (*process)(struct r600_shader_ctx *ctx);
320 };
321
322 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
323 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
324
325 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
326 {
327 struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;
328 int j;
329
330 if (i->Instruction.NumDstRegs > 1) {
331 R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
332 return -EINVAL;
333 }
334 if (i->Instruction.Predicate) {
335 R600_ERR("predicate unsupported\n");
336 return -EINVAL;
337 }
338 #if 0
339 if (i->Instruction.Label) {
340 R600_ERR("label unsupported\n");
341 return -EINVAL;
342 }
343 #endif
344 for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
345 if (i->Src[j].Register.Dimension) {
346 R600_ERR("unsupported src %d (dimension %d)\n", j,
347 i->Src[j].Register.Dimension);
348 return -EINVAL;
349 }
350 }
351 for (j = 0; j < i->Instruction.NumDstRegs; j++) {
352 if (i->Dst[j].Register.Dimension) {
353 R600_ERR("unsupported dst (dimension)\n");
354 return -EINVAL;
355 }
356 }
357 return 0;
358 }
359
360 static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
361 {
362 int i, r;
363 struct r600_bc_alu alu;
364 int gpr = 0, base_chan = 0;
365 int ij_index = 0;
366
367 if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
368 ij_index = 0;
369 if (ctx->shader->input[input].centroid)
370 ij_index++;
371 } else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
372 ij_index = 0;
373 /* if we have perspective add one */
374 if (ctx->input_perspective) {
375 ij_index++;
376 /* if we have perspective centroid */
377 if (ctx->input_centroid)
378 ij_index++;
379 }
380 if (ctx->shader->input[input].centroid)
381 ij_index++;
382 }
383
384 /* work out gpr and base_chan from index */
385 gpr = ij_index / 2;
386 base_chan = (2 * (ij_index % 2)) + 1;
387
388 for (i = 0; i < 8; i++) {
389 memset(&alu, 0, sizeof(struct r600_bc_alu));
390
391 if (i < 4)
392 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW;
393 else
394 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
395
396 if ((i > 1) && (i < 6)) {
397 alu.dst.sel = ctx->shader->input[input].gpr;
398 alu.dst.write = 1;
399 }
400
401 alu.dst.chan = i % 4;
402
403 alu.src[0].sel = gpr;
404 alu.src[0].chan = (base_chan - (i % 2));
405
406 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
407
408 alu.bank_swizzle_force = SQ_ALU_VEC_210;
409 if ((i % 4) == 3)
410 alu.last = 1;
411 r = r600_bc_add_alu(ctx->bc, &alu);
412 if (r)
413 return r;
414 }
415 return 0;
416 }
417
418
419 static int tgsi_declaration(struct r600_shader_ctx *ctx)
420 {
421 struct tgsi_full_declaration *d = &ctx->parse.FullToken.FullDeclaration;
422 unsigned i;
423
424 switch (d->Declaration.File) {
425 case TGSI_FILE_INPUT:
426 i = ctx->shader->ninput++;
427 ctx->shader->input[i].name = d->Semantic.Name;
428 ctx->shader->input[i].sid = d->Semantic.Index;
429 ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
430 ctx->shader->input[i].centroid = d->Declaration.Centroid;
431 ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
432 if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == CHIPREV_EVERGREEN) {
433 /* turn input into interpolate on EG */
434 if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
435 if (ctx->shader->input[i].interpolate > 0) {
436 ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
437 evergreen_interp_alu(ctx, i);
438 }
439 }
440 }
441 break;
442 case TGSI_FILE_OUTPUT:
443 i = ctx->shader->noutput++;
444 ctx->shader->output[i].name = d->Semantic.Name;
445 ctx->shader->output[i].sid = d->Semantic.Index;
446 ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
447 ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
448 break;
449 case TGSI_FILE_CONSTANT:
450 case TGSI_FILE_TEMPORARY:
451 case TGSI_FILE_SAMPLER:
452 case TGSI_FILE_ADDRESS:
453 break;
454 default:
455 R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
456 return -EINVAL;
457 }
458 return 0;
459 }
460
461 static int r600_get_temp(struct r600_shader_ctx *ctx)
462 {
463 return ctx->temp_reg + ctx->max_driver_temp_used++;
464 }
465
466 /*
467 * for evergreen we need to scan the shader to find the number of GPRs we need to
468 * reserve for interpolation.
469 *
470 * we need to know if we are going to emit
471 * any centroid inputs
472 * if perspective and linear are required
473 */
474 static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
475 {
476 int i;
477 int num_baryc;
478
479 ctx->input_linear = FALSE;
480 ctx->input_perspective = FALSE;
481 ctx->input_centroid = FALSE;
482 ctx->num_interp_gpr = 1;
483
484 /* any centroid inputs */
485 for (i = 0; i < ctx->info.num_inputs; i++) {
486 /* skip position/face */
487 if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
488 ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
489 continue;
490 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
491 ctx->input_linear = TRUE;
492 if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
493 ctx->input_perspective = TRUE;
494 if (ctx->info.input_centroid[i])
495 ctx->input_centroid = TRUE;
496 }
497
498 num_baryc = 0;
499 /* ignoring sample for now */
500 if (ctx->input_perspective)
501 num_baryc++;
502 if (ctx->input_linear)
503 num_baryc++;
504 if (ctx->input_centroid)
505 num_baryc *= 2;
506
507 ctx->num_interp_gpr += (num_baryc + 1) >> 1;
508
509 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
510 return ctx->num_interp_gpr;
511 }
512
513 static void tgsi_src(struct r600_shader_ctx *ctx,
514 const struct tgsi_full_src_register *tgsi_src,
515 struct r600_shader_src *r600_src)
516 {
517 memset(r600_src, 0, sizeof(*r600_src));
518 r600_src->swizzle[0] = tgsi_src->Register.SwizzleX;
519 r600_src->swizzle[1] = tgsi_src->Register.SwizzleY;
520 r600_src->swizzle[2] = tgsi_src->Register.SwizzleZ;
521 r600_src->swizzle[3] = tgsi_src->Register.SwizzleW;
522 r600_src->neg = tgsi_src->Register.Negate;
523 r600_src->abs = tgsi_src->Register.Absolute;
524 if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
525 int index;
526 if ((tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleY) &&
527 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleZ) &&
528 (tgsi_src->Register.SwizzleX == tgsi_src->Register.SwizzleW)) {
529
530 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
531 r600_bc_special_constants(ctx->literals[index], &r600_src->sel, &r600_src->neg);
532 if (r600_src->sel != V_SQ_ALU_SRC_LITERAL)
533 return;
534 }
535 index = tgsi_src->Register.Index;
536 r600_src->sel = V_SQ_ALU_SRC_LITERAL;
537 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
538 } else {
539 if (tgsi_src->Register.Indirect)
540 r600_src->rel = V_SQ_REL_RELATIVE;
541 r600_src->sel = tgsi_src->Register.Index;
542 r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
543 }
544 }
545
546 static int tgsi_fetch_rel_const(struct r600_shader_ctx *ctx, unsigned int offset, unsigned int dst_reg)
547 {
548 struct r600_bc_vtx vtx;
549 unsigned int ar_reg;
550 int r;
551
552 if (offset) {
553 struct r600_bc_alu alu;
554
555 memset(&alu, 0, sizeof(alu));
556
557 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD_INT);
558 alu.src[0].sel = ctx->ar_reg;
559
560 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
561 alu.src[1].value = offset;
562
563 alu.dst.sel = dst_reg;
564 alu.dst.write = 1;
565 alu.last = 1;
566
567 if ((r = r600_bc_add_alu(ctx->bc, &alu)))
568 return r;
569
570 ar_reg = dst_reg;
571 } else {
572 ar_reg = ctx->ar_reg;
573 }
574
575 memset(&vtx, 0, sizeof(vtx));
576 vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
577 vtx.src_gpr = ar_reg;
578 vtx.mega_fetch_count = 16;
579 vtx.dst_gpr = dst_reg;
580 vtx.dst_sel_x = 0; /* SEL_X */
581 vtx.dst_sel_y = 1; /* SEL_Y */
582 vtx.dst_sel_z = 2; /* SEL_Z */
583 vtx.dst_sel_w = 3; /* SEL_W */
584 vtx.data_format = FMT_32_32_32_32_FLOAT;
585 vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
586 vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
587 vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
588
589 if ((r = r600_bc_add_vtx(ctx->bc, &vtx)))
590 return r;
591
592 return 0;
593 }
594
595 static int tgsi_split_constant(struct r600_shader_ctx *ctx)
596 {
597 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
598 struct r600_bc_alu alu;
599 int i, j, k, nconst, r;
600
601 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
602 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
603 nconst++;
604 }
605 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
606 }
607 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
608 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
609 continue;
610 }
611
612 if (ctx->src[i].rel) {
613 int treg = r600_get_temp(ctx);
614 if ((r = tgsi_fetch_rel_const(ctx, ctx->src[i].sel - 512, treg)))
615 return r;
616
617 ctx->src[i].sel = treg;
618 ctx->src[i].rel = 0;
619 j--;
620 } else if (j > 0) {
621 int treg = r600_get_temp(ctx);
622 for (k = 0; k < 4; k++) {
623 memset(&alu, 0, sizeof(struct r600_bc_alu));
624 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
625 alu.src[0].sel = ctx->src[i].sel;
626 alu.src[0].chan = k;
627 alu.src[0].rel = ctx->src[i].rel;
628 alu.dst.sel = treg;
629 alu.dst.chan = k;
630 alu.dst.write = 1;
631 if (k == 3)
632 alu.last = 1;
633 r = r600_bc_add_alu(ctx->bc, &alu);
634 if (r)
635 return r;
636 }
637 ctx->src[i].sel = treg;
638 ctx->src[i].rel =0;
639 j--;
640 }
641 }
642 return 0;
643 }
644
645 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
646 static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx)
647 {
648 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
649 struct r600_bc_alu alu;
650 int i, j, k, nliteral, r;
651
652 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
653 if (ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
654 nliteral++;
655 }
656 }
657 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
658 if (j > 0 && ctx->src[i].sel == V_SQ_ALU_SRC_LITERAL) {
659 int treg = r600_get_temp(ctx);
660 for (k = 0; k < 4; k++) {
661 memset(&alu, 0, sizeof(struct r600_bc_alu));
662 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
663 alu.src[0].sel = ctx->src[i].sel;
664 alu.src[0].chan = k;
665 alu.src[0].value = ctx->src[i].value[k];
666 alu.dst.sel = treg;
667 alu.dst.chan = k;
668 alu.dst.write = 1;
669 if (k == 3)
670 alu.last = 1;
671 r = r600_bc_add_alu(ctx->bc, &alu);
672 if (r)
673 return r;
674 }
675 ctx->src[i].sel = treg;
676 j--;
677 }
678 }
679 return 0;
680 }
681
682 static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
683 {
684 struct tgsi_full_immediate *immediate;
685 struct tgsi_full_property *property;
686 struct r600_shader_ctx ctx;
687 struct r600_bc_output output[32];
688 unsigned output_done, noutput;
689 unsigned opcode;
690 int i, r = 0, pos0;
691
692 ctx.bc = &shader->bc;
693 ctx.shader = shader;
694 r = r600_bc_init(ctx.bc, shader->family);
695 if (r)
696 return r;
697 ctx.tokens = tokens;
698 tgsi_scan_shader(tokens, &ctx.info);
699 tgsi_parse_init(&ctx.parse, tokens);
700 ctx.type = ctx.parse.FullHeader.Processor.Processor;
701 shader->processor_type = ctx.type;
702 ctx.bc->type = shader->processor_type;
703
704 /* register allocations */
705 /* Values [0,127] correspond to GPR[0..127].
706 * Values [128,159] correspond to constant buffer bank 0
707 * Values [160,191] correspond to constant buffer bank 1
708 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
709 * Values [256,287] correspond to constant buffer bank 2 (EG)
710 * Values [288,319] correspond to constant buffer bank 3 (EG)
711 * Other special values are shown in the list below.
712 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
713 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
714 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
715 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
716 * 248 SQ_ALU_SRC_0: special constant 0.0.
717 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
718 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
719 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
720 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
721 * 253 SQ_ALU_SRC_LITERAL: literal constant.
722 * 254 SQ_ALU_SRC_PV: previous vector result.
723 * 255 SQ_ALU_SRC_PS: previous scalar result.
724 */
725 for (i = 0; i < TGSI_FILE_COUNT; i++) {
726 ctx.file_offset[i] = 0;
727 }
728 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
729 ctx.file_offset[TGSI_FILE_INPUT] = 1;
730 if (ctx.bc->chiprev == CHIPREV_EVERGREEN) {
731 r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
732 } else {
733 r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
734 }
735 }
736 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == CHIPREV_EVERGREEN) {
737 ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
738 }
739 ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
740 ctx.info.file_count[TGSI_FILE_INPUT];
741 ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
742 ctx.info.file_count[TGSI_FILE_OUTPUT];
743
744 /* Outside the GPR range. This will be translated to one of the
745 * kcache banks later. */
746 ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
747
748 ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
749 ctx.ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
750 ctx.info.file_count[TGSI_FILE_TEMPORARY];
751 ctx.temp_reg = ctx.ar_reg + 1;
752
753 ctx.nliterals = 0;
754 ctx.literals = NULL;
755 shader->fs_write_all = FALSE;
756 while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
757 tgsi_parse_token(&ctx.parse);
758 switch (ctx.parse.FullToken.Token.Type) {
759 case TGSI_TOKEN_TYPE_IMMEDIATE:
760 immediate = &ctx.parse.FullToken.FullImmediate;
761 ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
762 if(ctx.literals == NULL) {
763 r = -ENOMEM;
764 goto out_err;
765 }
766 ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
767 ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
768 ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
769 ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
770 ctx.nliterals++;
771 break;
772 case TGSI_TOKEN_TYPE_DECLARATION:
773 r = tgsi_declaration(&ctx);
774 if (r)
775 goto out_err;
776 break;
777 case TGSI_TOKEN_TYPE_INSTRUCTION:
778 r = tgsi_is_supported(&ctx);
779 if (r)
780 goto out_err;
781 ctx.max_driver_temp_used = 0;
782 /* reserve first tmp for everyone */
783 r600_get_temp(&ctx);
784
785 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
786 if ((r = tgsi_split_constant(&ctx)))
787 goto out_err;
788 if ((r = tgsi_split_literal_constant(&ctx)))
789 goto out_err;
790 if (ctx.bc->chiprev == CHIPREV_EVERGREEN)
791 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
792 else
793 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
794 r = ctx.inst_info->process(&ctx);
795 if (r)
796 goto out_err;
797 break;
798 case TGSI_TOKEN_TYPE_PROPERTY:
799 property = &ctx.parse.FullToken.FullProperty;
800 if (property->Property.PropertyName == TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS) {
801 if (property->u[0].Data == 1)
802 shader->fs_write_all = TRUE;
803 }
804 break;
805 default:
806 R600_ERR("unsupported token type %d\n", ctx.parse.FullToken.Token.Type);
807 r = -EINVAL;
808 goto out_err;
809 }
810 }
811 /* export output */
812 noutput = shader->noutput;
813 for (i = 0, pos0 = 0; i < noutput; i++) {
814 memset(&output[i], 0, sizeof(struct r600_bc_output));
815 output[i].gpr = shader->output[i].gpr;
816 output[i].elem_size = 3;
817 output[i].swizzle_x = 0;
818 output[i].swizzle_y = 1;
819 output[i].swizzle_z = 2;
820 output[i].swizzle_w = 3;
821 output[i].burst_count = 1;
822 output[i].barrier = 1;
823 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
824 output[i].array_base = i - pos0;
825 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
826 switch (ctx.type) {
827 case TGSI_PROCESSOR_VERTEX:
828 if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
829 output[i].array_base = 60;
830 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
831 /* position doesn't count in array_base */
832 pos0++;
833 }
834 if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
835 output[i].array_base = 61;
836 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
837 /* position doesn't count in array_base */
838 pos0++;
839 }
840 break;
841 case TGSI_PROCESSOR_FRAGMENT:
842 if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
843 output[i].array_base = shader->output[i].sid;
844 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
845 } else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
846 output[i].array_base = 61;
847 output[i].swizzle_x = 2;
848 output[i].swizzle_y = 7;
849 output[i].swizzle_z = output[i].swizzle_w = 7;
850 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
851 } else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
852 output[i].array_base = 61;
853 output[i].swizzle_x = 7;
854 output[i].swizzle_y = 1;
855 output[i].swizzle_z = output[i].swizzle_w = 7;
856 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
857 } else {
858 R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
859 r = -EINVAL;
860 goto out_err;
861 }
862 break;
863 default:
864 R600_ERR("unsupported processor type %d\n", ctx.type);
865 r = -EINVAL;
866 goto out_err;
867 }
868 }
869 /* add fake param output for vertex shader if no param is exported */
870 if (ctx.type == TGSI_PROCESSOR_VERTEX) {
871 for (i = 0, pos0 = 0; i < noutput; i++) {
872 if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
873 pos0 = 1;
874 break;
875 }
876 }
877 if (!pos0) {
878 memset(&output[i], 0, sizeof(struct r600_bc_output));
879 output[i].gpr = 0;
880 output[i].elem_size = 3;
881 output[i].swizzle_x = 0;
882 output[i].swizzle_y = 1;
883 output[i].swizzle_z = 2;
884 output[i].swizzle_w = 3;
885 output[i].burst_count = 1;
886 output[i].barrier = 1;
887 output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
888 output[i].array_base = 0;
889 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
890 noutput++;
891 }
892 }
893 /* add fake pixel export */
894 if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
895 memset(&output[0], 0, sizeof(struct r600_bc_output));
896 output[0].gpr = 0;
897 output[0].elem_size = 3;
898 output[0].swizzle_x = 7;
899 output[0].swizzle_y = 7;
900 output[0].swizzle_z = 7;
901 output[0].swizzle_w = 7;
902 output[0].burst_count = 1;
903 output[0].barrier = 1;
904 output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
905 output[0].array_base = 0;
906 output[0].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
907 noutput++;
908 }
909 /* set export done on last export of each type */
910 for (i = noutput - 1, output_done = 0; i >= 0; i--) {
911 if (i == (noutput - 1)) {
912 output[i].end_of_program = 1;
913 }
914 if (!(output_done & (1 << output[i].type))) {
915 output_done |= (1 << output[i].type);
916 output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE);
917 }
918 }
919 /* add output to bytecode */
920 for (i = 0; i < noutput; i++) {
921 r = r600_bc_add_output(ctx.bc, &output[i]);
922 if (r)
923 goto out_err;
924 }
925 free(ctx.literals);
926 tgsi_parse_free(&ctx.parse);
927 return 0;
928 out_err:
929 free(ctx.literals);
930 tgsi_parse_free(&ctx.parse);
931 return r;
932 }
933
934 static int tgsi_unsupported(struct r600_shader_ctx *ctx)
935 {
936 R600_ERR("%d tgsi opcode unsupported\n", ctx->inst_info->tgsi_opcode);
937 return -EINVAL;
938 }
939
940 static int tgsi_end(struct r600_shader_ctx *ctx)
941 {
942 return 0;
943 }
944
945 static void r600_bc_src(struct r600_bc_alu_src *bc_src,
946 const struct r600_shader_src *shader_src,
947 unsigned chan)
948 {
949 bc_src->sel = shader_src->sel;
950 bc_src->chan = shader_src->swizzle[chan];
951 bc_src->neg = shader_src->neg;
952 bc_src->abs = shader_src->abs;
953 bc_src->rel = shader_src->rel;
954 bc_src->value = shader_src->value[bc_src->chan];
955 }
956
957 static void tgsi_dst(struct r600_shader_ctx *ctx,
958 const struct tgsi_full_dst_register *tgsi_dst,
959 unsigned swizzle,
960 struct r600_bc_alu_dst *r600_dst)
961 {
962 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
963
964 r600_dst->sel = tgsi_dst->Register.Index;
965 r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
966 r600_dst->chan = swizzle;
967 r600_dst->write = 1;
968 if (tgsi_dst->Register.Indirect)
969 r600_dst->rel = V_SQ_REL_RELATIVE;
970 if (inst->Instruction.Saturate) {
971 r600_dst->clamp = 1;
972 }
973 }
974
975 static int tgsi_last_instruction(unsigned writemask)
976 {
977 int i, lasti = 0;
978
979 for (i = 0; i < 4; i++) {
980 if (writemask & (1 << i)) {
981 lasti = i;
982 }
983 }
984 return lasti;
985 }
986
987 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
988 {
989 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
990 struct r600_bc_alu alu;
991 int i, j, r;
992 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
993
994 for (i = 0; i < lasti + 1; i++) {
995 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
996 continue;
997
998 memset(&alu, 0, sizeof(struct r600_bc_alu));
999 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1000
1001 alu.inst = ctx->inst_info->r600_opcode;
1002 if (!swap) {
1003 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1004 r600_bc_src(&alu.src[j], &ctx->src[j], i);
1005 }
1006 } else {
1007 r600_bc_src(&alu.src[0], &ctx->src[1], i);
1008 r600_bc_src(&alu.src[1], &ctx->src[0], i);
1009 }
1010 /* handle some special cases */
1011 switch (ctx->inst_info->tgsi_opcode) {
1012 case TGSI_OPCODE_SUB:
1013 alu.src[1].neg = 1;
1014 break;
1015 case TGSI_OPCODE_ABS:
1016 alu.src[0].abs = 1;
1017 break;
1018 default:
1019 break;
1020 }
1021 if (i == lasti) {
1022 alu.last = 1;
1023 }
1024 r = r600_bc_add_alu(ctx->bc, &alu);
1025 if (r)
1026 return r;
1027 }
1028 return 0;
1029 }
1030
1031 static int tgsi_op2(struct r600_shader_ctx *ctx)
1032 {
1033 return tgsi_op2_s(ctx, 0);
1034 }
1035
1036 static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
1037 {
1038 return tgsi_op2_s(ctx, 1);
1039 }
1040
1041 /*
1042 * r600 - trunc to -PI..PI range
1043 * r700 - normalize by dividing by 2PI
1044 * see fdo bug 27901
1045 */
1046 static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
1047 {
1048 static float half_inv_pi = 1.0 /(3.1415926535 * 2);
1049 static float double_pi = 3.1415926535 * 2;
1050 static float neg_pi = -3.1415926535;
1051
1052 int r;
1053 struct r600_bc_alu alu;
1054
1055 memset(&alu, 0, sizeof(struct r600_bc_alu));
1056 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1057 alu.is_op3 = 1;
1058
1059 alu.dst.chan = 0;
1060 alu.dst.sel = ctx->temp_reg;
1061 alu.dst.write = 1;
1062
1063 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
1064
1065 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1066 alu.src[1].chan = 0;
1067 alu.src[1].value = *(uint32_t *)&half_inv_pi;
1068 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1069 alu.src[2].chan = 0;
1070 alu.last = 1;
1071 r = r600_bc_add_alu(ctx->bc, &alu);
1072 if (r)
1073 return r;
1074
1075 memset(&alu, 0, sizeof(struct r600_bc_alu));
1076 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
1077
1078 alu.dst.chan = 0;
1079 alu.dst.sel = ctx->temp_reg;
1080 alu.dst.write = 1;
1081
1082 alu.src[0].sel = ctx->temp_reg;
1083 alu.src[0].chan = 0;
1084 alu.last = 1;
1085 r = r600_bc_add_alu(ctx->bc, &alu);
1086 if (r)
1087 return r;
1088
1089 memset(&alu, 0, sizeof(struct r600_bc_alu));
1090 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1091 alu.is_op3 = 1;
1092
1093 alu.dst.chan = 0;
1094 alu.dst.sel = ctx->temp_reg;
1095 alu.dst.write = 1;
1096
1097 alu.src[0].sel = ctx->temp_reg;
1098 alu.src[0].chan = 0;
1099
1100 alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
1101 alu.src[1].chan = 0;
1102 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1103 alu.src[2].chan = 0;
1104
1105 if (ctx->bc->chiprev == CHIPREV_R600) {
1106 alu.src[1].value = *(uint32_t *)&double_pi;
1107 alu.src[2].value = *(uint32_t *)&neg_pi;
1108 } else {
1109 alu.src[1].sel = V_SQ_ALU_SRC_1;
1110 alu.src[2].sel = V_SQ_ALU_SRC_0_5;
1111 alu.src[2].neg = 1;
1112 }
1113
1114 alu.last = 1;
1115 r = r600_bc_add_alu(ctx->bc, &alu);
1116 if (r)
1117 return r;
1118 return 0;
1119 }
1120
1121 static int tgsi_trig(struct r600_shader_ctx *ctx)
1122 {
1123 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1124 struct r600_bc_alu alu;
1125 int i, r;
1126 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1127
1128 r = tgsi_setup_trig(ctx);
1129 if (r)
1130 return r;
1131
1132 memset(&alu, 0, sizeof(struct r600_bc_alu));
1133 alu.inst = ctx->inst_info->r600_opcode;
1134 alu.dst.chan = 0;
1135 alu.dst.sel = ctx->temp_reg;
1136 alu.dst.write = 1;
1137
1138 alu.src[0].sel = ctx->temp_reg;
1139 alu.src[0].chan = 0;
1140 alu.last = 1;
1141 r = r600_bc_add_alu(ctx->bc, &alu);
1142 if (r)
1143 return r;
1144
1145 /* replicate result */
1146 for (i = 0; i < lasti + 1; i++) {
1147 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1148 continue;
1149
1150 memset(&alu, 0, sizeof(struct r600_bc_alu));
1151 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1152
1153 alu.src[0].sel = ctx->temp_reg;
1154 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1155 if (i == lasti)
1156 alu.last = 1;
1157 r = r600_bc_add_alu(ctx->bc, &alu);
1158 if (r)
1159 return r;
1160 }
1161 return 0;
1162 }
1163
1164 static int tgsi_scs(struct r600_shader_ctx *ctx)
1165 {
1166 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1167 struct r600_bc_alu alu;
1168 int r;
1169
1170 /* We'll only need the trig stuff if we are going to write to the
1171 * X or Y components of the destination vector.
1172 */
1173 if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
1174 r = tgsi_setup_trig(ctx);
1175 if (r)
1176 return r;
1177 }
1178
1179 /* dst.x = COS */
1180 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
1181 memset(&alu, 0, sizeof(struct r600_bc_alu));
1182 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
1183 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1184
1185 alu.src[0].sel = ctx->temp_reg;
1186 alu.src[0].chan = 0;
1187 alu.last = 1;
1188 r = r600_bc_add_alu(ctx->bc, &alu);
1189 if (r)
1190 return r;
1191 }
1192
1193 /* dst.y = SIN */
1194 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
1195 memset(&alu, 0, sizeof(struct r600_bc_alu));
1196 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
1197 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1198
1199 alu.src[0].sel = ctx->temp_reg;
1200 alu.src[0].chan = 0;
1201 alu.last = 1;
1202 r = r600_bc_add_alu(ctx->bc, &alu);
1203 if (r)
1204 return r;
1205 }
1206
1207 /* dst.z = 0.0; */
1208 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
1209 memset(&alu, 0, sizeof(struct r600_bc_alu));
1210
1211 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1212
1213 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1214
1215 alu.src[0].sel = V_SQ_ALU_SRC_0;
1216 alu.src[0].chan = 0;
1217
1218 alu.last = 1;
1219
1220 r = r600_bc_add_alu(ctx->bc, &alu);
1221 if (r)
1222 return r;
1223 }
1224
1225 /* dst.w = 1.0; */
1226 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
1227 memset(&alu, 0, sizeof(struct r600_bc_alu));
1228
1229 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1230
1231 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1232
1233 alu.src[0].sel = V_SQ_ALU_SRC_1;
1234 alu.src[0].chan = 0;
1235
1236 alu.last = 1;
1237
1238 r = r600_bc_add_alu(ctx->bc, &alu);
1239 if (r)
1240 return r;
1241 }
1242
1243 return 0;
1244 }
1245
1246 static int tgsi_kill(struct r600_shader_ctx *ctx)
1247 {
1248 struct r600_bc_alu alu;
1249 int i, r;
1250
1251 for (i = 0; i < 4; i++) {
1252 memset(&alu, 0, sizeof(struct r600_bc_alu));
1253 alu.inst = ctx->inst_info->r600_opcode;
1254
1255 alu.dst.chan = i;
1256
1257 alu.src[0].sel = V_SQ_ALU_SRC_0;
1258
1259 if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
1260 alu.src[1].sel = V_SQ_ALU_SRC_1;
1261 alu.src[1].neg = 1;
1262 } else {
1263 r600_bc_src(&alu.src[1], &ctx->src[0], i);
1264 }
1265 if (i == 3) {
1266 alu.last = 1;
1267 }
1268 r = r600_bc_add_alu(ctx->bc, &alu);
1269 if (r)
1270 return r;
1271 }
1272
1273 /* kill must be last in ALU */
1274 ctx->bc->force_add_cf = 1;
1275 ctx->shader->uses_kill = TRUE;
1276 return 0;
1277 }
1278
1279 static int tgsi_lit(struct r600_shader_ctx *ctx)
1280 {
1281 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1282 struct r600_bc_alu alu;
1283 int r;
1284
1285 /* dst.x, <- 1.0 */
1286 memset(&alu, 0, sizeof(struct r600_bc_alu));
1287 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1288 alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/
1289 alu.src[0].chan = 0;
1290 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
1291 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
1292 r = r600_bc_add_alu(ctx->bc, &alu);
1293 if (r)
1294 return r;
1295
1296 /* dst.y = max(src.x, 0.0) */
1297 memset(&alu, 0, sizeof(struct r600_bc_alu));
1298 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
1299 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
1300 alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
1301 alu.src[1].chan = 0;
1302 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
1303 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
1304 r = r600_bc_add_alu(ctx->bc, &alu);
1305 if (r)
1306 return r;
1307
1308 /* dst.w, <- 1.0 */
1309 memset(&alu, 0, sizeof(struct r600_bc_alu));
1310 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1311 alu.src[0].sel = V_SQ_ALU_SRC_1;
1312 alu.src[0].chan = 0;
1313 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
1314 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
1315 alu.last = 1;
1316 r = r600_bc_add_alu(ctx->bc, &alu);
1317 if (r)
1318 return r;
1319
1320 if (inst->Dst[0].Register.WriteMask & (1 << 2))
1321 {
1322 int chan;
1323 int sel;
1324
1325 /* dst.z = log(src.y) */
1326 memset(&alu, 0, sizeof(struct r600_bc_alu));
1327 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
1328 r600_bc_src(&alu.src[0], &ctx->src[0], 1);
1329 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1330 alu.last = 1;
1331 r = r600_bc_add_alu(ctx->bc, &alu);
1332 if (r)
1333 return r;
1334
1335 chan = alu.dst.chan;
1336 sel = alu.dst.sel;
1337
1338 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1339 memset(&alu, 0, sizeof(struct r600_bc_alu));
1340 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
1341 r600_bc_src(&alu.src[0], &ctx->src[0], 3);
1342 alu.src[1].sel = sel;
1343 alu.src[1].chan = chan;
1344
1345 r600_bc_src(&alu.src[2], &ctx->src[0], 0);
1346 alu.dst.sel = ctx->temp_reg;
1347 alu.dst.chan = 0;
1348 alu.dst.write = 1;
1349 alu.is_op3 = 1;
1350 alu.last = 1;
1351 r = r600_bc_add_alu(ctx->bc, &alu);
1352 if (r)
1353 return r;
1354
1355 /* dst.z = exp(tmp.x) */
1356 memset(&alu, 0, sizeof(struct r600_bc_alu));
1357 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1358 alu.src[0].sel = ctx->temp_reg;
1359 alu.src[0].chan = 0;
1360 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
1361 alu.last = 1;
1362 r = r600_bc_add_alu(ctx->bc, &alu);
1363 if (r)
1364 return r;
1365 }
1366 return 0;
1367 }
1368
1369 static int tgsi_rsq(struct r600_shader_ctx *ctx)
1370 {
1371 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1372 struct r600_bc_alu alu;
1373 int i, r;
1374
1375 memset(&alu, 0, sizeof(struct r600_bc_alu));
1376
1377 /* FIXME:
1378 * For state trackers other than OpenGL, we'll want to use
1379 * _RECIPSQRT_IEEE instead.
1380 */
1381 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED);
1382
1383 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1384 r600_bc_src(&alu.src[i], &ctx->src[i], 0);
1385 alu.src[i].abs = 1;
1386 }
1387 alu.dst.sel = ctx->temp_reg;
1388 alu.dst.write = 1;
1389 alu.last = 1;
1390 r = r600_bc_add_alu(ctx->bc, &alu);
1391 if (r)
1392 return r;
1393 /* replicate result */
1394 return tgsi_helper_tempx_replicate(ctx);
1395 }
1396
1397 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
1398 {
1399 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1400 struct r600_bc_alu alu;
1401 int i, r;
1402
1403 for (i = 0; i < 4; i++) {
1404 memset(&alu, 0, sizeof(struct r600_bc_alu));
1405 alu.src[0].sel = ctx->temp_reg;
1406 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1407 alu.dst.chan = i;
1408 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1409 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1410 if (i == 3)
1411 alu.last = 1;
1412 r = r600_bc_add_alu(ctx->bc, &alu);
1413 if (r)
1414 return r;
1415 }
1416 return 0;
1417 }
1418
1419 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
1420 {
1421 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1422 struct r600_bc_alu alu;
1423 int i, r;
1424
1425 memset(&alu, 0, sizeof(struct r600_bc_alu));
1426 alu.inst = ctx->inst_info->r600_opcode;
1427 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
1428 r600_bc_src(&alu.src[i], &ctx->src[i], 0);
1429 }
1430 alu.dst.sel = ctx->temp_reg;
1431 alu.dst.write = 1;
1432 alu.last = 1;
1433 r = r600_bc_add_alu(ctx->bc, &alu);
1434 if (r)
1435 return r;
1436 /* replicate result */
1437 return tgsi_helper_tempx_replicate(ctx);
1438 }
1439
1440 static int tgsi_pow(struct r600_shader_ctx *ctx)
1441 {
1442 struct r600_bc_alu alu;
1443 int r;
1444
1445 /* LOG2(a) */
1446 memset(&alu, 0, sizeof(struct r600_bc_alu));
1447 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
1448 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
1449 alu.dst.sel = ctx->temp_reg;
1450 alu.dst.write = 1;
1451 alu.last = 1;
1452 r = r600_bc_add_alu(ctx->bc, &alu);
1453 if (r)
1454 return r;
1455 /* b * LOG2(a) */
1456 memset(&alu, 0, sizeof(struct r600_bc_alu));
1457 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1458 r600_bc_src(&alu.src[0], &ctx->src[1], 0);
1459 alu.src[1].sel = ctx->temp_reg;
1460 alu.dst.sel = ctx->temp_reg;
1461 alu.dst.write = 1;
1462 alu.last = 1;
1463 r = r600_bc_add_alu(ctx->bc, &alu);
1464 if (r)
1465 return r;
1466 /* POW(a,b) = EXP2(b * LOG2(a))*/
1467 memset(&alu, 0, sizeof(struct r600_bc_alu));
1468 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
1469 alu.src[0].sel = ctx->temp_reg;
1470 alu.dst.sel = ctx->temp_reg;
1471 alu.dst.write = 1;
1472 alu.last = 1;
1473 r = r600_bc_add_alu(ctx->bc, &alu);
1474 if (r)
1475 return r;
1476 return tgsi_helper_tempx_replicate(ctx);
1477 }
1478
1479 static int tgsi_ssg(struct r600_shader_ctx *ctx)
1480 {
1481 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1482 struct r600_bc_alu alu;
1483 int i, r;
1484
1485 /* tmp = (src > 0 ? 1 : src) */
1486 for (i = 0; i < 4; i++) {
1487 memset(&alu, 0, sizeof(struct r600_bc_alu));
1488 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1489 alu.is_op3 = 1;
1490
1491 alu.dst.sel = ctx->temp_reg;
1492 alu.dst.chan = i;
1493
1494 r600_bc_src(&alu.src[0], &ctx->src[0], i);
1495 alu.src[1].sel = V_SQ_ALU_SRC_1;
1496 r600_bc_src(&alu.src[2], &ctx->src[0], i);
1497
1498 if (i == 3)
1499 alu.last = 1;
1500 r = r600_bc_add_alu(ctx->bc, &alu);
1501 if (r)
1502 return r;
1503 }
1504
1505 /* dst = (-tmp > 0 ? -1 : tmp) */
1506 for (i = 0; i < 4; i++) {
1507 memset(&alu, 0, sizeof(struct r600_bc_alu));
1508 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT);
1509 alu.is_op3 = 1;
1510 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1511
1512 alu.src[0].sel = ctx->temp_reg;
1513 alu.src[0].chan = i;
1514 alu.src[0].neg = 1;
1515
1516 alu.src[1].sel = V_SQ_ALU_SRC_1;
1517 alu.src[1].neg = 1;
1518
1519 alu.src[2].sel = ctx->temp_reg;
1520 alu.src[2].chan = i;
1521
1522 if (i == 3)
1523 alu.last = 1;
1524 r = r600_bc_add_alu(ctx->bc, &alu);
1525 if (r)
1526 return r;
1527 }
1528 return 0;
1529 }
1530
1531 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
1532 {
1533 struct r600_bc_alu alu;
1534 int i, r;
1535
1536 for (i = 0; i < 4; i++) {
1537 memset(&alu, 0, sizeof(struct r600_bc_alu));
1538 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
1539 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP);
1540 alu.dst.chan = i;
1541 } else {
1542 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1543 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1544 alu.src[0].sel = ctx->temp_reg;
1545 alu.src[0].chan = i;
1546 }
1547 if (i == 3) {
1548 alu.last = 1;
1549 }
1550 r = r600_bc_add_alu(ctx->bc, &alu);
1551 if (r)
1552 return r;
1553 }
1554 return 0;
1555 }
1556
1557 static int tgsi_op3(struct r600_shader_ctx *ctx)
1558 {
1559 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1560 struct r600_bc_alu alu;
1561 int i, j, r;
1562 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1563
1564 for (i = 0; i < lasti + 1; i++) {
1565 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1566 continue;
1567
1568 memset(&alu, 0, sizeof(struct r600_bc_alu));
1569 alu.inst = ctx->inst_info->r600_opcode;
1570 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1571 r600_bc_src(&alu.src[j], &ctx->src[j], i);
1572 }
1573
1574 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1575 alu.dst.chan = i;
1576 alu.dst.write = 1;
1577 alu.is_op3 = 1;
1578 if (i == lasti) {
1579 alu.last = 1;
1580 }
1581 r = r600_bc_add_alu(ctx->bc, &alu);
1582 if (r)
1583 return r;
1584 }
1585 return 0;
1586 }
1587
1588 static int tgsi_dp(struct r600_shader_ctx *ctx)
1589 {
1590 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1591 struct r600_bc_alu alu;
1592 int i, j, r;
1593
1594 for (i = 0; i < 4; i++) {
1595 memset(&alu, 0, sizeof(struct r600_bc_alu));
1596 alu.inst = ctx->inst_info->r600_opcode;
1597 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
1598 r600_bc_src(&alu.src[j], &ctx->src[j], i);
1599 }
1600
1601 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1602 alu.dst.chan = i;
1603 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
1604 /* handle some special cases */
1605 switch (ctx->inst_info->tgsi_opcode) {
1606 case TGSI_OPCODE_DP2:
1607 if (i > 1) {
1608 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1609 alu.src[0].chan = alu.src[1].chan = 0;
1610 }
1611 break;
1612 case TGSI_OPCODE_DP3:
1613 if (i > 2) {
1614 alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
1615 alu.src[0].chan = alu.src[1].chan = 0;
1616 }
1617 break;
1618 case TGSI_OPCODE_DPH:
1619 if (i == 3) {
1620 alu.src[0].sel = V_SQ_ALU_SRC_1;
1621 alu.src[0].chan = 0;
1622 alu.src[0].neg = 0;
1623 }
1624 break;
1625 default:
1626 break;
1627 }
1628 if (i == 3) {
1629 alu.last = 1;
1630 }
1631 r = r600_bc_add_alu(ctx->bc, &alu);
1632 if (r)
1633 return r;
1634 }
1635 return 0;
1636 }
1637
1638 static int tgsi_tex(struct r600_shader_ctx *ctx)
1639 {
1640 static float one_point_five = 1.5f;
1641 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1642 struct r600_bc_tex tex;
1643 struct r600_bc_alu alu;
1644 unsigned src_gpr;
1645 int r, i;
1646 int opcode;
1647 boolean src_not_temp =
1648 inst->Src[0].Register.File != TGSI_FILE_TEMPORARY &&
1649 inst->Src[0].Register.File != TGSI_FILE_INPUT;
1650
1651 src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
1652
1653 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
1654 /* Add perspective divide */
1655 memset(&alu, 0, sizeof(struct r600_bc_alu));
1656 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1657 r600_bc_src(&alu.src[0], &ctx->src[0], 3);
1658
1659 alu.dst.sel = ctx->temp_reg;
1660 alu.dst.chan = 3;
1661 alu.last = 1;
1662 alu.dst.write = 1;
1663 r = r600_bc_add_alu(ctx->bc, &alu);
1664 if (r)
1665 return r;
1666
1667 for (i = 0; i < 3; i++) {
1668 memset(&alu, 0, sizeof(struct r600_bc_alu));
1669 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1670 alu.src[0].sel = ctx->temp_reg;
1671 alu.src[0].chan = 3;
1672 r600_bc_src(&alu.src[1], &ctx->src[0], i);
1673 alu.dst.sel = ctx->temp_reg;
1674 alu.dst.chan = i;
1675 alu.dst.write = 1;
1676 r = r600_bc_add_alu(ctx->bc, &alu);
1677 if (r)
1678 return r;
1679 }
1680 memset(&alu, 0, sizeof(struct r600_bc_alu));
1681 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1682 alu.src[0].sel = V_SQ_ALU_SRC_1;
1683 alu.src[0].chan = 0;
1684 alu.dst.sel = ctx->temp_reg;
1685 alu.dst.chan = 3;
1686 alu.last = 1;
1687 alu.dst.write = 1;
1688 r = r600_bc_add_alu(ctx->bc, &alu);
1689 if (r)
1690 return r;
1691 src_not_temp = FALSE;
1692 src_gpr = ctx->temp_reg;
1693 }
1694
1695 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1696 int src_chan, src2_chan;
1697
1698 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1699 for (i = 0; i < 4; i++) {
1700 memset(&alu, 0, sizeof(struct r600_bc_alu));
1701 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE);
1702 switch (i) {
1703 case 0:
1704 src_chan = 2;
1705 src2_chan = 1;
1706 break;
1707 case 1:
1708 src_chan = 2;
1709 src2_chan = 0;
1710 break;
1711 case 2:
1712 src_chan = 0;
1713 src2_chan = 2;
1714 break;
1715 case 3:
1716 src_chan = 1;
1717 src2_chan = 2;
1718 break;
1719 default:
1720 assert(0);
1721 src_chan = 0;
1722 src2_chan = 0;
1723 break;
1724 }
1725 r600_bc_src(&alu.src[0], &ctx->src[0], src_chan);
1726 r600_bc_src(&alu.src[1], &ctx->src[0], src2_chan);
1727 alu.dst.sel = ctx->temp_reg;
1728 alu.dst.chan = i;
1729 if (i == 3)
1730 alu.last = 1;
1731 alu.dst.write = 1;
1732 r = r600_bc_add_alu(ctx->bc, &alu);
1733 if (r)
1734 return r;
1735 }
1736
1737 /* tmp1.z = RCP_e(|tmp1.z|) */
1738 memset(&alu, 0, sizeof(struct r600_bc_alu));
1739 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
1740 alu.src[0].sel = ctx->temp_reg;
1741 alu.src[0].chan = 2;
1742 alu.src[0].abs = 1;
1743 alu.dst.sel = ctx->temp_reg;
1744 alu.dst.chan = 2;
1745 alu.dst.write = 1;
1746 alu.last = 1;
1747 r = r600_bc_add_alu(ctx->bc, &alu);
1748 if (r)
1749 return r;
1750
1751 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1752 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1753 * muladd has no writemask, have to use another temp
1754 */
1755 memset(&alu, 0, sizeof(struct r600_bc_alu));
1756 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1757 alu.is_op3 = 1;
1758
1759 alu.src[0].sel = ctx->temp_reg;
1760 alu.src[0].chan = 0;
1761 alu.src[1].sel = ctx->temp_reg;
1762 alu.src[1].chan = 2;
1763
1764 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1765 alu.src[2].chan = 0;
1766 alu.src[2].value = *(uint32_t *)&one_point_five;
1767
1768 alu.dst.sel = ctx->temp_reg;
1769 alu.dst.chan = 0;
1770 alu.dst.write = 1;
1771
1772 r = r600_bc_add_alu(ctx->bc, &alu);
1773 if (r)
1774 return r;
1775
1776 memset(&alu, 0, sizeof(struct r600_bc_alu));
1777 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1778 alu.is_op3 = 1;
1779
1780 alu.src[0].sel = ctx->temp_reg;
1781 alu.src[0].chan = 1;
1782 alu.src[1].sel = ctx->temp_reg;
1783 alu.src[1].chan = 2;
1784
1785 alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
1786 alu.src[2].chan = 0;
1787 alu.src[2].value = *(uint32_t *)&one_point_five;
1788
1789 alu.dst.sel = ctx->temp_reg;
1790 alu.dst.chan = 1;
1791 alu.dst.write = 1;
1792
1793 alu.last = 1;
1794 r = r600_bc_add_alu(ctx->bc, &alu);
1795 if (r)
1796 return r;
1797
1798 src_not_temp = FALSE;
1799 src_gpr = ctx->temp_reg;
1800 }
1801
1802 if (src_not_temp) {
1803 for (i = 0; i < 4; i++) {
1804 memset(&alu, 0, sizeof(struct r600_bc_alu));
1805 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
1806 r600_bc_src(&alu.src[0], &ctx->src[0], i);
1807 alu.dst.sel = ctx->temp_reg;
1808 alu.dst.chan = i;
1809 if (i == 3)
1810 alu.last = 1;
1811 alu.dst.write = 1;
1812 r = r600_bc_add_alu(ctx->bc, &alu);
1813 if (r)
1814 return r;
1815 }
1816 src_gpr = ctx->temp_reg;
1817 }
1818
1819 opcode = ctx->inst_info->r600_opcode;
1820 if (opcode == SQ_TEX_INST_SAMPLE &&
1821 (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
1822 opcode = SQ_TEX_INST_SAMPLE_C;
1823
1824 memset(&tex, 0, sizeof(struct r600_bc_tex));
1825 tex.inst = opcode;
1826 tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
1827 tex.resource_id = tex.sampler_id + R600_MAX_CONST_BUFFERS;
1828 tex.src_gpr = src_gpr;
1829 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
1830 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
1831 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
1832 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
1833 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
1834 tex.src_sel_x = 0;
1835 tex.src_sel_y = 1;
1836 tex.src_sel_z = 2;
1837 tex.src_sel_w = 3;
1838
1839 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
1840 tex.src_sel_x = 1;
1841 tex.src_sel_y = 0;
1842 tex.src_sel_z = 3;
1843 tex.src_sel_w = 1;
1844 }
1845
1846 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
1847 tex.coord_type_x = 1;
1848 tex.coord_type_y = 1;
1849 tex.coord_type_z = 1;
1850 tex.coord_type_w = 1;
1851 }
1852
1853 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY) {
1854 tex.coord_type_z = 0;
1855 tex.src_sel_z = 1;
1856 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY)
1857 tex.coord_type_z = 0;
1858
1859 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
1860 tex.src_sel_w = 2;
1861
1862 r = r600_bc_add_tex(ctx->bc, &tex);
1863 if (r)
1864 return r;
1865
1866 /* add shadow ambient support - gallium doesn't do it yet */
1867 return 0;
1868 }
1869
1870 static int tgsi_lrp(struct r600_shader_ctx *ctx)
1871 {
1872 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1873 struct r600_bc_alu alu;
1874 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1875 unsigned i;
1876 int r;
1877
1878 /* optimize if it's just an equal balance */
1879 if (ctx->src[0].sel == V_SQ_ALU_SRC_0_5) {
1880 for (i = 0; i < lasti + 1; i++) {
1881 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1882 continue;
1883
1884 memset(&alu, 0, sizeof(struct r600_bc_alu));
1885 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1886 r600_bc_src(&alu.src[0], &ctx->src[1], i);
1887 r600_bc_src(&alu.src[1], &ctx->src[2], i);
1888 alu.omod = 3;
1889 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1890 alu.dst.chan = i;
1891 if (i == lasti) {
1892 alu.last = 1;
1893 }
1894 r = r600_bc_add_alu(ctx->bc, &alu);
1895 if (r)
1896 return r;
1897 }
1898 return 0;
1899 }
1900
1901 /* 1 - src0 */
1902 for (i = 0; i < lasti + 1; i++) {
1903 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1904 continue;
1905
1906 memset(&alu, 0, sizeof(struct r600_bc_alu));
1907 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD);
1908 alu.src[0].sel = V_SQ_ALU_SRC_1;
1909 alu.src[0].chan = 0;
1910 r600_bc_src(&alu.src[1], &ctx->src[0], i);
1911 alu.src[1].neg = 1;
1912 alu.dst.sel = ctx->temp_reg;
1913 alu.dst.chan = i;
1914 if (i == lasti) {
1915 alu.last = 1;
1916 }
1917 alu.dst.write = 1;
1918 r = r600_bc_add_alu(ctx->bc, &alu);
1919 if (r)
1920 return r;
1921 }
1922
1923 /* (1 - src0) * src2 */
1924 for (i = 0; i < lasti + 1; i++) {
1925 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1926 continue;
1927
1928 memset(&alu, 0, sizeof(struct r600_bc_alu));
1929 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
1930 alu.src[0].sel = ctx->temp_reg;
1931 alu.src[0].chan = i;
1932 r600_bc_src(&alu.src[1], &ctx->src[2], i);
1933 alu.dst.sel = ctx->temp_reg;
1934 alu.dst.chan = i;
1935 if (i == lasti) {
1936 alu.last = 1;
1937 }
1938 alu.dst.write = 1;
1939 r = r600_bc_add_alu(ctx->bc, &alu);
1940 if (r)
1941 return r;
1942 }
1943
1944 /* src0 * src1 + (1 - src0) * src2 */
1945 for (i = 0; i < lasti + 1; i++) {
1946 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1947 continue;
1948
1949 memset(&alu, 0, sizeof(struct r600_bc_alu));
1950 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
1951 alu.is_op3 = 1;
1952 r600_bc_src(&alu.src[0], &ctx->src[0], i);
1953 r600_bc_src(&alu.src[1], &ctx->src[1], i);
1954 alu.src[2].sel = ctx->temp_reg;
1955 alu.src[2].chan = i;
1956
1957 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1958 alu.dst.chan = i;
1959 if (i == lasti) {
1960 alu.last = 1;
1961 }
1962 r = r600_bc_add_alu(ctx->bc, &alu);
1963 if (r)
1964 return r;
1965 }
1966 return 0;
1967 }
1968
1969 static int tgsi_cmp(struct r600_shader_ctx *ctx)
1970 {
1971 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1972 struct r600_bc_alu alu;
1973 int i, r;
1974 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
1975
1976 for (i = 0; i < lasti + 1; i++) {
1977 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
1978 continue;
1979
1980 memset(&alu, 0, sizeof(struct r600_bc_alu));
1981 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE);
1982 r600_bc_src(&alu.src[0], &ctx->src[0], i);
1983 r600_bc_src(&alu.src[1], &ctx->src[2], i);
1984 r600_bc_src(&alu.src[2], &ctx->src[1], i);
1985 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
1986 alu.dst.chan = i;
1987 alu.dst.write = 1;
1988 alu.is_op3 = 1;
1989 if (i == lasti)
1990 alu.last = 1;
1991 r = r600_bc_add_alu(ctx->bc, &alu);
1992 if (r)
1993 return r;
1994 }
1995 return 0;
1996 }
1997
1998 static int tgsi_xpd(struct r600_shader_ctx *ctx)
1999 {
2000 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2001 struct r600_bc_alu alu;
2002 uint32_t use_temp = 0;
2003 int i, r;
2004
2005 if (inst->Dst[0].Register.WriteMask != 0xf)
2006 use_temp = 1;
2007
2008 for (i = 0; i < 4; i++) {
2009 memset(&alu, 0, sizeof(struct r600_bc_alu));
2010 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2011
2012 switch (i) {
2013 case 0:
2014 r600_bc_src(&alu.src[0], &ctx->src[0], 2);
2015 break;
2016 case 1:
2017 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2018 break;
2019 case 2:
2020 r600_bc_src(&alu.src[0], &ctx->src[0], 1);
2021 break;
2022 case 3:
2023 alu.src[0].sel = V_SQ_ALU_SRC_0;
2024 alu.src[0].chan = i;
2025 }
2026
2027 switch (i) {
2028 case 0:
2029 r600_bc_src(&alu.src[1], &ctx->src[1], 1);
2030 break;
2031 case 1:
2032 r600_bc_src(&alu.src[1], &ctx->src[1], 2);
2033 break;
2034 case 2:
2035 r600_bc_src(&alu.src[1], &ctx->src[1], 0);
2036 break;
2037 case 3:
2038 alu.src[1].sel = V_SQ_ALU_SRC_0;
2039 alu.src[1].chan = i;
2040 }
2041
2042 alu.dst.sel = ctx->temp_reg;
2043 alu.dst.chan = i;
2044 alu.dst.write = 1;
2045
2046 if (i == 3)
2047 alu.last = 1;
2048 r = r600_bc_add_alu(ctx->bc, &alu);
2049 if (r)
2050 return r;
2051 }
2052
2053 for (i = 0; i < 4; i++) {
2054 memset(&alu, 0, sizeof(struct r600_bc_alu));
2055 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD);
2056
2057 switch (i) {
2058 case 0:
2059 r600_bc_src(&alu.src[0], &ctx->src[0], 1);
2060 break;
2061 case 1:
2062 r600_bc_src(&alu.src[0], &ctx->src[0], 2);
2063 break;
2064 case 2:
2065 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2066 break;
2067 case 3:
2068 alu.src[0].sel = V_SQ_ALU_SRC_0;
2069 alu.src[0].chan = i;
2070 }
2071
2072 switch (i) {
2073 case 0:
2074 r600_bc_src(&alu.src[1], &ctx->src[1], 2);
2075 break;
2076 case 1:
2077 r600_bc_src(&alu.src[1], &ctx->src[1], 0);
2078 break;
2079 case 2:
2080 r600_bc_src(&alu.src[1], &ctx->src[1], 1);
2081 break;
2082 case 3:
2083 alu.src[1].sel = V_SQ_ALU_SRC_0;
2084 alu.src[1].chan = i;
2085 }
2086
2087 alu.src[2].sel = ctx->temp_reg;
2088 alu.src[2].neg = 1;
2089 alu.src[2].chan = i;
2090
2091 if (use_temp)
2092 alu.dst.sel = ctx->temp_reg;
2093 else
2094 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2095 alu.dst.chan = i;
2096 alu.dst.write = 1;
2097 alu.is_op3 = 1;
2098 if (i == 3)
2099 alu.last = 1;
2100 r = r600_bc_add_alu(ctx->bc, &alu);
2101 if (r)
2102 return r;
2103 }
2104 if (use_temp)
2105 return tgsi_helper_copy(ctx, inst);
2106 return 0;
2107 }
2108
2109 static int tgsi_exp(struct r600_shader_ctx *ctx)
2110 {
2111 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2112 struct r600_bc_alu alu;
2113 int r;
2114
2115 /* result.x = 2^floor(src); */
2116 if (inst->Dst[0].Register.WriteMask & 1) {
2117 memset(&alu, 0, sizeof(struct r600_bc_alu));
2118
2119 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2120 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2121
2122 alu.dst.sel = ctx->temp_reg;
2123 alu.dst.chan = 0;
2124 alu.dst.write = 1;
2125 alu.last = 1;
2126 r = r600_bc_add_alu(ctx->bc, &alu);
2127 if (r)
2128 return r;
2129
2130 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2131 alu.src[0].sel = ctx->temp_reg;
2132 alu.src[0].chan = 0;
2133
2134 alu.dst.sel = ctx->temp_reg;
2135 alu.dst.chan = 0;
2136 alu.dst.write = 1;
2137 alu.last = 1;
2138 r = r600_bc_add_alu(ctx->bc, &alu);
2139 if (r)
2140 return r;
2141 }
2142
2143 /* result.y = tmp - floor(tmp); */
2144 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2145 memset(&alu, 0, sizeof(struct r600_bc_alu));
2146
2147 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT);
2148 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2149
2150 alu.dst.sel = ctx->temp_reg;
2151 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2152 // if (r)
2153 // return r;
2154 alu.dst.write = 1;
2155 alu.dst.chan = 1;
2156
2157 alu.last = 1;
2158
2159 r = r600_bc_add_alu(ctx->bc, &alu);
2160 if (r)
2161 return r;
2162 }
2163
2164 /* result.z = RoughApprox2ToX(tmp);*/
2165 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
2166 memset(&alu, 0, sizeof(struct r600_bc_alu));
2167 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2168 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2169
2170 alu.dst.sel = ctx->temp_reg;
2171 alu.dst.write = 1;
2172 alu.dst.chan = 2;
2173
2174 alu.last = 1;
2175
2176 r = r600_bc_add_alu(ctx->bc, &alu);
2177 if (r)
2178 return r;
2179 }
2180
2181 /* result.w = 1.0;*/
2182 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
2183 memset(&alu, 0, sizeof(struct r600_bc_alu));
2184
2185 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2186 alu.src[0].sel = V_SQ_ALU_SRC_1;
2187 alu.src[0].chan = 0;
2188
2189 alu.dst.sel = ctx->temp_reg;
2190 alu.dst.chan = 3;
2191 alu.dst.write = 1;
2192 alu.last = 1;
2193 r = r600_bc_add_alu(ctx->bc, &alu);
2194 if (r)
2195 return r;
2196 }
2197 return tgsi_helper_copy(ctx, inst);
2198 }
2199
2200 static int tgsi_log(struct r600_shader_ctx *ctx)
2201 {
2202 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2203 struct r600_bc_alu alu;
2204 int r;
2205
2206 /* result.x = floor(log2(src)); */
2207 if (inst->Dst[0].Register.WriteMask & 1) {
2208 memset(&alu, 0, sizeof(struct r600_bc_alu));
2209
2210 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2211 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2212
2213 alu.dst.sel = ctx->temp_reg;
2214 alu.dst.chan = 0;
2215 alu.dst.write = 1;
2216 alu.last = 1;
2217 r = r600_bc_add_alu(ctx->bc, &alu);
2218 if (r)
2219 return r;
2220
2221 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2222 alu.src[0].sel = ctx->temp_reg;
2223 alu.src[0].chan = 0;
2224
2225 alu.dst.sel = ctx->temp_reg;
2226 alu.dst.chan = 0;
2227 alu.dst.write = 1;
2228 alu.last = 1;
2229
2230 r = r600_bc_add_alu(ctx->bc, &alu);
2231 if (r)
2232 return r;
2233 }
2234
2235 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2236 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
2237 memset(&alu, 0, sizeof(struct r600_bc_alu));
2238
2239 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2240 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2241
2242 alu.dst.sel = ctx->temp_reg;
2243 alu.dst.chan = 1;
2244 alu.dst.write = 1;
2245 alu.last = 1;
2246
2247 r = r600_bc_add_alu(ctx->bc, &alu);
2248 if (r)
2249 return r;
2250
2251 memset(&alu, 0, sizeof(struct r600_bc_alu));
2252
2253 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR);
2254 alu.src[0].sel = ctx->temp_reg;
2255 alu.src[0].chan = 1;
2256
2257 alu.dst.sel = ctx->temp_reg;
2258 alu.dst.chan = 1;
2259 alu.dst.write = 1;
2260 alu.last = 1;
2261
2262 r = r600_bc_add_alu(ctx->bc, &alu);
2263 if (r)
2264 return r;
2265
2266 memset(&alu, 0, sizeof(struct r600_bc_alu));
2267
2268 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
2269 alu.src[0].sel = ctx->temp_reg;
2270 alu.src[0].chan = 1;
2271
2272 alu.dst.sel = ctx->temp_reg;
2273 alu.dst.chan = 1;
2274 alu.dst.write = 1;
2275 alu.last = 1;
2276
2277 r = r600_bc_add_alu(ctx->bc, &alu);
2278 if (r)
2279 return r;
2280
2281 memset(&alu, 0, sizeof(struct r600_bc_alu));
2282
2283 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
2284 alu.src[0].sel = ctx->temp_reg;
2285 alu.src[0].chan = 1;
2286
2287 alu.dst.sel = ctx->temp_reg;
2288 alu.dst.chan = 1;
2289 alu.dst.write = 1;
2290 alu.last = 1;
2291
2292 r = r600_bc_add_alu(ctx->bc, &alu);
2293 if (r)
2294 return r;
2295
2296 memset(&alu, 0, sizeof(struct r600_bc_alu));
2297
2298 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2299
2300 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2301
2302 alu.src[1].sel = ctx->temp_reg;
2303 alu.src[1].chan = 1;
2304
2305 alu.dst.sel = ctx->temp_reg;
2306 alu.dst.chan = 1;
2307 alu.dst.write = 1;
2308 alu.last = 1;
2309
2310 r = r600_bc_add_alu(ctx->bc, &alu);
2311 if (r)
2312 return r;
2313 }
2314
2315 /* result.z = log2(src);*/
2316 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
2317 memset(&alu, 0, sizeof(struct r600_bc_alu));
2318
2319 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
2320 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2321
2322 alu.dst.sel = ctx->temp_reg;
2323 alu.dst.write = 1;
2324 alu.dst.chan = 2;
2325 alu.last = 1;
2326
2327 r = r600_bc_add_alu(ctx->bc, &alu);
2328 if (r)
2329 return r;
2330 }
2331
2332 /* result.w = 1.0; */
2333 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
2334 memset(&alu, 0, sizeof(struct r600_bc_alu));
2335
2336 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
2337 alu.src[0].sel = V_SQ_ALU_SRC_1;
2338 alu.src[0].chan = 0;
2339
2340 alu.dst.sel = ctx->temp_reg;
2341 alu.dst.chan = 3;
2342 alu.dst.write = 1;
2343 alu.last = 1;
2344
2345 r = r600_bc_add_alu(ctx->bc, &alu);
2346 if (r)
2347 return r;
2348 }
2349
2350 return tgsi_helper_copy(ctx, inst);
2351 }
2352
2353 static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
2354 {
2355 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2356 struct r600_bc_alu alu;
2357 int r;
2358
2359 memset(&alu, 0, sizeof(struct r600_bc_alu));
2360
2361 switch (inst->Instruction.Opcode) {
2362 case TGSI_OPCODE_ARL:
2363 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
2364 break;
2365 case TGSI_OPCODE_ARR:
2366 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2367 break;
2368 default:
2369 assert(0);
2370 return -1;
2371 }
2372
2373 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2374 alu.last = 1;
2375 alu.dst.sel = ctx->ar_reg;
2376 alu.dst.write = 1;
2377 r = r600_bc_add_alu(ctx->bc, &alu);
2378 if (r)
2379 return r;
2380
2381 /* TODO: Note that the MOVA can be avoided if we never use AR for
2382 * indexing non-CB registers in the current ALU clause. Similarly, we
2383 * need to load AR from ar_reg again if we started a new clause
2384 * between ARL and AR usage. The easy way to do that is to remove
2385 * the MOVA here, and load it for the first AR access after ar_reg
2386 * has been modified in each clause. */
2387 memset(&alu, 0, sizeof(struct r600_bc_alu));
2388 alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2389 alu.src[0].sel = ctx->ar_reg;
2390 alu.src[0].chan = 0;
2391 alu.last = 1;
2392 r = r600_bc_add_alu(ctx->bc, &alu);
2393 if (r)
2394 return r;
2395 return 0;
2396 }
2397 static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
2398 {
2399 /* TODO from r600c, ar values don't persist between clauses */
2400 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2401 struct r600_bc_alu alu;
2402 int r;
2403
2404 switch (inst->Instruction.Opcode) {
2405 case TGSI_OPCODE_ARL:
2406 memset(&alu, 0, sizeof(alu));
2407 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
2408 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2409 alu.dst.sel = ctx->ar_reg;
2410 alu.dst.write = 1;
2411 alu.last = 1;
2412
2413 if ((r = r600_bc_add_alu(ctx->bc, &alu)))
2414 return r;
2415
2416 memset(&alu, 0, sizeof(alu));
2417 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2418 alu.src[0].sel = ctx->ar_reg;
2419 alu.dst.sel = ctx->ar_reg;
2420 alu.dst.write = 1;
2421 alu.last = 1;
2422
2423 if ((r = r600_bc_add_alu(ctx->bc, &alu)))
2424 return r;
2425 break;
2426 case TGSI_OPCODE_ARR:
2427 memset(&alu, 0, sizeof(alu));
2428 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT;
2429 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2430 alu.dst.sel = ctx->ar_reg;
2431 alu.dst.write = 1;
2432 alu.last = 1;
2433
2434 if ((r = r600_bc_add_alu(ctx->bc, &alu)))
2435 return r;
2436 break;
2437 default:
2438 assert(0);
2439 return -1;
2440 }
2441
2442 memset(&alu, 0, sizeof(alu));
2443 alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
2444 alu.src[0].sel = ctx->ar_reg;
2445 alu.last = 1;
2446
2447 r = r600_bc_add_alu(ctx->bc, &alu);
2448 if (r)
2449 return r;
2450 ctx->bc->cf_last->r6xx_uses_waterfall = 1;
2451 return 0;
2452 }
2453
2454 static int tgsi_opdst(struct r600_shader_ctx *ctx)
2455 {
2456 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2457 struct r600_bc_alu alu;
2458 int i, r = 0;
2459
2460 for (i = 0; i < 4; i++) {
2461 memset(&alu, 0, sizeof(struct r600_bc_alu));
2462
2463 alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
2464 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2465
2466 if (i == 0 || i == 3) {
2467 alu.src[0].sel = V_SQ_ALU_SRC_1;
2468 } else {
2469 r600_bc_src(&alu.src[0], &ctx->src[0], i);
2470 }
2471
2472 if (i == 0 || i == 2) {
2473 alu.src[1].sel = V_SQ_ALU_SRC_1;
2474 } else {
2475 r600_bc_src(&alu.src[1], &ctx->src[1], i);
2476 }
2477 if (i == 3)
2478 alu.last = 1;
2479 r = r600_bc_add_alu(ctx->bc, &alu);
2480 if (r)
2481 return r;
2482 }
2483 return 0;
2484 }
2485
2486 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
2487 {
2488 struct r600_bc_alu alu;
2489 int r;
2490
2491 memset(&alu, 0, sizeof(struct r600_bc_alu));
2492 alu.inst = opcode;
2493 alu.predicate = 1;
2494
2495 alu.dst.sel = ctx->temp_reg;
2496 alu.dst.write = 1;
2497 alu.dst.chan = 0;
2498
2499 r600_bc_src(&alu.src[0], &ctx->src[0], 0);
2500 alu.src[1].sel = V_SQ_ALU_SRC_0;
2501 alu.src[1].chan = 0;
2502
2503 alu.last = 1;
2504
2505 r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE));
2506 if (r)
2507 return r;
2508 return 0;
2509 }
2510
2511 static int pops(struct r600_shader_ctx *ctx, int pops)
2512 {
2513 int alu_pop = 3;
2514 if (ctx->bc->cf_last) {
2515 if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU) << 3)
2516 alu_pop = 0;
2517 else if (ctx->bc->cf_last->inst == CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3)
2518 alu_pop = 1;
2519 }
2520 alu_pop += pops;
2521 if (alu_pop == 1) {
2522 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER) << 3;
2523 ctx->bc->force_add_cf = 1;
2524 } else if (alu_pop == 2) {
2525 ctx->bc->cf_last->inst = CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER) << 3;
2526 ctx->bc->force_add_cf = 1;
2527 } else {
2528 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
2529 ctx->bc->cf_last->pop_count = pops;
2530 ctx->bc->cf_last->cf_addr = ctx->bc->cf_last->id + 2;
2531 }
2532 return 0;
2533 }
2534
2535 static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
2536 {
2537 switch(reason) {
2538 case FC_PUSH_VPM:
2539 ctx->bc->callstack[ctx->bc->call_sp].current--;
2540 break;
2541 case FC_PUSH_WQM:
2542 case FC_LOOP:
2543 ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
2544 break;
2545 case FC_REP:
2546 /* TOODO : for 16 vp asic should -= 2; */
2547 ctx->bc->callstack[ctx->bc->call_sp].current --;
2548 break;
2549 }
2550 }
2551
2552 static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
2553 {
2554 if (check_max_only) {
2555 int diff;
2556 switch (reason) {
2557 case FC_PUSH_VPM:
2558 diff = 1;
2559 break;
2560 case FC_PUSH_WQM:
2561 diff = 4;
2562 break;
2563 default:
2564 assert(0);
2565 diff = 0;
2566 }
2567 if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
2568 ctx->bc->callstack[ctx->bc->call_sp].max) {
2569 ctx->bc->callstack[ctx->bc->call_sp].max =
2570 ctx->bc->callstack[ctx->bc->call_sp].current + diff;
2571 }
2572 return;
2573 }
2574 switch (reason) {
2575 case FC_PUSH_VPM:
2576 ctx->bc->callstack[ctx->bc->call_sp].current++;
2577 break;
2578 case FC_PUSH_WQM:
2579 case FC_LOOP:
2580 ctx->bc->callstack[ctx->bc->call_sp].current += 4;
2581 break;
2582 case FC_REP:
2583 ctx->bc->callstack[ctx->bc->call_sp].current++;
2584 break;
2585 }
2586
2587 if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
2588 ctx->bc->callstack[ctx->bc->call_sp].max) {
2589 ctx->bc->callstack[ctx->bc->call_sp].max =
2590 ctx->bc->callstack[ctx->bc->call_sp].current;
2591 }
2592 }
2593
2594 static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
2595 {
2596 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
2597
2598 sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
2599 sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
2600 sp->mid[sp->num_mid] = ctx->bc->cf_last;
2601 sp->num_mid++;
2602 }
2603
2604 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
2605 {
2606 ctx->bc->fc_sp++;
2607 ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
2608 ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
2609 }
2610
2611 static void fc_poplevel(struct r600_shader_ctx *ctx)
2612 {
2613 struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
2614 if (sp->mid) {
2615 free(sp->mid);
2616 sp->mid = NULL;
2617 }
2618 sp->num_mid = 0;
2619 sp->start = NULL;
2620 sp->type = 0;
2621 ctx->bc->fc_sp--;
2622 }
2623
2624 #if 0
2625 static int emit_return(struct r600_shader_ctx *ctx)
2626 {
2627 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
2628 return 0;
2629 }
2630
2631 static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
2632 {
2633
2634 r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
2635 ctx->bc->cf_last->pop_count = pops;
2636 /* TODO work out offset */
2637 return 0;
2638 }
2639
2640 static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
2641 {
2642 return 0;
2643 }
2644
2645 static void emit_testflag(struct r600_shader_ctx *ctx)
2646 {
2647
2648 }
2649
2650 static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
2651 {
2652 emit_testflag(ctx);
2653 emit_jump_to_offset(ctx, 1, 4);
2654 emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
2655 pops(ctx, ifidx + 1);
2656 emit_return(ctx);
2657 }
2658
2659 static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
2660 {
2661 emit_testflag(ctx);
2662
2663 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2664 ctx->bc->cf_last->pop_count = 1;
2665
2666 fc_set_mid(ctx, fc_sp);
2667
2668 pops(ctx, 1);
2669 }
2670 #endif
2671
2672 static int tgsi_if(struct r600_shader_ctx *ctx)
2673 {
2674 emit_logic_pred(ctx, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
2675
2676 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
2677
2678 fc_pushlevel(ctx, FC_IF);
2679
2680 callstack_check_depth(ctx, FC_PUSH_VPM, 0);
2681 return 0;
2682 }
2683
2684 static int tgsi_else(struct r600_shader_ctx *ctx)
2685 {
2686 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE));
2687 ctx->bc->cf_last->pop_count = 1;
2688
2689 fc_set_mid(ctx, ctx->bc->fc_sp);
2690 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
2691 return 0;
2692 }
2693
2694 static int tgsi_endif(struct r600_shader_ctx *ctx)
2695 {
2696 pops(ctx, 1);
2697 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
2698 R600_ERR("if/endif unbalanced in shader\n");
2699 return -1;
2700 }
2701
2702 if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
2703 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2704 ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
2705 } else {
2706 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
2707 }
2708 fc_poplevel(ctx);
2709
2710 callstack_decrease_current(ctx, FC_PUSH_VPM);
2711 return 0;
2712 }
2713
2714 static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
2715 {
2716 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL));
2717
2718 fc_pushlevel(ctx, FC_LOOP);
2719
2720 /* check stack depth */
2721 callstack_check_depth(ctx, FC_LOOP, 0);
2722 return 0;
2723 }
2724
2725 static int tgsi_endloop(struct r600_shader_ctx *ctx)
2726 {
2727 int i;
2728
2729 r600_bc_add_cfinst(ctx->bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END));
2730
2731 if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
2732 R600_ERR("loop/endloop in shader code are not paired.\n");
2733 return -EINVAL;
2734 }
2735
2736 /* fixup loop pointers - from r600isa
2737 LOOP END points to CF after LOOP START,
2738 LOOP START point to CF after LOOP END
2739 BRK/CONT point to LOOP END CF
2740 */
2741 ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
2742
2743 ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
2744
2745 for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
2746 ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
2747 }
2748 /* TODO add LOOPRET support */
2749 fc_poplevel(ctx);
2750 callstack_decrease_current(ctx, FC_LOOP);
2751 return 0;
2752 }
2753
2754 static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
2755 {
2756 unsigned int fscp;
2757
2758 for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
2759 {
2760 if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
2761 break;
2762 }
2763
2764 if (fscp == 0) {
2765 R600_ERR("Break not inside loop/endloop pair\n");
2766 return -EINVAL;
2767 }
2768
2769 r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
2770 ctx->bc->cf_last->pop_count = 1;
2771
2772 fc_set_mid(ctx, fscp);
2773
2774 pops(ctx, 1);
2775 callstack_check_depth(ctx, FC_PUSH_VPM, 1);
2776 return 0;
2777 }
2778
2779 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
2780 {TGSI_OPCODE_ARL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2781 {TGSI_OPCODE_MOV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2782 {TGSI_OPCODE_LIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2783
2784 /* FIXME:
2785 * For state trackers other than OpenGL, we'll want to use
2786 * _RECIP_IEEE instead.
2787 */
2788 {TGSI_OPCODE_RCP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED, tgsi_trans_srcx_replicate},
2789
2790 {TGSI_OPCODE_RSQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_rsq},
2791 {TGSI_OPCODE_EXP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2792 {TGSI_OPCODE_LOG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_log},
2793 {TGSI_OPCODE_MUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2794 {TGSI_OPCODE_ADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2795 {TGSI_OPCODE_DP3, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2796 {TGSI_OPCODE_DP4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2797 {TGSI_OPCODE_DST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2798 {TGSI_OPCODE_MIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2799 {TGSI_OPCODE_MAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2800 {TGSI_OPCODE_SLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2801 {TGSI_OPCODE_SGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2802 {TGSI_OPCODE_MAD, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2803 {TGSI_OPCODE_SUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2804 {TGSI_OPCODE_LRP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2805 {TGSI_OPCODE_CND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2806 /* gap */
2807 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2808 {TGSI_OPCODE_DP2A, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2809 /* gap */
2810 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2811 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2812 {TGSI_OPCODE_FRC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2813 {TGSI_OPCODE_CLAMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2814 {TGSI_OPCODE_FLR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2815 {TGSI_OPCODE_ROUND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2816 {TGSI_OPCODE_EX2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2817 {TGSI_OPCODE_LG2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2818 {TGSI_OPCODE_POW, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2819 {TGSI_OPCODE_XPD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2820 /* gap */
2821 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2822 {TGSI_OPCODE_ABS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2823 {TGSI_OPCODE_RCC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2824 {TGSI_OPCODE_DPH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2825 {TGSI_OPCODE_COS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2826 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2827 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2828 {TGSI_OPCODE_KILP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2829 {TGSI_OPCODE_PK2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2830 {TGSI_OPCODE_PK2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2831 {TGSI_OPCODE_PK4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2832 {TGSI_OPCODE_PK4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2833 {TGSI_OPCODE_RFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2834 {TGSI_OPCODE_SEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2835 {TGSI_OPCODE_SFL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2836 {TGSI_OPCODE_SGT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2837 {TGSI_OPCODE_SIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2838 {TGSI_OPCODE_SLE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2839 {TGSI_OPCODE_SNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2840 {TGSI_OPCODE_STR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2841 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2842 {TGSI_OPCODE_TXD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2843 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
2844 {TGSI_OPCODE_UP2H, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2845 {TGSI_OPCODE_UP2US, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2846 {TGSI_OPCODE_UP4B, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2847 {TGSI_OPCODE_UP4UB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2848 {TGSI_OPCODE_X2D, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2849 {TGSI_OPCODE_ARA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2850 {TGSI_OPCODE_ARR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
2851 {TGSI_OPCODE_BRA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2852 {TGSI_OPCODE_CAL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2853 {TGSI_OPCODE_RET, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2854 {TGSI_OPCODE_SSG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
2855 {TGSI_OPCODE_CMP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
2856 {TGSI_OPCODE_SCS, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
2857 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2858 {TGSI_OPCODE_NRM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2859 {TGSI_OPCODE_DIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2860 {TGSI_OPCODE_DP2, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2861 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
2862 {TGSI_OPCODE_BRK, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
2863 {TGSI_OPCODE_IF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
2864 /* gap */
2865 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2866 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2867 {TGSI_OPCODE_ELSE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
2868 {TGSI_OPCODE_ENDIF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
2869 /* gap */
2870 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2871 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2872 {TGSI_OPCODE_PUSHA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2873 {TGSI_OPCODE_POPA, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2874 {TGSI_OPCODE_CEIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2875 {TGSI_OPCODE_I2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2876 {TGSI_OPCODE_NOT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2877 {TGSI_OPCODE_TRUNC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
2878 {TGSI_OPCODE_SHL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2879 /* gap */
2880 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2881 {TGSI_OPCODE_AND, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2882 {TGSI_OPCODE_OR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2883 {TGSI_OPCODE_MOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2884 {TGSI_OPCODE_XOR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2885 {TGSI_OPCODE_SAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2886 {TGSI_OPCODE_TXF, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2887 {TGSI_OPCODE_TXQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2888 {TGSI_OPCODE_CONT, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
2889 {TGSI_OPCODE_EMIT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2890 {TGSI_OPCODE_ENDPRIM, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2891 {TGSI_OPCODE_BGNLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
2892 {TGSI_OPCODE_BGNSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2893 {TGSI_OPCODE_ENDLOOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
2894 {TGSI_OPCODE_ENDSUB, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2895 /* gap */
2896 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2897 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2898 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2899 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2900 {TGSI_OPCODE_NOP, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2901 /* gap */
2902 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2903 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2904 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2905 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2906 {TGSI_OPCODE_NRM4, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2907 {TGSI_OPCODE_CALLNZ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2908 {TGSI_OPCODE_IFC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2909 {TGSI_OPCODE_BREAKC, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2910 {TGSI_OPCODE_KIL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
2911 {TGSI_OPCODE_END, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
2912 /* gap */
2913 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2914 {TGSI_OPCODE_F2I, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2915 {TGSI_OPCODE_IDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2916 {TGSI_OPCODE_IMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2917 {TGSI_OPCODE_IMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2918 {TGSI_OPCODE_INEG, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2919 {TGSI_OPCODE_ISGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2920 {TGSI_OPCODE_ISHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2921 {TGSI_OPCODE_ISLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2922 {TGSI_OPCODE_F2U, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2923 {TGSI_OPCODE_U2F, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2924 {TGSI_OPCODE_UADD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2925 {TGSI_OPCODE_UDIV, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2926 {TGSI_OPCODE_UMAD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2927 {TGSI_OPCODE_UMAX, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2928 {TGSI_OPCODE_UMIN, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2929 {TGSI_OPCODE_UMOD, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2930 {TGSI_OPCODE_UMUL, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2931 {TGSI_OPCODE_USEQ, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2932 {TGSI_OPCODE_USGE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2933 {TGSI_OPCODE_USHR, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2934 {TGSI_OPCODE_USLT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2935 {TGSI_OPCODE_USNE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2936 {TGSI_OPCODE_SWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2937 {TGSI_OPCODE_CASE, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2938 {TGSI_OPCODE_DEFAULT, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2939 {TGSI_OPCODE_ENDSWITCH, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2940 {TGSI_OPCODE_LAST, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2941 };
2942
2943 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
2944 {TGSI_OPCODE_ARL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
2945 {TGSI_OPCODE_MOV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2946 {TGSI_OPCODE_LIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
2947 {TGSI_OPCODE_RCP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
2948 {TGSI_OPCODE_RSQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
2949 {TGSI_OPCODE_EXP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
2950 {TGSI_OPCODE_LOG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2951 {TGSI_OPCODE_MUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
2952 {TGSI_OPCODE_ADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2953 {TGSI_OPCODE_DP3, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2954 {TGSI_OPCODE_DP4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2955 {TGSI_OPCODE_DST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
2956 {TGSI_OPCODE_MIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
2957 {TGSI_OPCODE_MAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
2958 {TGSI_OPCODE_SLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
2959 {TGSI_OPCODE_SGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
2960 {TGSI_OPCODE_MAD, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
2961 {TGSI_OPCODE_SUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
2962 {TGSI_OPCODE_LRP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
2963 {TGSI_OPCODE_CND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2964 /* gap */
2965 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2966 {TGSI_OPCODE_DP2A, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2967 /* gap */
2968 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2969 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2970 {TGSI_OPCODE_FRC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
2971 {TGSI_OPCODE_CLAMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2972 {TGSI_OPCODE_FLR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
2973 {TGSI_OPCODE_ROUND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2974 {TGSI_OPCODE_EX2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
2975 {TGSI_OPCODE_LG2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
2976 {TGSI_OPCODE_POW, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
2977 {TGSI_OPCODE_XPD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
2978 /* gap */
2979 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2980 {TGSI_OPCODE_ABS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
2981 {TGSI_OPCODE_RCC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2982 {TGSI_OPCODE_DPH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
2983 {TGSI_OPCODE_COS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
2984 {TGSI_OPCODE_DDX, 0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
2985 {TGSI_OPCODE_DDY, 0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
2986 {TGSI_OPCODE_KILP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* predicated kill */
2987 {TGSI_OPCODE_PK2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2988 {TGSI_OPCODE_PK2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2989 {TGSI_OPCODE_PK4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2990 {TGSI_OPCODE_PK4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2991 {TGSI_OPCODE_RFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2992 {TGSI_OPCODE_SEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
2993 {TGSI_OPCODE_SFL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2994 {TGSI_OPCODE_SGT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
2995 {TGSI_OPCODE_SIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
2996 {TGSI_OPCODE_SLE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
2997 {TGSI_OPCODE_SNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
2998 {TGSI_OPCODE_STR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
2999 {TGSI_OPCODE_TEX, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3000 {TGSI_OPCODE_TXD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3001 {TGSI_OPCODE_TXP, 0, SQ_TEX_INST_SAMPLE, tgsi_tex},
3002 {TGSI_OPCODE_UP2H, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3003 {TGSI_OPCODE_UP2US, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3004 {TGSI_OPCODE_UP4B, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3005 {TGSI_OPCODE_UP4UB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3006 {TGSI_OPCODE_X2D, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3007 {TGSI_OPCODE_ARA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3008 {TGSI_OPCODE_ARR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
3009 {TGSI_OPCODE_BRA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3010 {TGSI_OPCODE_CAL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3011 {TGSI_OPCODE_RET, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3012 {TGSI_OPCODE_SSG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
3013 {TGSI_OPCODE_CMP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
3014 {TGSI_OPCODE_SCS, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
3015 {TGSI_OPCODE_TXB, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3016 {TGSI_OPCODE_NRM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3017 {TGSI_OPCODE_DIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3018 {TGSI_OPCODE_DP2, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
3019 {TGSI_OPCODE_TXL, 0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
3020 {TGSI_OPCODE_BRK, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
3021 {TGSI_OPCODE_IF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
3022 /* gap */
3023 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3024 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3025 {TGSI_OPCODE_ELSE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
3026 {TGSI_OPCODE_ENDIF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
3027 /* gap */
3028 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3029 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3030 {TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3031 {TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3032 {TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3033 {TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3034 {TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3035 {TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
3036 {TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3037 /* gap */
3038 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3039 {TGSI_OPCODE_AND, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3040 {TGSI_OPCODE_OR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3041 {TGSI_OPCODE_MOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3042 {TGSI_OPCODE_XOR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3043 {TGSI_OPCODE_SAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3044 {TGSI_OPCODE_TXF, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3045 {TGSI_OPCODE_TXQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3046 {TGSI_OPCODE_CONT, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
3047 {TGSI_OPCODE_EMIT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3048 {TGSI_OPCODE_ENDPRIM, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3049 {TGSI_OPCODE_BGNLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
3050 {TGSI_OPCODE_BGNSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3051 {TGSI_OPCODE_ENDLOOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
3052 {TGSI_OPCODE_ENDSUB, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3053 /* gap */
3054 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3055 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3056 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3057 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3058 {TGSI_OPCODE_NOP, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3059 /* gap */
3060 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3061 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3062 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3063 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3064 {TGSI_OPCODE_NRM4, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3065 {TGSI_OPCODE_CALLNZ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3066 {TGSI_OPCODE_IFC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3067 {TGSI_OPCODE_BREAKC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3068 {TGSI_OPCODE_KIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill}, /* conditional kill */
3069 {TGSI_OPCODE_END, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_end}, /* aka HALT */
3070 /* gap */
3071 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3072 {TGSI_OPCODE_F2I, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3073 {TGSI_OPCODE_IDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3074 {TGSI_OPCODE_IMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3075 {TGSI_OPCODE_IMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3076 {TGSI_OPCODE_INEG, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3077 {TGSI_OPCODE_ISGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3078 {TGSI_OPCODE_ISHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3079 {TGSI_OPCODE_ISLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3080 {TGSI_OPCODE_F2U, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3081 {TGSI_OPCODE_U2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3082 {TGSI_OPCODE_UADD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3083 {TGSI_OPCODE_UDIV, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3084 {TGSI_OPCODE_UMAD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3085 {TGSI_OPCODE_UMAX, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3086 {TGSI_OPCODE_UMIN, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3087 {TGSI_OPCODE_UMOD, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3088 {TGSI_OPCODE_UMUL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3089 {TGSI_OPCODE_USEQ, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3090 {TGSI_OPCODE_USGE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3091 {TGSI_OPCODE_USHR, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3092 {TGSI_OPCODE_USLT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3093 {TGSI_OPCODE_USNE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3094 {TGSI_OPCODE_SWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3095 {TGSI_OPCODE_CASE, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3096 {TGSI_OPCODE_DEFAULT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3097 {TGSI_OPCODE_ENDSWITCH, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3098 {TGSI_OPCODE_LAST, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
3099 };