2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 #include "pipe/p_shader_tokens.h"
24 #include "tgsi/tgsi_parse.h"
25 #include "tgsi/tgsi_scan.h"
26 #include "tgsi/tgsi_dump.h"
27 #include "util/u_format.h"
28 #include "r600_pipe.h"
31 #include "r600_opcodes.h"
36 static void r600_pipe_shader_vs(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
38 struct r600_pipe_state
*rstate
= &shader
->rstate
;
39 struct r600_shader
*rshader
= &shader
->shader
;
40 unsigned spi_vs_out_id
[10];
43 /* clear previous register */
46 /* so far never got proper semantic id from tgsi */
47 /* FIXME better to move this in config things so they get emited
48 * only one time per cs
50 for (i
= 0; i
< 10; i
++) {
53 for (i
= 0; i
< 32; i
++) {
54 tmp
= i
<< ((i
& 3) * 8);
55 spi_vs_out_id
[i
/ 4] |= tmp
;
57 for (i
= 0; i
< 10; i
++) {
58 r600_pipe_state_add_reg(rstate
,
59 R_028614_SPI_VS_OUT_ID_0
+ i
* 4,
60 spi_vs_out_id
[i
], 0xFFFFFFFF, NULL
);
63 r600_pipe_state_add_reg(rstate
,
64 R_0286C4_SPI_VS_OUT_CONFIG
,
65 S_0286C4_VS_EXPORT_COUNT(rshader
->noutput
- 2),
67 r600_pipe_state_add_reg(rstate
,
68 R_028868_SQ_PGM_RESOURCES_VS
,
69 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
70 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
72 r600_pipe_state_add_reg(rstate
,
73 R_0288D0_SQ_PGM_CF_OFFSET_VS
,
74 0x00000000, 0xFFFFFFFF, NULL
);
75 r600_pipe_state_add_reg(rstate
,
76 R_028858_SQ_PGM_START_VS
,
77 r600_bo_offset(shader
->bo
) >> 8, 0xFFFFFFFF, shader
->bo
);
79 r600_pipe_state_add_reg(rstate
,
80 R_03E200_SQ_LOOP_CONST_0
+ (32 * 4), 0x01000FFF,
85 int r600_find_vs_semantic_index(struct r600_shader
*vs
,
86 struct r600_shader
*ps
, int id
)
88 struct r600_shader_io
*input
= &ps
->input
[id
];
90 for (int i
= 0; i
< vs
->noutput
; i
++) {
91 if (input
->name
== vs
->output
[i
].name
&&
92 input
->sid
== vs
->output
[i
].sid
) {
99 static void r600_pipe_shader_ps(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
101 struct r600_pipe_state
*rstate
= &shader
->rstate
;
102 struct r600_shader
*rshader
= &shader
->shader
;
103 unsigned i
, exports_ps
, num_cout
, spi_ps_in_control_0
, spi_input_z
, spi_ps_in_control_1
;
104 int pos_index
= -1, face_index
= -1;
108 for (i
= 0; i
< rshader
->ninput
; i
++) {
109 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_POSITION
)
111 if (rshader
->input
[i
].name
== TGSI_SEMANTIC_FACE
)
115 for (i
= 0; i
< rshader
->noutput
; i
++) {
116 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
)
117 r600_pipe_state_add_reg(rstate
,
118 R_02880C_DB_SHADER_CONTROL
,
119 S_02880C_Z_EXPORT_ENABLE(1),
120 S_02880C_Z_EXPORT_ENABLE(1), NULL
);
121 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
122 r600_pipe_state_add_reg(rstate
,
123 R_02880C_DB_SHADER_CONTROL
,
124 S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
125 S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL
);
130 for (i
= 0; i
< rshader
->noutput
; i
++) {
131 if (rshader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
|| rshader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
)
133 else if (rshader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
137 exports_ps
|= S_028854_EXPORT_COLORS(num_cout
);
139 /* always at least export 1 component per pixel */
143 spi_ps_in_control_0
= S_0286CC_NUM_INTERP(rshader
->ninput
) |
144 S_0286CC_PERSP_GRADIENT_ENA(1);
146 if (pos_index
!= -1) {
147 spi_ps_in_control_0
|= (S_0286CC_POSITION_ENA(1) |
148 S_0286CC_POSITION_CENTROID(rshader
->input
[pos_index
].centroid
) |
149 S_0286CC_POSITION_ADDR(rshader
->input
[pos_index
].gpr
) |
150 S_0286CC_BARYC_SAMPLE_CNTL(1));
154 spi_ps_in_control_1
= 0;
155 if (face_index
!= -1) {
156 spi_ps_in_control_1
|= S_0286D0_FRONT_FACE_ENA(1) |
157 S_0286D0_FRONT_FACE_ADDR(rshader
->input
[face_index
].gpr
);
160 r600_pipe_state_add_reg(rstate
, R_0286CC_SPI_PS_IN_CONTROL_0
, spi_ps_in_control_0
, 0xFFFFFFFF, NULL
);
161 r600_pipe_state_add_reg(rstate
, R_0286D0_SPI_PS_IN_CONTROL_1
, spi_ps_in_control_1
, 0xFFFFFFFF, NULL
);
162 r600_pipe_state_add_reg(rstate
, R_0286D8_SPI_INPUT_Z
, spi_input_z
, 0xFFFFFFFF, NULL
);
163 r600_pipe_state_add_reg(rstate
,
164 R_028840_SQ_PGM_START_PS
,
165 r600_bo_offset(shader
->bo
) >> 8, 0xFFFFFFFF, shader
->bo
);
166 r600_pipe_state_add_reg(rstate
,
167 R_028850_SQ_PGM_RESOURCES_PS
,
168 S_028868_NUM_GPRS(rshader
->bc
.ngpr
) |
169 S_028868_STACK_SIZE(rshader
->bc
.nstack
),
171 r600_pipe_state_add_reg(rstate
,
172 R_028854_SQ_PGM_EXPORTS_PS
,
173 exports_ps
, 0xFFFFFFFF, NULL
);
174 r600_pipe_state_add_reg(rstate
,
175 R_0288CC_SQ_PGM_CF_OFFSET_PS
,
176 0x00000000, 0xFFFFFFFF, NULL
);
178 if (rshader
->uses_kill
) {
179 /* only set some bits here, the other bits are set in the dsa state */
180 r600_pipe_state_add_reg(rstate
,
181 R_02880C_DB_SHADER_CONTROL
,
182 S_02880C_KILL_ENABLE(1),
183 S_02880C_KILL_ENABLE(1), NULL
);
185 r600_pipe_state_add_reg(rstate
,
186 R_03E200_SQ_LOOP_CONST_0
, 0x01000FFF,
190 int r600_pipe_shader(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
192 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
193 struct r600_shader
*rshader
= &shader
->shader
;
196 /* copy new shader */
197 if (shader
->bo
== NULL
) {
198 shader
->bo
= r600_bo(rctx
->radeon
, rshader
->bc
.ndw
* 4, 4096, 0, 0);
199 if (shader
->bo
== NULL
) {
202 ptr
= r600_bo_map(rctx
->radeon
, shader
->bo
, 0, NULL
);
203 memcpy(ptr
, rshader
->bc
.bytecode
, rshader
->bc
.ndw
* 4);
204 r600_bo_unmap(rctx
->radeon
, shader
->bo
);
207 switch (rshader
->processor_type
) {
208 case TGSI_PROCESSOR_VERTEX
:
209 if (rshader
->family
>= CHIP_CEDAR
) {
210 evergreen_pipe_shader_vs(ctx
, shader
);
212 r600_pipe_shader_vs(ctx
, shader
);
215 case TGSI_PROCESSOR_FRAGMENT
:
216 if (rshader
->family
>= CHIP_CEDAR
) {
217 evergreen_pipe_shader_ps(ctx
, shader
);
219 r600_pipe_shader_ps(ctx
, shader
);
228 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
, u32
**literals
);
229 int r600_pipe_shader_create(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
, const struct tgsi_token
*tokens
)
231 static int dump_shaders
= -1;
232 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
236 /* Would like some magic "get_bool_option_once" routine.
238 if (dump_shaders
== -1)
239 dump_shaders
= debug_get_bool_option("R600_DUMP_SHADERS", FALSE
);
242 fprintf(stderr
, "--------------------------------------------------------------\n");
243 tgsi_dump(tokens
, 0);
245 shader
->shader
.family
= r600_get_family(rctx
->radeon
);
246 r
= r600_shader_from_tgsi(tokens
, &shader
->shader
, &literals
);
248 R600_ERR("translation from TGSI failed !\n");
251 r
= r600_bc_build(&shader
->shader
.bc
);
254 R600_ERR("building bytecode failed !\n");
258 r600_bc_dump(&shader
->shader
.bc
);
259 fprintf(stderr
, "______________________________________________________________\n");
261 return r600_pipe_shader(ctx
, shader
);
264 void r600_pipe_shader_destroy(struct pipe_context
*ctx
, struct r600_pipe_shader
*shader
)
266 struct r600_pipe_context
*rctx
= (struct r600_pipe_context
*)ctx
;
268 r600_bo_reference(rctx
->radeon
, &shader
->bo
, NULL
);
269 r600_bc_clear(&shader
->shader
.bc
);
273 * tgsi -> r600 shader
275 struct r600_shader_tgsi_instruction
;
277 struct r600_shader_ctx
{
278 struct tgsi_shader_info info
;
279 struct tgsi_parse_context parse
;
280 const struct tgsi_token
*tokens
;
282 unsigned file_offset
[TGSI_FILE_COUNT
];
284 struct r600_shader_tgsi_instruction
*inst_info
;
286 struct r600_shader
*shader
;
289 u32 max_driver_temp_used
;
290 /* needed for evergreen interpolation */
291 boolean input_centroid
;
292 boolean input_linear
;
293 boolean input_perspective
;
297 struct r600_shader_tgsi_instruction
{
298 unsigned tgsi_opcode
;
300 unsigned r600_opcode
;
301 int (*process
)(struct r600_shader_ctx
*ctx
);
304 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[], eg_shader_tgsi_instruction
[];
305 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
);
307 static int tgsi_is_supported(struct r600_shader_ctx
*ctx
)
309 struct tgsi_full_instruction
*i
= &ctx
->parse
.FullToken
.FullInstruction
;
312 if (i
->Instruction
.NumDstRegs
> 1) {
313 R600_ERR("too many dst (%d)\n", i
->Instruction
.NumDstRegs
);
316 if (i
->Instruction
.Predicate
) {
317 R600_ERR("predicate unsupported\n");
321 if (i
->Instruction
.Label
) {
322 R600_ERR("label unsupported\n");
326 for (j
= 0; j
< i
->Instruction
.NumSrcRegs
; j
++) {
327 if (i
->Src
[j
].Register
.Dimension
) {
328 R600_ERR("unsupported src %d (dimension %d)\n", j
,
329 i
->Src
[j
].Register
.Dimension
);
333 for (j
= 0; j
< i
->Instruction
.NumDstRegs
; j
++) {
334 if (i
->Dst
[j
].Register
.Dimension
) {
335 R600_ERR("unsupported dst (dimension)\n");
342 static int evergreen_interp_alu(struct r600_shader_ctx
*ctx
, int input
)
345 struct r600_bc_alu alu
;
346 int gpr
= 0, base_chan
= 0;
349 if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_PERSPECTIVE
) {
351 if (ctx
->shader
->input
[input
].centroid
)
353 } else if (ctx
->shader
->input
[input
].interpolate
== TGSI_INTERPOLATE_LINEAR
) {
355 /* if we have perspective add one */
356 if (ctx
->input_perspective
) {
358 /* if we have perspective centroid */
359 if (ctx
->input_centroid
)
362 if (ctx
->shader
->input
[input
].centroid
)
366 /* work out gpr and base_chan from index */
368 base_chan
= (2 * (ij_index
% 2)) + 1;
370 for (i
= 0; i
< 8; i
++) {
371 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
374 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW
;
376 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY
;
378 if ((i
> 1) && (i
< 6)) {
379 alu
.dst
.sel
= ctx
->shader
->input
[input
].gpr
;
383 alu
.dst
.chan
= i
% 4;
385 alu
.src
[0].sel
= gpr
;
386 alu
.src
[0].chan
= (base_chan
- (i
% 2));
388 alu
.src
[1].sel
= V_SQ_ALU_SRC_PARAM_BASE
+ ctx
->shader
->input
[input
].lds_pos
;
390 alu
.bank_swizzle_force
= SQ_ALU_VEC_210
;
393 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
401 static int tgsi_declaration(struct r600_shader_ctx
*ctx
)
403 struct tgsi_full_declaration
*d
= &ctx
->parse
.FullToken
.FullDeclaration
;
406 switch (d
->Declaration
.File
) {
407 case TGSI_FILE_INPUT
:
408 i
= ctx
->shader
->ninput
++;
409 ctx
->shader
->input
[i
].name
= d
->Semantic
.Name
;
410 ctx
->shader
->input
[i
].sid
= d
->Semantic
.Index
;
411 ctx
->shader
->input
[i
].interpolate
= d
->Declaration
.Interpolate
;
412 ctx
->shader
->input
[i
].centroid
= d
->Declaration
.Centroid
;
413 ctx
->shader
->input
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_INPUT
] + i
;
414 if (ctx
->type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
->bc
->chiprev
== CHIPREV_EVERGREEN
) {
415 /* turn input into interpolate on EG */
416 if (ctx
->shader
->input
[i
].name
!= TGSI_SEMANTIC_POSITION
) {
417 if (ctx
->shader
->input
[i
].interpolate
> 0) {
418 ctx
->shader
->input
[i
].lds_pos
= ctx
->shader
->nlds
++;
419 evergreen_interp_alu(ctx
, i
);
424 case TGSI_FILE_OUTPUT
:
425 i
= ctx
->shader
->noutput
++;
426 ctx
->shader
->output
[i
].name
= d
->Semantic
.Name
;
427 ctx
->shader
->output
[i
].sid
= d
->Semantic
.Index
;
428 ctx
->shader
->output
[i
].gpr
= ctx
->file_offset
[TGSI_FILE_OUTPUT
] + i
;
429 ctx
->shader
->output
[i
].interpolate
= d
->Declaration
.Interpolate
;
431 case TGSI_FILE_CONSTANT
:
432 case TGSI_FILE_TEMPORARY
:
433 case TGSI_FILE_SAMPLER
:
434 case TGSI_FILE_ADDRESS
:
437 R600_ERR("unsupported file %d declaration\n", d
->Declaration
.File
);
443 static int r600_get_temp(struct r600_shader_ctx
*ctx
)
445 return ctx
->temp_reg
+ ctx
->max_driver_temp_used
++;
449 * for evergreen we need to scan the shader to find the number of GPRs we need to
450 * reserve for interpolation.
452 * we need to know if we are going to emit
453 * any centroid inputs
454 * if perspective and linear are required
456 static int evergreen_gpr_count(struct r600_shader_ctx
*ctx
)
461 ctx
->input_linear
= FALSE
;
462 ctx
->input_perspective
= FALSE
;
463 ctx
->input_centroid
= FALSE
;
464 ctx
->num_interp_gpr
= 1;
466 /* any centroid inputs */
467 for (i
= 0; i
< ctx
->info
.num_inputs
; i
++) {
468 /* skip position/face */
469 if (ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_POSITION
||
470 ctx
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_FACE
)
472 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_LINEAR
)
473 ctx
->input_linear
= TRUE
;
474 if (ctx
->info
.input_interpolate
[i
] == TGSI_INTERPOLATE_PERSPECTIVE
)
475 ctx
->input_perspective
= TRUE
;
476 if (ctx
->info
.input_centroid
[i
])
477 ctx
->input_centroid
= TRUE
;
481 /* ignoring sample for now */
482 if (ctx
->input_perspective
)
484 if (ctx
->input_linear
)
486 if (ctx
->input_centroid
)
489 ctx
->num_interp_gpr
+= (num_baryc
+ 1) >> 1;
491 /* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
492 return ctx
->num_interp_gpr
;
495 int r600_shader_from_tgsi(const struct tgsi_token
*tokens
, struct r600_shader
*shader
, u32
**literals
)
497 struct tgsi_full_immediate
*immediate
;
498 struct r600_shader_ctx ctx
;
499 struct r600_bc_output output
[32];
504 ctx
.bc
= &shader
->bc
;
506 r
= r600_bc_init(ctx
.bc
, shader
->family
);
510 tgsi_scan_shader(tokens
, &ctx
.info
);
511 tgsi_parse_init(&ctx
.parse
, tokens
);
512 ctx
.type
= ctx
.parse
.FullHeader
.Processor
.Processor
;
513 shader
->processor_type
= ctx
.type
;
514 ctx
.bc
->type
= shader
->processor_type
;
516 /* register allocations */
517 /* Values [0,127] correspond to GPR[0..127].
518 * Values [128,159] correspond to constant buffer bank 0
519 * Values [160,191] correspond to constant buffer bank 1
520 * Values [256,511] correspond to cfile constants c[0..255]. (Gone on EG)
521 * Values [256,287] correspond to constant buffer bank 2 (EG)
522 * Values [288,319] correspond to constant buffer bank 3 (EG)
523 * Other special values are shown in the list below.
524 * 244 ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
525 * 245 ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
526 * 246 ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
527 * 247 ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
528 * 248 SQ_ALU_SRC_0: special constant 0.0.
529 * 249 SQ_ALU_SRC_1: special constant 1.0 float.
530 * 250 SQ_ALU_SRC_1_INT: special constant 1 integer.
531 * 251 SQ_ALU_SRC_M_1_INT: special constant -1 integer.
532 * 252 SQ_ALU_SRC_0_5: special constant 0.5 float.
533 * 253 SQ_ALU_SRC_LITERAL: literal constant.
534 * 254 SQ_ALU_SRC_PV: previous vector result.
535 * 255 SQ_ALU_SRC_PS: previous scalar result.
537 for (i
= 0; i
< TGSI_FILE_COUNT
; i
++) {
538 ctx
.file_offset
[i
] = 0;
540 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
541 ctx
.file_offset
[TGSI_FILE_INPUT
] = 1;
542 if (ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
) {
543 r600_bc_add_cfinst(ctx
.bc
, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
545 r600_bc_add_cfinst(ctx
.bc
, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS
);
548 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
) {
549 ctx
.file_offset
[TGSI_FILE_INPUT
] = evergreen_gpr_count(&ctx
);
551 ctx
.file_offset
[TGSI_FILE_OUTPUT
] = ctx
.file_offset
[TGSI_FILE_INPUT
] +
552 ctx
.info
.file_count
[TGSI_FILE_INPUT
];
553 ctx
.file_offset
[TGSI_FILE_TEMPORARY
] = ctx
.file_offset
[TGSI_FILE_OUTPUT
] +
554 ctx
.info
.file_count
[TGSI_FILE_OUTPUT
];
556 /* Outside the GPR range. This will be translated to one of the
557 * kcache banks later. */
558 ctx
.file_offset
[TGSI_FILE_CONSTANT
] = 512;
560 ctx
.file_offset
[TGSI_FILE_IMMEDIATE
] = V_SQ_ALU_SRC_LITERAL
;
561 ctx
.temp_reg
= ctx
.file_offset
[TGSI_FILE_TEMPORARY
] +
562 ctx
.info
.file_count
[TGSI_FILE_TEMPORARY
];
567 while (!tgsi_parse_end_of_tokens(&ctx
.parse
)) {
568 tgsi_parse_token(&ctx
.parse
);
569 switch (ctx
.parse
.FullToken
.Token
.Type
) {
570 case TGSI_TOKEN_TYPE_IMMEDIATE
:
571 immediate
= &ctx
.parse
.FullToken
.FullImmediate
;
572 ctx
.literals
= realloc(ctx
.literals
, (ctx
.nliterals
+ 1) * 16);
573 if(ctx
.literals
== NULL
) {
577 ctx
.literals
[ctx
.nliterals
* 4 + 0] = immediate
->u
[0].Uint
;
578 ctx
.literals
[ctx
.nliterals
* 4 + 1] = immediate
->u
[1].Uint
;
579 ctx
.literals
[ctx
.nliterals
* 4 + 2] = immediate
->u
[2].Uint
;
580 ctx
.literals
[ctx
.nliterals
* 4 + 3] = immediate
->u
[3].Uint
;
583 case TGSI_TOKEN_TYPE_DECLARATION
:
584 r
= tgsi_declaration(&ctx
);
588 case TGSI_TOKEN_TYPE_INSTRUCTION
:
589 r
= tgsi_is_supported(&ctx
);
592 ctx
.max_driver_temp_used
= 0;
593 /* reserve first tmp for everyone */
595 opcode
= ctx
.parse
.FullToken
.FullInstruction
.Instruction
.Opcode
;
596 if (ctx
.bc
->chiprev
== CHIPREV_EVERGREEN
)
597 ctx
.inst_info
= &eg_shader_tgsi_instruction
[opcode
];
599 ctx
.inst_info
= &r600_shader_tgsi_instruction
[opcode
];
600 r
= ctx
.inst_info
->process(&ctx
);
604 case TGSI_TOKEN_TYPE_PROPERTY
:
607 R600_ERR("unsupported token type %d\n", ctx
.parse
.FullToken
.Token
.Type
);
613 noutput
= shader
->noutput
;
614 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
615 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
616 output
[i
].gpr
= shader
->output
[i
].gpr
;
617 output
[i
].elem_size
= 3;
618 output
[i
].swizzle_x
= 0;
619 output
[i
].swizzle_y
= 1;
620 output
[i
].swizzle_z
= 2;
621 output
[i
].swizzle_w
= 3;
622 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
623 output
[i
].array_base
= i
- pos0
;
625 case TGSI_PROCESSOR_VERTEX
:
626 if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
627 output
[i
].array_base
= 60;
628 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
629 /* position doesn't count in array_base */
632 if (shader
->output
[i
].name
== TGSI_SEMANTIC_PSIZE
) {
633 output
[i
].array_base
= 61;
634 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS
;
635 /* position doesn't count in array_base */
639 case TGSI_PROCESSOR_FRAGMENT
:
640 if (shader
->output
[i
].name
== TGSI_SEMANTIC_COLOR
) {
641 output
[i
].array_base
= shader
->output
[i
].sid
;
642 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
643 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_POSITION
) {
644 output
[i
].array_base
= 61;
645 output
[i
].swizzle_x
= 2;
646 output
[i
].swizzle_y
= 7;
647 output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
648 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
649 } else if (shader
->output
[i
].name
== TGSI_SEMANTIC_STENCIL
) {
650 output
[i
].array_base
= 61;
651 output
[i
].swizzle_x
= 7;
652 output
[i
].swizzle_y
= 1;
653 output
[i
].swizzle_z
= output
[i
].swizzle_w
= 7;
654 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
656 R600_ERR("unsupported fragment output name %d\n", shader
->output
[i
].name
);
662 R600_ERR("unsupported processor type %d\n", ctx
.type
);
667 /* add fake param output for vertex shader if no param is exported */
668 if (ctx
.type
== TGSI_PROCESSOR_VERTEX
) {
669 for (i
= 0, pos0
= 0; i
< noutput
; i
++) {
670 if (output
[i
].type
== V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
) {
676 memset(&output
[i
], 0, sizeof(struct r600_bc_output
));
678 output
[i
].elem_size
= 3;
679 output
[i
].swizzle_x
= 0;
680 output
[i
].swizzle_y
= 1;
681 output
[i
].swizzle_z
= 2;
682 output
[i
].swizzle_w
= 3;
683 output
[i
].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM
;
684 output
[i
].array_base
= 0;
688 /* add fake pixel export */
689 if (ctx
.type
== TGSI_PROCESSOR_FRAGMENT
&& !noutput
) {
690 memset(&output
[0], 0, sizeof(struct r600_bc_output
));
692 output
[0].elem_size
= 3;
693 output
[0].swizzle_x
= 7;
694 output
[0].swizzle_y
= 7;
695 output
[0].swizzle_z
= 7;
696 output
[0].swizzle_w
= 7;
697 output
[0].type
= V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL
;
698 output
[0].array_base
= 0;
701 /* add output to bytecode */
702 for (i
= 0; i
< noutput
; i
++) {
703 r
= r600_bc_add_output(ctx
.bc
, &output
[i
]);
707 *literals
= ctx
.literals
;
708 tgsi_parse_free(&ctx
.parse
);
712 tgsi_parse_free(&ctx
.parse
);
716 static int tgsi_unsupported(struct r600_shader_ctx
*ctx
)
718 R600_ERR("%d tgsi opcode unsupported\n", ctx
->inst_info
->tgsi_opcode
);
722 static int tgsi_end(struct r600_shader_ctx
*ctx
)
727 static int tgsi_src(struct r600_shader_ctx
*ctx
,
728 const struct tgsi_full_src_register
*tgsi_src
,
729 struct r600_bc_alu_src
*r600_src
)
731 memset(r600_src
, 0, sizeof(struct r600_bc_alu_src
));
732 r600_src
->neg
= tgsi_src
->Register
.Negate
;
733 r600_src
->abs
= tgsi_src
->Register
.Absolute
;
734 if (tgsi_src
->Register
.File
== TGSI_FILE_IMMEDIATE
) {
736 if((tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleY
) &&
737 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleZ
) &&
738 (tgsi_src
->Register
.SwizzleX
== tgsi_src
->Register
.SwizzleW
)) {
740 index
= tgsi_src
->Register
.Index
* 4 + tgsi_src
->Register
.SwizzleX
;
741 r600_bc_special_constants(ctx
->literals
[index
], &r600_src
->sel
, &r600_src
->neg
);
742 if (r600_src
->sel
!= V_SQ_ALU_SRC_LITERAL
)
745 index
= tgsi_src
->Register
.Index
;
746 r600_src
->sel
= V_SQ_ALU_SRC_LITERAL
;
747 r600_src
->value
= ctx
->literals
+ index
* 4;
749 if (tgsi_src
->Register
.Indirect
)
750 r600_src
->rel
= V_SQ_REL_RELATIVE
;
751 r600_src
->sel
= tgsi_src
->Register
.Index
;
752 r600_src
->sel
+= ctx
->file_offset
[tgsi_src
->Register
.File
];
757 static int tgsi_dst(struct r600_shader_ctx
*ctx
,
758 const struct tgsi_full_dst_register
*tgsi_dst
,
760 struct r600_bc_alu_dst
*r600_dst
)
762 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
764 r600_dst
->sel
= tgsi_dst
->Register
.Index
;
765 r600_dst
->sel
+= ctx
->file_offset
[tgsi_dst
->Register
.File
];
766 r600_dst
->chan
= swizzle
;
768 if (tgsi_dst
->Register
.Indirect
)
769 r600_dst
->rel
= V_SQ_REL_RELATIVE
;
770 if (inst
->Instruction
.Saturate
) {
776 static unsigned tgsi_chan(const struct tgsi_full_src_register
*tgsi_src
, unsigned swizzle
)
780 return tgsi_src
->Register
.SwizzleX
;
782 return tgsi_src
->Register
.SwizzleY
;
784 return tgsi_src
->Register
.SwizzleZ
;
786 return tgsi_src
->Register
.SwizzleW
;
792 static int tgsi_split_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
794 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
795 struct r600_bc_alu alu
;
796 int i
, j
, k
, nconst
, r
;
798 for (i
= 0, nconst
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
799 if (inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
802 r
= tgsi_src(ctx
, &inst
->Src
[i
], &r600_src
[i
]);
807 for (i
= 0, j
= nconst
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
808 if (j
> 0 && inst
->Src
[i
].Register
.File
== TGSI_FILE_CONSTANT
) {
809 int treg
= r600_get_temp(ctx
);
810 for (k
= 0; k
< 4; k
++) {
811 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
812 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
813 alu
.src
[0].sel
= r600_src
[i
].sel
;
815 alu
.src
[0].rel
= r600_src
[i
].rel
;
821 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
825 r600_src
[i
].sel
= treg
;
833 /* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
834 static int tgsi_split_literal_constant(struct r600_shader_ctx
*ctx
, struct r600_bc_alu_src r600_src
[3])
836 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
837 struct r600_bc_alu alu
;
838 int i
, j
, k
, nliteral
, r
;
840 for (i
= 0, nliteral
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
841 if (r600_src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
845 for (i
= 0, j
= nliteral
- 1; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
846 if (j
> 0 && r600_src
[i
].sel
== V_SQ_ALU_SRC_LITERAL
) {
847 int treg
= r600_get_temp(ctx
);
848 for (k
= 0; k
< 4; k
++) {
849 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
850 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
851 alu
.src
[0].sel
= r600_src
[i
].sel
;
853 alu
.src
[0].value
= r600_src
[i
].value
;
859 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
863 r600_src
[i
].sel
= treg
;
870 static int tgsi_last_instruction(unsigned writemask
)
874 for (i
= 0; i
< 4; i
++) {
875 if (writemask
& (1 << i
)) {
882 static int tgsi_op2_s(struct r600_shader_ctx
*ctx
, int swap
)
884 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
885 struct r600_bc_alu_src r600_src
[3];
886 struct r600_bc_alu alu
;
888 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
890 r
= tgsi_split_constant(ctx
, r600_src
);
893 r
= tgsi_split_literal_constant(ctx
, r600_src
);
896 for (i
= 0; i
< lasti
+ 1; i
++) {
897 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
900 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
901 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
905 alu
.inst
= ctx
->inst_info
->r600_opcode
;
907 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
908 alu
.src
[j
] = r600_src
[j
];
909 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
912 alu
.src
[0] = r600_src
[1];
913 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
915 alu
.src
[1] = r600_src
[0];
916 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
918 /* handle some special cases */
919 switch (ctx
->inst_info
->tgsi_opcode
) {
920 case TGSI_OPCODE_SUB
:
923 case TGSI_OPCODE_ABS
:
932 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
939 static int tgsi_op2(struct r600_shader_ctx
*ctx
)
941 return tgsi_op2_s(ctx
, 0);
944 static int tgsi_op2_swap(struct r600_shader_ctx
*ctx
)
946 return tgsi_op2_s(ctx
, 1);
950 * r600 - trunc to -PI..PI range
951 * r700 - normalize by dividing by 2PI
954 static int tgsi_setup_trig(struct r600_shader_ctx
*ctx
,
955 struct r600_bc_alu_src r600_src
[3])
957 static float half_inv_pi
= 1.0 /(3.1415926535 * 2);
958 static float double_pi
= 3.1415926535 * 2;
959 static float neg_pi
= -3.1415926535;
961 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
963 struct r600_bc_alu alu
;
965 r
= tgsi_split_constant(ctx
, r600_src
);
968 r
= tgsi_split_literal_constant(ctx
, r600_src
);
972 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
973 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
977 alu
.dst
.sel
= ctx
->temp_reg
;
980 alu
.src
[0] = r600_src
[0];
981 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
983 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
985 alu
.src
[1].value
= (uint32_t *)&half_inv_pi
;
986 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
989 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
993 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
994 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
997 alu
.dst
.sel
= ctx
->temp_reg
;
1000 alu
.src
[0].sel
= ctx
->temp_reg
;
1001 alu
.src
[0].chan
= 0;
1003 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1007 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1008 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1012 alu
.dst
.sel
= ctx
->temp_reg
;
1015 alu
.src
[0].sel
= ctx
->temp_reg
;
1016 alu
.src
[0].chan
= 0;
1018 alu
.src
[1].sel
= V_SQ_ALU_SRC_LITERAL
;
1019 alu
.src
[1].chan
= 0;
1020 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1021 alu
.src
[2].chan
= 0;
1023 if (ctx
->bc
->chiprev
== CHIPREV_R600
) {
1024 alu
.src
[1].value
= (uint32_t *)&double_pi
;
1025 alu
.src
[2].value
= (uint32_t *)&neg_pi
;
1027 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1028 alu
.src
[2].sel
= V_SQ_ALU_SRC_0_5
;
1033 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1039 static int tgsi_trig(struct r600_shader_ctx
*ctx
)
1041 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1042 struct r600_bc_alu_src r600_src
[3];
1043 struct r600_bc_alu alu
;
1045 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1047 r
= tgsi_setup_trig(ctx
, r600_src
);
1051 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1052 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1054 alu
.dst
.sel
= ctx
->temp_reg
;
1057 alu
.src
[0].sel
= ctx
->temp_reg
;
1058 alu
.src
[0].chan
= 0;
1060 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1064 /* replicate result */
1065 for (i
= 0; i
< lasti
+ 1; i
++) {
1066 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1069 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1070 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1072 alu
.src
[0].sel
= ctx
->temp_reg
;
1073 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1078 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1085 static int tgsi_scs(struct r600_shader_ctx
*ctx
)
1087 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1088 struct r600_bc_alu_src r600_src
[3];
1089 struct r600_bc_alu alu
;
1092 /* We'll only need the trig stuff if we are going to write to the
1093 * X or Y components of the destination vector.
1095 if (likely(inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
)) {
1096 r
= tgsi_setup_trig(ctx
, r600_src
);
1102 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
1103 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1104 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
);
1105 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1109 alu
.src
[0].sel
= ctx
->temp_reg
;
1110 alu
.src
[0].chan
= 0;
1112 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1118 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
1119 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1120 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
);
1121 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1125 alu
.src
[0].sel
= ctx
->temp_reg
;
1126 alu
.src
[0].chan
= 0;
1128 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1134 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
1135 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1137 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1139 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1143 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1144 alu
.src
[0].chan
= 0;
1148 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1154 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
1155 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1157 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1159 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1163 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1164 alu
.src
[0].chan
= 0;
1168 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1176 static int tgsi_kill(struct r600_shader_ctx
*ctx
)
1178 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1179 struct r600_bc_alu alu
;
1182 for (i
= 0; i
< 4; i
++) {
1183 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1184 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1188 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
1190 if (ctx
->inst_info
->tgsi_opcode
== TGSI_OPCODE_KILP
) {
1191 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1194 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1197 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1202 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1207 /* kill must be last in ALU */
1208 ctx
->bc
->force_add_cf
= 1;
1209 ctx
->shader
->uses_kill
= TRUE
;
1213 static int tgsi_lit(struct r600_shader_ctx
*ctx
)
1215 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1216 struct r600_bc_alu alu
;
1217 struct r600_bc_alu_src r600_src
[3];
1220 r
= tgsi_split_constant(ctx
, r600_src
);
1223 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1228 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1229 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1230 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
; /*1.0*/
1231 alu
.src
[0].chan
= 0;
1232 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 0, &alu
.dst
);
1235 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 0) & 1;
1236 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1240 /* dst.y = max(src.x, 0.0) */
1241 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1242 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
);
1243 alu
.src
[0] = r600_src
[0];
1244 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
; /*0.0*/
1245 alu
.src
[1].chan
= 0;
1246 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 1, &alu
.dst
);
1249 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 1) & 1;
1250 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1255 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1256 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1257 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1258 alu
.src
[0].chan
= 0;
1259 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 3, &alu
.dst
);
1262 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> 3) & 1;
1264 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1268 if (inst
->Dst
[0].Register
.WriteMask
& (1 << 2))
1273 /* dst.z = log(src.y) */
1274 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1275 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED
);
1276 alu
.src
[0] = r600_src
[0];
1277 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
1278 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1282 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1286 chan
= alu
.dst
.chan
;
1289 /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
1290 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1291 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT
);
1292 alu
.src
[0] = r600_src
[0];
1293 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1294 alu
.src
[1].sel
= sel
;
1295 alu
.src
[1].chan
= chan
;
1297 alu
.src
[2] = r600_src
[0];
1298 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], 0);
1299 alu
.dst
.sel
= ctx
->temp_reg
;
1304 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1308 /* dst.z = exp(tmp.x) */
1309 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1310 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1311 alu
.src
[0].sel
= ctx
->temp_reg
;
1312 alu
.src
[0].chan
= 0;
1313 r
= tgsi_dst(ctx
, &inst
->Dst
[0], 2, &alu
.dst
);
1317 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1324 static int tgsi_rsq(struct r600_shader_ctx
*ctx
)
1326 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1327 struct r600_bc_alu alu
;
1330 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1333 * For state trackers other than OpenGL, we'll want to use
1334 * _RECIPSQRT_IEEE instead.
1336 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED
);
1338 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1339 r
= tgsi_src(ctx
, &inst
->Src
[i
], &alu
.src
[i
]);
1342 alu
.src
[i
].chan
= tgsi_chan(&inst
->Src
[i
], 0);
1345 alu
.dst
.sel
= ctx
->temp_reg
;
1348 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1351 /* replicate result */
1352 return tgsi_helper_tempx_replicate(ctx
);
1355 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx
*ctx
)
1357 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1358 struct r600_bc_alu alu
;
1361 for (i
= 0; i
< 4; i
++) {
1362 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1363 alu
.src
[0].sel
= ctx
->temp_reg
;
1364 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1366 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1369 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1372 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1379 static int tgsi_trans_srcx_replicate(struct r600_shader_ctx
*ctx
)
1381 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1382 struct r600_bc_alu alu
;
1385 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1386 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1387 for (i
= 0; i
< inst
->Instruction
.NumSrcRegs
; i
++) {
1388 r
= tgsi_src(ctx
, &inst
->Src
[i
], &alu
.src
[i
]);
1391 alu
.src
[i
].chan
= tgsi_chan(&inst
->Src
[i
], 0);
1393 alu
.dst
.sel
= ctx
->temp_reg
;
1396 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1399 /* replicate result */
1400 return tgsi_helper_tempx_replicate(ctx
);
1403 static int tgsi_pow(struct r600_shader_ctx
*ctx
)
1405 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1406 struct r600_bc_alu alu
;
1410 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1411 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
1412 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1415 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
1416 alu
.dst
.sel
= ctx
->temp_reg
;
1419 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1423 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1424 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1425 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[0]);
1428 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], 0);
1429 alu
.src
[1].sel
= ctx
->temp_reg
;
1430 alu
.dst
.sel
= ctx
->temp_reg
;
1433 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1436 /* POW(a,b) = EXP2(b * LOG2(a))*/
1437 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1438 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
1439 alu
.src
[0].sel
= ctx
->temp_reg
;
1440 alu
.dst
.sel
= ctx
->temp_reg
;
1443 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1446 return tgsi_helper_tempx_replicate(ctx
);
1449 static int tgsi_ssg(struct r600_shader_ctx
*ctx
)
1451 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1452 struct r600_bc_alu alu
;
1453 struct r600_bc_alu_src r600_src
[3];
1456 r
= tgsi_split_constant(ctx
, r600_src
);
1459 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1463 /* tmp = (src > 0 ? 1 : src) */
1464 for (i
= 0; i
< 4; i
++) {
1465 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1466 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1469 alu
.dst
.sel
= ctx
->temp_reg
;
1472 alu
.src
[0] = r600_src
[0];
1473 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1475 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1477 alu
.src
[2] = r600_src
[0];
1478 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[0], i
);
1481 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1486 /* dst = (-tmp > 0 ? -1 : tmp) */
1487 for (i
= 0; i
< 4; i
++) {
1488 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1489 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT
);
1491 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1495 alu
.src
[0].sel
= ctx
->temp_reg
;
1496 alu
.src
[0].chan
= i
;
1499 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
1502 alu
.src
[2].sel
= ctx
->temp_reg
;
1503 alu
.src
[2].chan
= i
;
1507 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1514 static int tgsi_helper_copy(struct r600_shader_ctx
*ctx
, struct tgsi_full_instruction
*inst
)
1516 struct r600_bc_alu alu
;
1519 for (i
= 0; i
< 4; i
++) {
1520 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1521 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
))) {
1522 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
);
1525 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1526 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1529 alu
.src
[0].sel
= ctx
->temp_reg
;
1530 alu
.src
[0].chan
= i
;
1535 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1542 static int tgsi_op3(struct r600_shader_ctx
*ctx
)
1544 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1545 struct r600_bc_alu_src r600_src
[3];
1546 struct r600_bc_alu alu
;
1548 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1550 r
= tgsi_split_constant(ctx
, r600_src
);
1553 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1556 for (i
= 0; i
< lasti
+ 1; i
++) {
1557 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1560 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1561 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1562 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1563 alu
.src
[j
] = r600_src
[j
];
1564 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1567 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1577 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1584 static int tgsi_dp(struct r600_shader_ctx
*ctx
)
1586 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1587 struct r600_bc_alu_src r600_src
[3];
1588 struct r600_bc_alu alu
;
1591 r
= tgsi_split_constant(ctx
, r600_src
);
1594 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1597 for (i
= 0; i
< 4; i
++) {
1598 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1599 alu
.inst
= ctx
->inst_info
->r600_opcode
;
1600 for (j
= 0; j
< inst
->Instruction
.NumSrcRegs
; j
++) {
1601 alu
.src
[j
] = r600_src
[j
];
1602 alu
.src
[j
].chan
= tgsi_chan(&inst
->Src
[j
], i
);
1605 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1610 alu
.dst
.write
= (inst
->Dst
[0].Register
.WriteMask
>> i
) & 1;
1611 /* handle some special cases */
1612 switch (ctx
->inst_info
->tgsi_opcode
) {
1613 case TGSI_OPCODE_DP2
:
1615 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1616 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1619 case TGSI_OPCODE_DP3
:
1621 alu
.src
[0].sel
= alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
1622 alu
.src
[0].chan
= alu
.src
[1].chan
= 0;
1625 case TGSI_OPCODE_DPH
:
1627 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1628 alu
.src
[0].chan
= 0;
1638 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1645 static int tgsi_tex(struct r600_shader_ctx
*ctx
)
1647 static float one_point_five
= 1.5f
;
1648 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1649 struct r600_bc_tex tex
;
1650 struct r600_bc_alu alu
;
1654 boolean src_not_temp
=
1655 inst
->Src
[0].Register
.File
!= TGSI_FILE_TEMPORARY
&&
1656 inst
->Src
[0].Register
.File
!= TGSI_FILE_INPUT
;
1658 src_gpr
= ctx
->file_offset
[inst
->Src
[0].Register
.File
] + inst
->Src
[0].Register
.Index
;
1660 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1661 /* Add perspective divide */
1662 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1663 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1664 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1668 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 3);
1669 alu
.dst
.sel
= ctx
->temp_reg
;
1673 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1677 for (i
= 0; i
< 3; i
++) {
1678 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1679 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1680 alu
.src
[0].sel
= ctx
->temp_reg
;
1681 alu
.src
[0].chan
= 3;
1682 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1685 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1686 alu
.dst
.sel
= ctx
->temp_reg
;
1689 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1693 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1694 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1695 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1696 alu
.src
[0].chan
= 0;
1697 alu
.dst
.sel
= ctx
->temp_reg
;
1701 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1704 src_not_temp
= FALSE
;
1705 src_gpr
= ctx
->temp_reg
;
1708 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1709 int src_chan
, src2_chan
;
1711 /* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
1712 for (i
= 0; i
< 4; i
++) {
1713 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1714 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE
);
1738 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1741 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], src_chan
);
1742 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[1]);
1745 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], src2_chan
);
1746 alu
.dst
.sel
= ctx
->temp_reg
;
1751 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1756 /* tmp1.z = RCP_e(|tmp1.z|) */
1757 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1758 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
1759 alu
.src
[0].sel
= ctx
->temp_reg
;
1760 alu
.src
[0].chan
= 2;
1762 alu
.dst
.sel
= ctx
->temp_reg
;
1766 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1770 /* MULADD R0.x, R0.x, PS1, (0x3FC00000, 1.5f).x
1771 * MULADD R0.y, R0.y, PS1, (0x3FC00000, 1.5f).x
1772 * muladd has no writemask, have to use another temp
1774 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1775 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1778 alu
.src
[0].sel
= ctx
->temp_reg
;
1779 alu
.src
[0].chan
= 0;
1780 alu
.src
[1].sel
= ctx
->temp_reg
;
1781 alu
.src
[1].chan
= 2;
1783 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1784 alu
.src
[2].chan
= 0;
1785 alu
.src
[2].value
= (u32
*)&one_point_five
;
1787 alu
.dst
.sel
= ctx
->temp_reg
;
1791 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1795 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1796 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1799 alu
.src
[0].sel
= ctx
->temp_reg
;
1800 alu
.src
[0].chan
= 1;
1801 alu
.src
[1].sel
= ctx
->temp_reg
;
1802 alu
.src
[1].chan
= 2;
1804 alu
.src
[2].sel
= V_SQ_ALU_SRC_LITERAL
;
1805 alu
.src
[2].chan
= 0;
1806 alu
.src
[2].value
= (u32
*)&one_point_five
;
1808 alu
.dst
.sel
= ctx
->temp_reg
;
1813 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1817 src_not_temp
= FALSE
;
1818 src_gpr
= ctx
->temp_reg
;
1822 for (i
= 0; i
< 4; i
++) {
1823 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1824 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
1825 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
1828 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1829 alu
.dst
.sel
= ctx
->temp_reg
;
1834 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1838 src_gpr
= ctx
->temp_reg
;
1841 opcode
= ctx
->inst_info
->r600_opcode
;
1842 if (opcode
== SQ_TEX_INST_SAMPLE
&&
1843 (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
))
1844 opcode
= SQ_TEX_INST_SAMPLE_C
;
1846 memset(&tex
, 0, sizeof(struct r600_bc_tex
));
1848 tex
.sampler_id
= ctx
->file_offset
[inst
->Src
[1].Register
.File
] + inst
->Src
[1].Register
.Index
;
1849 tex
.resource_id
= tex
.sampler_id
;
1850 tex
.src_gpr
= src_gpr
;
1851 tex
.dst_gpr
= ctx
->file_offset
[inst
->Dst
[0].Register
.File
] + inst
->Dst
[0].Register
.Index
;
1852 tex
.dst_sel_x
= (inst
->Dst
[0].Register
.WriteMask
& 1) ? 0 : 7;
1853 tex
.dst_sel_y
= (inst
->Dst
[0].Register
.WriteMask
& 2) ? 1 : 7;
1854 tex
.dst_sel_z
= (inst
->Dst
[0].Register
.WriteMask
& 4) ? 2 : 7;
1855 tex
.dst_sel_w
= (inst
->Dst
[0].Register
.WriteMask
& 8) ? 3 : 7;
1861 if (inst
->Texture
.Texture
== TGSI_TEXTURE_CUBE
) {
1868 if (inst
->Texture
.Texture
!= TGSI_TEXTURE_RECT
) {
1869 tex
.coord_type_x
= 1;
1870 tex
.coord_type_y
= 1;
1871 tex
.coord_type_z
= 1;
1872 tex
.coord_type_w
= 1;
1875 if (inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW1D
|| inst
->Texture
.Texture
== TGSI_TEXTURE_SHADOW2D
)
1878 r
= r600_bc_add_tex(ctx
->bc
, &tex
);
1882 /* add shadow ambient support - gallium doesn't do it yet */
1886 static int tgsi_lrp(struct r600_shader_ctx
*ctx
)
1888 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
1889 struct r600_bc_alu_src r600_src
[3];
1890 struct r600_bc_alu alu
;
1891 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
1895 r
= tgsi_split_constant(ctx
, r600_src
);
1898 r
= tgsi_split_literal_constant(ctx
, r600_src
);
1902 /* optimize if it's just an equal balance */
1903 if(r600_src
[0].sel
== V_SQ_ALU_SRC_0_5
) {
1904 for (i
= 0; i
< lasti
+ 1; i
++) {
1905 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1908 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1909 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
1910 alu
.src
[0] = r600_src
[1];
1911 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[1], i
);
1912 alu
.src
[1] = r600_src
[2];
1913 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1915 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1923 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1931 for (i
= 0; i
< lasti
+ 1; i
++) {
1932 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1935 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1936 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
);
1937 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
1938 alu
.src
[0].chan
= 0;
1939 alu
.src
[1] = r600_src
[0];
1940 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[0], i
);
1942 alu
.dst
.sel
= ctx
->temp_reg
;
1948 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1953 /* (1 - src0) * src2 */
1954 for (i
= 0; i
< lasti
+ 1; i
++) {
1955 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1958 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1959 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
1960 alu
.src
[0].sel
= ctx
->temp_reg
;
1961 alu
.src
[0].chan
= i
;
1962 alu
.src
[1] = r600_src
[2];
1963 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
1964 alu
.dst
.sel
= ctx
->temp_reg
;
1970 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
1975 /* src0 * src1 + (1 - src0) * src2 */
1976 for (i
= 0; i
< lasti
+ 1; i
++) {
1977 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
1980 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
1981 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
1983 alu
.src
[0] = r600_src
[0];
1984 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
1985 alu
.src
[1] = r600_src
[1];
1986 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
1987 alu
.src
[2].sel
= ctx
->temp_reg
;
1988 alu
.src
[2].chan
= i
;
1990 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
1998 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2005 static int tgsi_cmp(struct r600_shader_ctx
*ctx
)
2007 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2008 struct r600_bc_alu_src r600_src
[3];
2009 struct r600_bc_alu alu
;
2011 int lasti
= tgsi_last_instruction(inst
->Dst
[0].Register
.WriteMask
);
2013 r
= tgsi_split_constant(ctx
, r600_src
);
2016 r
= tgsi_split_literal_constant(ctx
, r600_src
);
2020 for (i
= 0; i
< lasti
+ 1; i
++) {
2021 if (!(inst
->Dst
[0].Register
.WriteMask
& (1 << i
)))
2024 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2025 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE
);
2026 alu
.src
[0] = r600_src
[0];
2027 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
2029 alu
.src
[1] = r600_src
[2];
2030 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[2], i
);
2032 alu
.src
[2] = r600_src
[1];
2033 alu
.src
[2].chan
= tgsi_chan(&inst
->Src
[1], i
);
2035 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2044 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2051 static int tgsi_xpd(struct r600_shader_ctx
*ctx
)
2053 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2054 struct r600_bc_alu_src r600_src
[3];
2055 struct r600_bc_alu alu
;
2056 uint32_t use_temp
= 0;
2059 if (inst
->Dst
[0].Register
.WriteMask
!= 0xf)
2062 r
= tgsi_split_constant(ctx
, r600_src
);
2065 r
= tgsi_split_literal_constant(ctx
, r600_src
);
2069 for (i
= 0; i
< 4; i
++) {
2070 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2071 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2073 alu
.src
[0] = r600_src
[0];
2076 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
2079 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2082 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
2085 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2086 alu
.src
[0].chan
= i
;
2089 alu
.src
[1] = r600_src
[1];
2092 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
2095 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
2098 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
2101 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2102 alu
.src
[1].chan
= i
;
2105 alu
.dst
.sel
= ctx
->temp_reg
;
2111 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2116 for (i
= 0; i
< 4; i
++) {
2117 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2118 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
);
2120 alu
.src
[0] = r600_src
[0];
2123 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 1);
2126 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 2);
2129 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2132 alu
.src
[0].sel
= V_SQ_ALU_SRC_0
;
2133 alu
.src
[0].chan
= i
;
2136 alu
.src
[1] = r600_src
[1];
2139 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 2);
2142 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 0);
2145 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], 1);
2148 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2149 alu
.src
[1].chan
= i
;
2152 alu
.src
[2].sel
= ctx
->temp_reg
;
2154 alu
.src
[2].chan
= i
;
2157 alu
.dst
.sel
= ctx
->temp_reg
;
2159 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2168 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2173 return tgsi_helper_copy(ctx
, inst
);
2177 static int tgsi_exp(struct r600_shader_ctx
*ctx
)
2179 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2180 struct r600_bc_alu_src r600_src
[3] = { { 0 } };
2181 struct r600_bc_alu alu
;
2184 /* result.x = 2^floor(src); */
2185 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
2186 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2188 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2189 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2193 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2195 alu
.dst
.sel
= ctx
->temp_reg
;
2199 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2203 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2204 alu
.src
[0].sel
= ctx
->temp_reg
;
2205 alu
.src
[0].chan
= 0;
2207 alu
.dst
.sel
= ctx
->temp_reg
;
2211 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2216 /* result.y = tmp - floor(tmp); */
2217 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
2218 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2220 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
);
2221 alu
.src
[0] = r600_src
[0];
2222 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2225 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2227 alu
.dst
.sel
= ctx
->temp_reg
;
2228 // r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
2236 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2241 /* result.z = RoughApprox2ToX(tmp);*/
2242 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 0x1) {
2243 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2244 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2245 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2248 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2250 alu
.dst
.sel
= ctx
->temp_reg
;
2256 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2261 /* result.w = 1.0;*/
2262 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 0x1) {
2263 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2265 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2266 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2267 alu
.src
[0].chan
= 0;
2269 alu
.dst
.sel
= ctx
->temp_reg
;
2273 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2277 return tgsi_helper_copy(ctx
, inst
);
2280 static int tgsi_log(struct r600_shader_ctx
*ctx
)
2282 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2283 struct r600_bc_alu alu
;
2286 /* result.x = floor(log2(src)); */
2287 if (inst
->Dst
[0].Register
.WriteMask
& 1) {
2288 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2290 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2291 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2295 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2297 alu
.dst
.sel
= ctx
->temp_reg
;
2301 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2305 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2306 alu
.src
[0].sel
= ctx
->temp_reg
;
2307 alu
.src
[0].chan
= 0;
2309 alu
.dst
.sel
= ctx
->temp_reg
;
2314 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2319 /* result.y = src.x / (2 ^ floor(log2(src.x))); */
2320 if ((inst
->Dst
[0].Register
.WriteMask
>> 1) & 1) {
2321 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2323 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2324 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2328 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2330 alu
.dst
.sel
= ctx
->temp_reg
;
2335 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2339 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2341 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
);
2342 alu
.src
[0].sel
= ctx
->temp_reg
;
2343 alu
.src
[0].chan
= 1;
2345 alu
.dst
.sel
= ctx
->temp_reg
;
2350 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2354 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2356 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
);
2357 alu
.src
[0].sel
= ctx
->temp_reg
;
2358 alu
.src
[0].chan
= 1;
2360 alu
.dst
.sel
= ctx
->temp_reg
;
2365 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2369 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2371 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
);
2372 alu
.src
[0].sel
= ctx
->temp_reg
;
2373 alu
.src
[0].chan
= 1;
2375 alu
.dst
.sel
= ctx
->temp_reg
;
2380 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2384 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2386 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2388 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2392 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2394 alu
.src
[1].sel
= ctx
->temp_reg
;
2395 alu
.src
[1].chan
= 1;
2397 alu
.dst
.sel
= ctx
->temp_reg
;
2402 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2407 /* result.z = log2(src);*/
2408 if ((inst
->Dst
[0].Register
.WriteMask
>> 2) & 1) {
2409 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2411 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
);
2412 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2416 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2418 alu
.dst
.sel
= ctx
->temp_reg
;
2423 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2428 /* result.w = 1.0; */
2429 if ((inst
->Dst
[0].Register
.WriteMask
>> 3) & 1) {
2430 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2432 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
);
2433 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2434 alu
.src
[0].chan
= 0;
2436 alu
.dst
.sel
= ctx
->temp_reg
;
2441 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2446 return tgsi_helper_copy(ctx
, inst
);
2449 static int tgsi_eg_arl(struct r600_shader_ctx
*ctx
)
2451 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2452 struct r600_bc_alu alu
;
2454 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2456 switch (inst
->Instruction
.Opcode
) {
2457 case TGSI_OPCODE_ARL
:
2458 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR
;
2460 case TGSI_OPCODE_ARR
:
2461 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT
;
2468 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2471 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2474 alu
.dst
.sel
= ctx
->temp_reg
;
2476 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2479 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2480 alu
.inst
= EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT
;
2481 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2484 alu
.src
[0].sel
= ctx
->temp_reg
;
2485 alu
.src
[0].chan
= 0;
2487 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2492 static int tgsi_r600_arl(struct r600_shader_ctx
*ctx
)
2494 /* TODO from r600c, ar values don't persist between clauses */
2495 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2496 struct r600_bc_alu alu
;
2498 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2500 switch (inst
->Instruction
.Opcode
) {
2501 case TGSI_OPCODE_ARL
:
2502 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR
;
2504 case TGSI_OPCODE_ARR
:
2505 alu
.inst
= V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA
;
2513 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2516 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2520 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2523 ctx
->bc
->cf_last
->r6xx_uses_waterfall
= 1;
2527 static int tgsi_opdst(struct r600_shader_ctx
*ctx
)
2529 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2530 struct r600_bc_alu alu
;
2533 for (i
= 0; i
< 4; i
++) {
2534 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2536 alu
.inst
= CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
);
2537 r
= tgsi_dst(ctx
, &inst
->Dst
[0], i
, &alu
.dst
);
2541 if (i
== 0 || i
== 3) {
2542 alu
.src
[0].sel
= V_SQ_ALU_SRC_1
;
2544 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2547 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], i
);
2550 if (i
== 0 || i
== 2) {
2551 alu
.src
[1].sel
= V_SQ_ALU_SRC_1
;
2553 r
= tgsi_src(ctx
, &inst
->Src
[1], &alu
.src
[1]);
2556 alu
.src
[1].chan
= tgsi_chan(&inst
->Src
[1], i
);
2560 r
= r600_bc_add_alu(ctx
->bc
, &alu
);
2567 static int emit_logic_pred(struct r600_shader_ctx
*ctx
, int opcode
)
2569 struct tgsi_full_instruction
*inst
= &ctx
->parse
.FullToken
.FullInstruction
;
2570 struct r600_bc_alu alu
;
2573 memset(&alu
, 0, sizeof(struct r600_bc_alu
));
2577 alu
.dst
.sel
= ctx
->temp_reg
;
2581 r
= tgsi_src(ctx
, &inst
->Src
[0], &alu
.src
[0]);
2584 alu
.src
[0].chan
= tgsi_chan(&inst
->Src
[0], 0);
2585 alu
.src
[1].sel
= V_SQ_ALU_SRC_0
;
2586 alu
.src
[1].chan
= 0;
2590 r
= r600_bc_add_alu_type(ctx
->bc
, &alu
, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE
));
2596 static int pops(struct r600_shader_ctx
*ctx
, int pops
)
2599 if (ctx
->bc
->cf_last
) {
2600 if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU
) << 3)
2602 else if (ctx
->bc
->cf_last
->inst
== CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
) << 3)
2607 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP_AFTER
) << 3;
2608 ctx
->bc
->force_add_cf
= 1;
2609 } else if (alu_pop
== 2) {
2610 ctx
->bc
->cf_last
->inst
= CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_POP2_AFTER
) << 3;
2611 ctx
->bc
->force_add_cf
= 1;
2613 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP
));
2614 ctx
->bc
->cf_last
->pop_count
= pops
;
2615 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2620 static inline void callstack_decrease_current(struct r600_shader_ctx
*ctx
, unsigned reason
)
2624 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2628 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
-= 4;
2631 /* TOODO : for 16 vp asic should -= 2; */
2632 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
--;
2637 static inline void callstack_check_depth(struct r600_shader_ctx
*ctx
, unsigned reason
, unsigned check_max_only
)
2639 if (check_max_only
) {
2652 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
) >
2653 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2654 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2655 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+ diff
;
2661 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2665 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
+= 4;
2668 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
++;
2672 if ((ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
) >
2673 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
) {
2674 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].max
=
2675 ctx
->bc
->callstack
[ctx
->bc
->call_sp
].current
;
2679 static void fc_set_mid(struct r600_shader_ctx
*ctx
, int fc_sp
)
2681 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[fc_sp
];
2683 sp
->mid
= (struct r600_bc_cf
**)realloc((void *)sp
->mid
,
2684 sizeof(struct r600_bc_cf
*) * (sp
->num_mid
+ 1));
2685 sp
->mid
[sp
->num_mid
] = ctx
->bc
->cf_last
;
2689 static void fc_pushlevel(struct r600_shader_ctx
*ctx
, int type
)
2692 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
= type
;
2693 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
= ctx
->bc
->cf_last
;
2696 static void fc_poplevel(struct r600_shader_ctx
*ctx
)
2698 struct r600_cf_stack_entry
*sp
= &ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
];
2710 static int emit_return(struct r600_shader_ctx
*ctx
)
2712 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_RETURN
);
2716 static int emit_jump_to_offset(struct r600_shader_ctx
*ctx
, int pops
, int offset
)
2719 r600_bc_add_cfinst(ctx
->bc
, V_SQ_CF_WORD1_SQ_CF_INST_JUMP
);
2720 ctx
->bc
->cf_last
->pop_count
= pops
;
2721 /* TODO work out offset */
2725 static int emit_setret_in_loop_flag(struct r600_shader_ctx
*ctx
, unsigned flag_value
)
2730 static void emit_testflag(struct r600_shader_ctx
*ctx
)
2735 static void emit_return_on_flag(struct r600_shader_ctx
*ctx
, unsigned ifidx
)
2738 emit_jump_to_offset(ctx
, 1, 4);
2739 emit_setret_in_loop_flag(ctx
, V_SQ_ALU_SRC_0
);
2740 pops(ctx
, ifidx
+ 1);
2744 static void break_loop_on_flag(struct r600_shader_ctx
*ctx
, unsigned fc_sp
)
2748 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2749 ctx
->bc
->cf_last
->pop_count
= 1;
2751 fc_set_mid(ctx
, fc_sp
);
2757 static int tgsi_if(struct r600_shader_ctx
*ctx
)
2759 emit_logic_pred(ctx
, CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE
));
2761 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP
));
2763 fc_pushlevel(ctx
, FC_IF
);
2765 callstack_check_depth(ctx
, FC_PUSH_VPM
, 0);
2769 static int tgsi_else(struct r600_shader_ctx
*ctx
)
2771 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_ELSE
));
2772 ctx
->bc
->cf_last
->pop_count
= 1;
2774 fc_set_mid(ctx
, ctx
->bc
->fc_sp
);
2775 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
;
2779 static int tgsi_endif(struct r600_shader_ctx
*ctx
)
2782 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_IF
) {
2783 R600_ERR("if/endif unbalanced in shader\n");
2787 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
== NULL
) {
2788 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2789 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->pop_count
= 1;
2791 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[0]->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2795 callstack_decrease_current(ctx
, FC_PUSH_VPM
);
2799 static int tgsi_bgnloop(struct r600_shader_ctx
*ctx
)
2801 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL
));
2803 fc_pushlevel(ctx
, FC_LOOP
);
2805 /* check stack depth */
2806 callstack_check_depth(ctx
, FC_LOOP
, 0);
2810 static int tgsi_endloop(struct r600_shader_ctx
*ctx
)
2814 r600_bc_add_cfinst(ctx
->bc
, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END
));
2816 if (ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].type
!= FC_LOOP
) {
2817 R600_ERR("loop/endloop in shader code are not paired.\n");
2821 /* fixup loop pointers - from r600isa
2822 LOOP END points to CF after LOOP START,
2823 LOOP START point to CF after LOOP END
2824 BRK/CONT point to LOOP END CF
2826 ctx
->bc
->cf_last
->cf_addr
= ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->id
+ 2;
2828 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].start
->cf_addr
= ctx
->bc
->cf_last
->id
+ 2;
2830 for (i
= 0; i
< ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].num_mid
; i
++) {
2831 ctx
->bc
->fc_stack
[ctx
->bc
->fc_sp
].mid
[i
]->cf_addr
= ctx
->bc
->cf_last
->id
;
2833 /* TODO add LOOPRET support */
2835 callstack_decrease_current(ctx
, FC_LOOP
);
2839 static int tgsi_loop_brk_cont(struct r600_shader_ctx
*ctx
)
2843 for (fscp
= ctx
->bc
->fc_sp
; fscp
> 0; fscp
--)
2845 if (FC_LOOP
== ctx
->bc
->fc_stack
[fscp
].type
)
2850 R600_ERR("Break not inside loop/endloop pair\n");
2854 r600_bc_add_cfinst(ctx
->bc
, ctx
->inst_info
->r600_opcode
);
2855 ctx
->bc
->cf_last
->pop_count
= 1;
2857 fc_set_mid(ctx
, fscp
);
2860 callstack_check_depth(ctx
, FC_PUSH_VPM
, 1);
2864 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction
[] = {
2865 {TGSI_OPCODE_ARL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
2866 {TGSI_OPCODE_MOV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2867 {TGSI_OPCODE_LIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
2870 * For state trackers other than OpenGL, we'll want to use
2871 * _RECIP_IEEE instead.
2873 {TGSI_OPCODE_RCP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_CLAMPED
, tgsi_trans_srcx_replicate
},
2875 {TGSI_OPCODE_RSQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_rsq
},
2876 {TGSI_OPCODE_EXP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
2877 {TGSI_OPCODE_LOG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_log
},
2878 {TGSI_OPCODE_MUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
2879 {TGSI_OPCODE_ADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2880 {TGSI_OPCODE_DP3
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2881 {TGSI_OPCODE_DP4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2882 {TGSI_OPCODE_DST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
2883 {TGSI_OPCODE_MIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
2884 {TGSI_OPCODE_MAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
2885 {TGSI_OPCODE_SLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
2886 {TGSI_OPCODE_SGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
2887 {TGSI_OPCODE_MAD
, 1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
2888 {TGSI_OPCODE_SUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
2889 {TGSI_OPCODE_LRP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
2890 {TGSI_OPCODE_CND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2892 {20, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2893 {TGSI_OPCODE_DP2A
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2895 {22, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2896 {23, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2897 {TGSI_OPCODE_FRC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
2898 {TGSI_OPCODE_CLAMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2899 {TGSI_OPCODE_FLR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
2900 {TGSI_OPCODE_ROUND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2901 {TGSI_OPCODE_EX2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
2902 {TGSI_OPCODE_LG2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
2903 {TGSI_OPCODE_POW
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
2904 {TGSI_OPCODE_XPD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
2906 {32, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2907 {TGSI_OPCODE_ABS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
2908 {TGSI_OPCODE_RCC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2909 {TGSI_OPCODE_DPH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2910 {TGSI_OPCODE_COS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
2911 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
2912 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
2913 {TGSI_OPCODE_KILP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
2914 {TGSI_OPCODE_PK2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2915 {TGSI_OPCODE_PK2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2916 {TGSI_OPCODE_PK4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2917 {TGSI_OPCODE_PK4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2918 {TGSI_OPCODE_RFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2919 {TGSI_OPCODE_SEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
2920 {TGSI_OPCODE_SFL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2921 {TGSI_OPCODE_SGT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
2922 {TGSI_OPCODE_SIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
2923 {TGSI_OPCODE_SLE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
2924 {TGSI_OPCODE_SNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
2925 {TGSI_OPCODE_STR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2926 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2927 {TGSI_OPCODE_TXD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2928 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
2929 {TGSI_OPCODE_UP2H
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2930 {TGSI_OPCODE_UP2US
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2931 {TGSI_OPCODE_UP4B
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2932 {TGSI_OPCODE_UP4UB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2933 {TGSI_OPCODE_X2D
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2934 {TGSI_OPCODE_ARA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2935 {TGSI_OPCODE_ARR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_r600_arl
},
2936 {TGSI_OPCODE_BRA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2937 {TGSI_OPCODE_CAL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2938 {TGSI_OPCODE_RET
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2939 {TGSI_OPCODE_SSG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
2940 {TGSI_OPCODE_CMP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
2941 {TGSI_OPCODE_SCS
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
2942 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2943 {TGSI_OPCODE_NRM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2944 {TGSI_OPCODE_DIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2945 {TGSI_OPCODE_DP2
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
2946 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
2947 {TGSI_OPCODE_BRK
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
2948 {TGSI_OPCODE_IF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
2950 {75, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2951 {76, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2952 {TGSI_OPCODE_ELSE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
2953 {TGSI_OPCODE_ENDIF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
2955 {79, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2956 {80, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2957 {TGSI_OPCODE_PUSHA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2958 {TGSI_OPCODE_POPA
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2959 {TGSI_OPCODE_CEIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2960 {TGSI_OPCODE_I2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2961 {TGSI_OPCODE_NOT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2962 {TGSI_OPCODE_TRUNC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
2963 {TGSI_OPCODE_SHL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2965 {88, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2966 {TGSI_OPCODE_AND
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2967 {TGSI_OPCODE_OR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2968 {TGSI_OPCODE_MOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2969 {TGSI_OPCODE_XOR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2970 {TGSI_OPCODE_SAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2971 {TGSI_OPCODE_TXF
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2972 {TGSI_OPCODE_TXQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2973 {TGSI_OPCODE_CONT
, 0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
2974 {TGSI_OPCODE_EMIT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2975 {TGSI_OPCODE_ENDPRIM
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2976 {TGSI_OPCODE_BGNLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
2977 {TGSI_OPCODE_BGNSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2978 {TGSI_OPCODE_ENDLOOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
2979 {TGSI_OPCODE_ENDSUB
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2981 {103, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2982 {104, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2983 {105, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2984 {106, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2985 {TGSI_OPCODE_NOP
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2987 {108, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2988 {109, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2989 {110, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2990 {111, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2991 {TGSI_OPCODE_NRM4
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2992 {TGSI_OPCODE_CALLNZ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2993 {TGSI_OPCODE_IFC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2994 {TGSI_OPCODE_BREAKC
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2995 {TGSI_OPCODE_KIL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
2996 {TGSI_OPCODE_END
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
2998 {118, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
2999 {TGSI_OPCODE_F2I
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3000 {TGSI_OPCODE_IDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3001 {TGSI_OPCODE_IMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3002 {TGSI_OPCODE_IMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3003 {TGSI_OPCODE_INEG
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3004 {TGSI_OPCODE_ISGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3005 {TGSI_OPCODE_ISHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3006 {TGSI_OPCODE_ISLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3007 {TGSI_OPCODE_F2U
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3008 {TGSI_OPCODE_U2F
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3009 {TGSI_OPCODE_UADD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3010 {TGSI_OPCODE_UDIV
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3011 {TGSI_OPCODE_UMAD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3012 {TGSI_OPCODE_UMAX
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3013 {TGSI_OPCODE_UMIN
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3014 {TGSI_OPCODE_UMOD
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3015 {TGSI_OPCODE_UMUL
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3016 {TGSI_OPCODE_USEQ
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3017 {TGSI_OPCODE_USGE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3018 {TGSI_OPCODE_USHR
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3019 {TGSI_OPCODE_USLT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3020 {TGSI_OPCODE_USNE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3021 {TGSI_OPCODE_SWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3022 {TGSI_OPCODE_CASE
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3023 {TGSI_OPCODE_DEFAULT
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3024 {TGSI_OPCODE_ENDSWITCH
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3025 {TGSI_OPCODE_LAST
, 0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3028 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction
[] = {
3029 {TGSI_OPCODE_ARL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
3030 {TGSI_OPCODE_MOV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
3031 {TGSI_OPCODE_LIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lit
},
3032 {TGSI_OPCODE_RCP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE
, tgsi_trans_srcx_replicate
},
3033 {TGSI_OPCODE_RSQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE
, tgsi_trans_srcx_replicate
},
3034 {TGSI_OPCODE_EXP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_exp
},
3035 {TGSI_OPCODE_LOG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3036 {TGSI_OPCODE_MUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL
, tgsi_op2
},
3037 {TGSI_OPCODE_ADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
3038 {TGSI_OPCODE_DP3
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3039 {TGSI_OPCODE_DP4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3040 {TGSI_OPCODE_DST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_opdst
},
3041 {TGSI_OPCODE_MIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN
, tgsi_op2
},
3042 {TGSI_OPCODE_MAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX
, tgsi_op2
},
3043 {TGSI_OPCODE_SLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2_swap
},
3044 {TGSI_OPCODE_SGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2
},
3045 {TGSI_OPCODE_MAD
, 1, EG_V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD
, tgsi_op3
},
3046 {TGSI_OPCODE_SUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD
, tgsi_op2
},
3047 {TGSI_OPCODE_LRP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_lrp
},
3048 {TGSI_OPCODE_CND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3050 {20, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3051 {TGSI_OPCODE_DP2A
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3053 {22, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3054 {23, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3055 {TGSI_OPCODE_FRC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT
, tgsi_op2
},
3056 {TGSI_OPCODE_CLAMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3057 {TGSI_OPCODE_FLR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR
, tgsi_op2
},
3058 {TGSI_OPCODE_ROUND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3059 {TGSI_OPCODE_EX2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE
, tgsi_trans_srcx_replicate
},
3060 {TGSI_OPCODE_LG2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE
, tgsi_trans_srcx_replicate
},
3061 {TGSI_OPCODE_POW
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_pow
},
3062 {TGSI_OPCODE_XPD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_xpd
},
3064 {32, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3065 {TGSI_OPCODE_ABS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV
, tgsi_op2
},
3066 {TGSI_OPCODE_RCC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3067 {TGSI_OPCODE_DPH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3068 {TGSI_OPCODE_COS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS
, tgsi_trig
},
3069 {TGSI_OPCODE_DDX
, 0, SQ_TEX_INST_GET_GRADIENTS_H
, tgsi_tex
},
3070 {TGSI_OPCODE_DDY
, 0, SQ_TEX_INST_GET_GRADIENTS_V
, tgsi_tex
},
3071 {TGSI_OPCODE_KILP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* predicated kill */
3072 {TGSI_OPCODE_PK2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3073 {TGSI_OPCODE_PK2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3074 {TGSI_OPCODE_PK4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3075 {TGSI_OPCODE_PK4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3076 {TGSI_OPCODE_RFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3077 {TGSI_OPCODE_SEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE
, tgsi_op2
},
3078 {TGSI_OPCODE_SFL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3079 {TGSI_OPCODE_SGT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT
, tgsi_op2
},
3080 {TGSI_OPCODE_SIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN
, tgsi_trig
},
3081 {TGSI_OPCODE_SLE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE
, tgsi_op2_swap
},
3082 {TGSI_OPCODE_SNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE
, tgsi_op2
},
3083 {TGSI_OPCODE_STR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3084 {TGSI_OPCODE_TEX
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3085 {TGSI_OPCODE_TXD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3086 {TGSI_OPCODE_TXP
, 0, SQ_TEX_INST_SAMPLE
, tgsi_tex
},
3087 {TGSI_OPCODE_UP2H
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3088 {TGSI_OPCODE_UP2US
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3089 {TGSI_OPCODE_UP4B
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3090 {TGSI_OPCODE_UP4UB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3091 {TGSI_OPCODE_X2D
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3092 {TGSI_OPCODE_ARA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3093 {TGSI_OPCODE_ARR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_eg_arl
},
3094 {TGSI_OPCODE_BRA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3095 {TGSI_OPCODE_CAL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3096 {TGSI_OPCODE_RET
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3097 {TGSI_OPCODE_SSG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_ssg
},
3098 {TGSI_OPCODE_CMP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_cmp
},
3099 {TGSI_OPCODE_SCS
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_scs
},
3100 {TGSI_OPCODE_TXB
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
3101 {TGSI_OPCODE_NRM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3102 {TGSI_OPCODE_DIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3103 {TGSI_OPCODE_DP2
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4
, tgsi_dp
},
3104 {TGSI_OPCODE_TXL
, 0, SQ_TEX_INST_SAMPLE_L
, tgsi_tex
},
3105 {TGSI_OPCODE_BRK
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK
, tgsi_loop_brk_cont
},
3106 {TGSI_OPCODE_IF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_if
},
3108 {75, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3109 {76, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3110 {TGSI_OPCODE_ELSE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_else
},
3111 {TGSI_OPCODE_ENDIF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endif
},
3113 {79, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3114 {80, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3115 {TGSI_OPCODE_PUSHA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3116 {TGSI_OPCODE_POPA
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3117 {TGSI_OPCODE_CEIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3118 {TGSI_OPCODE_I2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3119 {TGSI_OPCODE_NOT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3120 {TGSI_OPCODE_TRUNC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC
, tgsi_trans_srcx_replicate
},
3121 {TGSI_OPCODE_SHL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3123 {88, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3124 {TGSI_OPCODE_AND
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3125 {TGSI_OPCODE_OR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3126 {TGSI_OPCODE_MOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3127 {TGSI_OPCODE_XOR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3128 {TGSI_OPCODE_SAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3129 {TGSI_OPCODE_TXF
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3130 {TGSI_OPCODE_TXQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3131 {TGSI_OPCODE_CONT
, 0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE
, tgsi_loop_brk_cont
},
3132 {TGSI_OPCODE_EMIT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3133 {TGSI_OPCODE_ENDPRIM
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3134 {TGSI_OPCODE_BGNLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_bgnloop
},
3135 {TGSI_OPCODE_BGNSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3136 {TGSI_OPCODE_ENDLOOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_endloop
},
3137 {TGSI_OPCODE_ENDSUB
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3139 {103, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3140 {104, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3141 {105, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3142 {106, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3143 {TGSI_OPCODE_NOP
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3145 {108, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3146 {109, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3147 {110, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3148 {111, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3149 {TGSI_OPCODE_NRM4
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3150 {TGSI_OPCODE_CALLNZ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3151 {TGSI_OPCODE_IFC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3152 {TGSI_OPCODE_BREAKC
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3153 {TGSI_OPCODE_KIL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT
, tgsi_kill
}, /* conditional kill */
3154 {TGSI_OPCODE_END
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_end
}, /* aka HALT */
3156 {118, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3157 {TGSI_OPCODE_F2I
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3158 {TGSI_OPCODE_IDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3159 {TGSI_OPCODE_IMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3160 {TGSI_OPCODE_IMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3161 {TGSI_OPCODE_INEG
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3162 {TGSI_OPCODE_ISGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3163 {TGSI_OPCODE_ISHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3164 {TGSI_OPCODE_ISLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3165 {TGSI_OPCODE_F2U
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3166 {TGSI_OPCODE_U2F
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3167 {TGSI_OPCODE_UADD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3168 {TGSI_OPCODE_UDIV
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3169 {TGSI_OPCODE_UMAD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3170 {TGSI_OPCODE_UMAX
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3171 {TGSI_OPCODE_UMIN
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3172 {TGSI_OPCODE_UMOD
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3173 {TGSI_OPCODE_UMUL
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3174 {TGSI_OPCODE_USEQ
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3175 {TGSI_OPCODE_USGE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3176 {TGSI_OPCODE_USHR
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3177 {TGSI_OPCODE_USLT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3178 {TGSI_OPCODE_USNE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3179 {TGSI_OPCODE_SWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3180 {TGSI_OPCODE_CASE
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3181 {TGSI_OPCODE_DEFAULT
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3182 {TGSI_OPCODE_ENDSWITCH
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},
3183 {TGSI_OPCODE_LAST
, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP
, tgsi_unsupported
},