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Merge branch 'xa_branch'
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include "util/u_transfer.h"
41 #include <pipebuffer/pb_buffer.h>
42 #include "r600.h"
43 #include "r600d.h"
44 #include "r600_resource.h"
45 #include "r600_shader.h"
46 #include "r600_pipe.h"
47 #include "r600_state_inlines.h"
48
49 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
50 {
51 struct r600_pipe_state state;
52
53 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
54 state.nregs = 0;
55 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
56 float offset_units = rctx->rasterizer->offset_units;
57 unsigned offset_db_fmt_cntl = 0, depth;
58
59 switch (rctx->framebuffer.zsbuf->texture->format) {
60 case PIPE_FORMAT_Z24X8_UNORM:
61 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
62 depth = -24;
63 offset_units *= 2.0f;
64 break;
65 case PIPE_FORMAT_Z32_FLOAT:
66 depth = -23;
67 offset_units *= 1.0f;
68 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
69 break;
70 case PIPE_FORMAT_Z16_UNORM:
71 depth = -16;
72 offset_units *= 4.0f;
73 break;
74 default:
75 return;
76 }
77 /* FIXME some of those reg can be computed with cso */
78 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
79 r600_pipe_state_add_reg(&state,
80 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
81 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
82 r600_pipe_state_add_reg(&state,
83 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
84 fui(offset_units), 0xFFFFFFFF, NULL);
85 r600_pipe_state_add_reg(&state,
86 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
87 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
88 r600_pipe_state_add_reg(&state,
89 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
90 fui(offset_units), 0xFFFFFFFF, NULL);
91 r600_pipe_state_add_reg(&state,
92 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
93 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
94 r600_context_pipe_state_set(&rctx->ctx, &state);
95 }
96 }
97
98 static void r600_set_blend_color(struct pipe_context *ctx,
99 const struct pipe_blend_color *state)
100 {
101 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
102 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
103
104 if (rstate == NULL)
105 return;
106
107 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
108 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
109 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
110 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
111 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
112 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
113 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
114 r600_context_pipe_state_set(&rctx->ctx, rstate);
115 }
116
117 static void *r600_create_blend_state(struct pipe_context *ctx,
118 const struct pipe_blend_state *state)
119 {
120 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
121 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
122 struct r600_pipe_state *rstate;
123 u32 color_control = 0, target_mask;
124
125 if (blend == NULL) {
126 return NULL;
127 }
128 rstate = &blend->rstate;
129
130 rstate->id = R600_PIPE_STATE_BLEND;
131
132 target_mask = 0;
133
134 /* R600 does not support per-MRT blends */
135 if (rctx->family > CHIP_R600)
136 color_control |= S_028808_PER_MRT_BLEND(1);
137 if (state->logicop_enable) {
138 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
139 } else {
140 color_control |= (0xcc << 16);
141 }
142 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
143 if (state->independent_blend_enable) {
144 for (int i = 0; i < 8; i++) {
145 if (state->rt[i].blend_enable) {
146 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
147 }
148 target_mask |= (state->rt[i].colormask << (4 * i));
149 }
150 } else {
151 for (int i = 0; i < 8; i++) {
152 if (state->rt[0].blend_enable) {
153 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
154 }
155 target_mask |= (state->rt[0].colormask << (4 * i));
156 }
157 }
158 blend->cb_target_mask = target_mask;
159 /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
160 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
161 color_control, 0xFFFFFFFD, NULL);
162
163 for (int i = 0; i < 8; i++) {
164 /* state->rt entries > 0 only written if independent blending */
165 const int j = state->independent_blend_enable ? i : 0;
166
167 unsigned eqRGB = state->rt[j].rgb_func;
168 unsigned srcRGB = state->rt[j].rgb_src_factor;
169 unsigned dstRGB = state->rt[j].rgb_dst_factor;
170
171 unsigned eqA = state->rt[j].alpha_func;
172 unsigned srcA = state->rt[j].alpha_src_factor;
173 unsigned dstA = state->rt[j].alpha_dst_factor;
174 uint32_t bc = 0;
175
176 if (!state->rt[j].blend_enable)
177 continue;
178
179 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
180 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
181 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
182
183 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
184 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
185 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
186 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
187 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
188 }
189
190 /* R600 does not support per-MRT blends */
191 if (rctx->family > CHIP_R600)
192 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
193 if (i == 0)
194 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
195 }
196 return rstate;
197 }
198
199 static void *r600_create_dsa_state(struct pipe_context *ctx,
200 const struct pipe_depth_stencil_alpha_state *state)
201 {
202 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
203 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
204 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
205 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
206 struct r600_pipe_state *rstate;
207
208 if (dsa == NULL) {
209 return NULL;
210 }
211
212 rstate = &dsa->rstate;
213
214 rstate->id = R600_PIPE_STATE_DSA;
215 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
216 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
217 stencil_ref_mask = 0;
218 stencil_ref_mask_bf = 0;
219 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
220 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
221 S_028800_ZFUNC(state->depth.func);
222
223 /* stencil */
224 if (state->stencil[0].enabled) {
225 db_depth_control |= S_028800_STENCIL_ENABLE(1);
226 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
227 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
228 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
229 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
230
231
232 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
233 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
234 if (state->stencil[1].enabled) {
235 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
236 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
237 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
238 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
239 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
240 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
241 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
242 }
243 }
244
245 /* alpha */
246 alpha_test_control = 0;
247 alpha_ref = 0;
248 if (state->alpha.enabled) {
249 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
250 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
251 alpha_ref = fui(state->alpha.ref_value);
252 }
253 dsa->alpha_ref = alpha_ref;
254
255 /* misc */
256 db_render_control = 0;
257 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
258 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
259 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
260 /* TODO db_render_override depends on query */
261 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
262 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
263 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
264 r600_pipe_state_add_reg(rstate,
265 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
266 0xFFFFFFFF & C_028430_STENCILREF, NULL);
267 r600_pipe_state_add_reg(rstate,
268 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
269 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
270 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
271 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
272 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
273 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
274 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
275 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
276 * r600_pipe_shader_ps().*/
277 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
278 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
279 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
280 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
281 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
282 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
283
284 return rstate;
285 }
286
287 static void *r600_create_rs_state(struct pipe_context *ctx,
288 const struct pipe_rasterizer_state *state)
289 {
290 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
291 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
292 struct r600_pipe_state *rstate;
293 unsigned tmp;
294 unsigned prov_vtx = 1, polygon_dual_mode;
295 unsigned clip_rule;
296
297 if (rs == NULL) {
298 return NULL;
299 }
300
301 rstate = &rs->rstate;
302 rs->clamp_vertex_color = state->clamp_vertex_color;
303 rs->clamp_fragment_color = state->clamp_fragment_color;
304 rs->flatshade = state->flatshade;
305 rs->sprite_coord_enable = state->sprite_coord_enable;
306
307 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
308 /* offset */
309 rs->offset_units = state->offset_units;
310 rs->offset_scale = state->offset_scale * 12.0f;
311
312 rstate->id = R600_PIPE_STATE_RASTERIZER;
313 if (state->flatshade_first)
314 prov_vtx = 0;
315 tmp = S_0286D4_FLAT_SHADE_ENA(1);
316 if (state->sprite_coord_enable) {
317 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
318 S_0286D4_PNT_SPRITE_OVRD_X(2) |
319 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
320 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
321 S_0286D4_PNT_SPRITE_OVRD_W(1);
322 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
323 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
324 }
325 }
326 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
327
328 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
329 state->fill_back != PIPE_POLYGON_MODE_FILL);
330 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
331 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
332 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
333 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
334 S_028814_FACE(!state->front_ccw) |
335 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
336 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
337 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
338 S_028814_POLY_MODE(polygon_dual_mode) |
339 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
340 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
341 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
342 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
343 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
344 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
345 /* point size 12.4 fixed point */
346 tmp = (unsigned)(state->point_size * 8.0);
347 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
348 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
349
350 tmp = (unsigned)state->line_width * 8;
351 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
352
353 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
354 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
355 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
356
357 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
358 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
359 0xFFFFFFFF, NULL);
360
361 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
362 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
363 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
364 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
365 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
366 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
367
368 return rstate;
369 }
370
371 static void *r600_create_sampler_state(struct pipe_context *ctx,
372 const struct pipe_sampler_state *state)
373 {
374 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
375 struct r600_pipe_state *rstate;
376 union util_color uc;
377 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
378
379 if (ss == NULL) {
380 return NULL;
381 }
382
383 ss->seamless_cube_map = state->seamless_cube_map;
384 rstate = &ss->rstate;
385 rstate->id = R600_PIPE_STATE_SAMPLER;
386 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
387 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
388 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
389 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
390 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
391 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
392 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
393 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
394 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
395 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
396 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
397 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
398 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
399 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
400 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
401 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
402 if (uc.ui) {
403 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
404 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
405 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
406 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
407 }
408 return rstate;
409 }
410
411 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
412 struct pipe_resource *texture,
413 const struct pipe_sampler_view *state)
414 {
415 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
416 struct r600_pipe_resource_state *rstate;
417 const struct util_format_description *desc;
418 struct r600_resource_texture *tmp;
419 struct r600_resource *rbuffer;
420 unsigned format, endian;
421 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
422 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
423 struct r600_bo *bo[2];
424 unsigned width, height, depth, offset_level, last_level;
425
426 if (resource == NULL)
427 return NULL;
428 rstate = &resource->state;
429
430 /* initialize base object */
431 resource->base = *state;
432 resource->base.texture = NULL;
433 pipe_reference(NULL, &texture->reference);
434 resource->base.texture = texture;
435 resource->base.reference.count = 1;
436 resource->base.context = ctx;
437
438 swizzle[0] = state->swizzle_r;
439 swizzle[1] = state->swizzle_g;
440 swizzle[2] = state->swizzle_b;
441 swizzle[3] = state->swizzle_a;
442 format = r600_translate_texformat(ctx->screen, state->format,
443 swizzle,
444 &word4, &yuv_format);
445 if (format == ~0) {
446 format = 0;
447 }
448 desc = util_format_description(state->format);
449 if (desc == NULL) {
450 R600_ERR("unknown format %d\n", state->format);
451 }
452 tmp = (struct r600_resource_texture *)texture;
453 if (tmp->depth && !tmp->is_flushing_texture) {
454 r600_texture_depth_flush(ctx, texture, TRUE);
455 tmp = tmp->flushed_depth_texture;
456 }
457 endian = r600_colorformat_endian_swap(format);
458
459 if (tmp->force_int_type) {
460 word4 &= C_038010_NUM_FORMAT_ALL;
461 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
462 }
463 rbuffer = &tmp->resource;
464 bo[0] = rbuffer->bo;
465 bo[1] = rbuffer->bo;
466
467 offset_level = state->u.tex.first_level;
468 last_level = state->u.tex.last_level - offset_level;
469 width = u_minify(texture->width0, offset_level);
470 height = u_minify(texture->height0, offset_level);
471 depth = u_minify(texture->depth0, offset_level);
472
473 pitch = align(tmp->pitch_in_blocks[offset_level] *
474 util_format_get_blockwidth(state->format), 8);
475 array_mode = tmp->array_mode[offset_level];
476 tile_type = tmp->tile_type;
477
478 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
479 height = 1;
480 depth = texture->array_size;
481 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
482 depth = texture->array_size;
483 }
484
485 rstate->bo[0] = bo[0];
486 rstate->bo[1] = bo[1];
487
488 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
489 S_038000_TILE_MODE(array_mode) |
490 S_038000_TILE_TYPE(tile_type) |
491 S_038000_PITCH((pitch / 8) - 1) |
492 S_038000_TEX_WIDTH(width - 1));
493 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
494 S_038004_TEX_DEPTH(depth - 1) |
495 S_038004_DATA_FORMAT(format));
496 rstate->val[2] = (tmp->offset[offset_level] + r600_bo_offset(bo[0])) >> 8;
497 rstate->val[3] = (tmp->offset[offset_level+1] + r600_bo_offset(bo[1])) >> 8;
498 rstate->val[4] = (word4 |
499 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
500 S_038010_REQUEST_SIZE(1) |
501 S_038010_ENDIAN_SWAP(endian) |
502 S_038010_BASE_LEVEL(0));
503 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
504 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
505 S_038014_LAST_ARRAY(state->u.tex.last_layer));
506 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
507 S_038018_MAX_ANISO(4 /* max 16 samples */));
508
509 return &resource->base;
510 }
511
512 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
513 struct pipe_sampler_view **views)
514 {
515 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
516 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
517
518 for (int i = 0; i < count; i++) {
519 if (resource[i]) {
520 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
521 i + R600_MAX_CONST_BUFFERS);
522 }
523 }
524 }
525
526 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
527 struct pipe_sampler_view **views)
528 {
529 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
530 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
531 int i;
532 int has_depth = 0;
533
534 for (i = 0; i < count; i++) {
535 if (&rctx->ps_samplers.views[i]->base != views[i]) {
536 if (resource[i]) {
537 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
538 has_depth = 1;
539 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
540 i + R600_MAX_CONST_BUFFERS);
541 } else
542 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
543 i + R600_MAX_CONST_BUFFERS);
544
545 pipe_sampler_view_reference(
546 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
547 views[i]);
548
549 } else {
550 if (resource[i]) {
551 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
552 has_depth = 1;
553 }
554 }
555 }
556 for (i = count; i < NUM_TEX_UNITS; i++) {
557 if (rctx->ps_samplers.views[i]) {
558 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
559 i + R600_MAX_CONST_BUFFERS);
560 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
561 }
562 }
563 rctx->have_depth_texture = has_depth;
564 rctx->ps_samplers.n_views = count;
565 }
566
567 static void r600_set_seamless_cubemap(struct r600_pipe_context *rctx, boolean enable)
568 {
569 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
570 if (rstate == NULL)
571 return;
572
573 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
574 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
575 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)),
576 1, NULL);
577
578 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
579 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
580 r600_context_pipe_state_set(&rctx->ctx, rstate);
581 }
582
583 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
584 {
585 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
586 struct r600_pipe_sampler_state **sstates = (struct r600_pipe_sampler_state **)states;
587 int seamless = -1;
588
589 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
590 rctx->ps_samplers.n_samplers = count;
591
592 for (int i = 0; i < count; i++) {
593 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, &sstates[i]->rstate, i);
594
595 if (sstates[i])
596 seamless = sstates[i]->seamless_cube_map;
597 }
598
599 if (seamless != -1)
600 r600_set_seamless_cubemap(rctx, seamless);
601 }
602
603 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
604 {
605 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
606 struct r600_pipe_sampler_state **sstates = (struct r600_pipe_sampler_state **)states;
607 int seamless = -1;
608
609 for (int i = 0; i < count; i++) {
610 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, &sstates[i]->rstate, i);
611
612 if (sstates[i])
613 seamless = sstates[i]->seamless_cube_map;
614 }
615
616 if (seamless != -1)
617 r600_set_seamless_cubemap(rctx, seamless);
618 }
619
620 static void r600_set_clip_state(struct pipe_context *ctx,
621 const struct pipe_clip_state *state)
622 {
623 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
624 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
625
626 if (rstate == NULL)
627 return;
628
629 rctx->clip = *state;
630 rstate->id = R600_PIPE_STATE_CLIP;
631 for (int i = 0; i < state->nr; i++) {
632 r600_pipe_state_add_reg(rstate,
633 R_028E20_PA_CL_UCP0_X + i * 16,
634 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
635 r600_pipe_state_add_reg(rstate,
636 R_028E24_PA_CL_UCP0_Y + i * 16,
637 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
638 r600_pipe_state_add_reg(rstate,
639 R_028E28_PA_CL_UCP0_Z + i * 16,
640 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
641 r600_pipe_state_add_reg(rstate,
642 R_028E2C_PA_CL_UCP0_W + i * 16,
643 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
644 }
645 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
646 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
647 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
648 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
649
650 free(rctx->states[R600_PIPE_STATE_CLIP]);
651 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
652 r600_context_pipe_state_set(&rctx->ctx, rstate);
653 }
654
655 static void r600_set_polygon_stipple(struct pipe_context *ctx,
656 const struct pipe_poly_stipple *state)
657 {
658 }
659
660 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
661 {
662 }
663
664 static void r600_set_scissor_state(struct pipe_context *ctx,
665 const struct pipe_scissor_state *state)
666 {
667 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
668 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
669 u32 tl, br;
670
671 if (rstate == NULL)
672 return;
673
674 rstate->id = R600_PIPE_STATE_SCISSOR;
675 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
676 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
677 r600_pipe_state_add_reg(rstate,
678 R_028210_PA_SC_CLIPRECT_0_TL, tl,
679 0xFFFFFFFF, NULL);
680 r600_pipe_state_add_reg(rstate,
681 R_028214_PA_SC_CLIPRECT_0_BR, br,
682 0xFFFFFFFF, NULL);
683 r600_pipe_state_add_reg(rstate,
684 R_028218_PA_SC_CLIPRECT_1_TL, tl,
685 0xFFFFFFFF, NULL);
686 r600_pipe_state_add_reg(rstate,
687 R_02821C_PA_SC_CLIPRECT_1_BR, br,
688 0xFFFFFFFF, NULL);
689 r600_pipe_state_add_reg(rstate,
690 R_028220_PA_SC_CLIPRECT_2_TL, tl,
691 0xFFFFFFFF, NULL);
692 r600_pipe_state_add_reg(rstate,
693 R_028224_PA_SC_CLIPRECT_2_BR, br,
694 0xFFFFFFFF, NULL);
695 r600_pipe_state_add_reg(rstate,
696 R_028228_PA_SC_CLIPRECT_3_TL, tl,
697 0xFFFFFFFF, NULL);
698 r600_pipe_state_add_reg(rstate,
699 R_02822C_PA_SC_CLIPRECT_3_BR, br,
700 0xFFFFFFFF, NULL);
701
702 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
703 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
704 r600_context_pipe_state_set(&rctx->ctx, rstate);
705 }
706
707 static void r600_set_stencil_ref(struct pipe_context *ctx,
708 const struct pipe_stencil_ref *state)
709 {
710 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
711 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
712 u32 tmp;
713
714 if (rstate == NULL)
715 return;
716
717 rctx->stencil_ref = *state;
718 rstate->id = R600_PIPE_STATE_STENCIL_REF;
719 tmp = S_028430_STENCILREF(state->ref_value[0]);
720 r600_pipe_state_add_reg(rstate,
721 R_028430_DB_STENCILREFMASK, tmp,
722 ~C_028430_STENCILREF, NULL);
723 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
724 r600_pipe_state_add_reg(rstate,
725 R_028434_DB_STENCILREFMASK_BF, tmp,
726 ~C_028434_STENCILREF_BF, NULL);
727
728 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
729 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
730 r600_context_pipe_state_set(&rctx->ctx, rstate);
731 }
732
733 static void r600_set_viewport_state(struct pipe_context *ctx,
734 const struct pipe_viewport_state *state)
735 {
736 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
737 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
738
739 if (rstate == NULL)
740 return;
741
742 rctx->viewport = *state;
743 rstate->id = R600_PIPE_STATE_VIEWPORT;
744 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
745 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
746 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
747 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
748 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
749 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
750 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
751 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
752 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
753
754 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
755 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
756 r600_context_pipe_state_set(&rctx->ctx, rstate);
757 }
758
759 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
760 const struct pipe_framebuffer_state *state, int cb)
761 {
762 struct r600_resource_texture *rtex;
763 struct r600_resource *rbuffer;
764 struct r600_surface *surf;
765 unsigned level = state->cbufs[cb]->u.tex.level;
766 unsigned pitch, slice;
767 unsigned color_info;
768 unsigned format, swap, ntype, endian;
769 unsigned offset;
770 const struct util_format_description *desc;
771 struct r600_bo *bo[3];
772 int i;
773
774 surf = (struct r600_surface *)state->cbufs[cb];
775 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
776
777 if (rtex->depth)
778 rctx->have_depth_fb = TRUE;
779
780 if (rtex->depth && !rtex->is_flushing_texture) {
781 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
782 rtex = rtex->flushed_depth_texture;
783 }
784
785 rbuffer = &rtex->resource;
786 bo[0] = rbuffer->bo;
787 bo[1] = rbuffer->bo;
788 bo[2] = rbuffer->bo;
789
790 /* XXX quite sure for dx10+ hw don't need any offset hacks */
791 offset = r600_texture_get_offset(rtex,
792 level, state->cbufs[cb]->u.tex.first_layer);
793 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
794 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
795 desc = util_format_description(surf->base.format);
796
797 for (i = 0; i < 4; i++) {
798 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
799 break;
800 }
801 }
802 ntype = V_0280A0_NUMBER_UNORM;
803 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
804 ntype = V_0280A0_NUMBER_SRGB;
805 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
806 ntype = V_0280A0_NUMBER_SNORM;
807
808 format = r600_translate_colorformat(surf->base.format);
809 swap = r600_translate_colorswap(surf->base.format);
810 if(rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
811 endian = ENDIAN_NONE;
812 } else {
813 endian = r600_colorformat_endian_swap(format);
814 }
815
816 /* disable when gallium grows int textures */
817 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
818 ntype = V_0280A0_NUMBER_UINT;
819
820 color_info = S_0280A0_FORMAT(format) |
821 S_0280A0_COMP_SWAP(swap) |
822 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
823 S_0280A0_BLEND_CLAMP(1) |
824 S_0280A0_NUMBER_TYPE(ntype) |
825 S_0280A0_ENDIAN(endian);
826
827 /* EXPORT_NORM is an optimzation that can be enabled for better
828 * performance in certain cases
829 */
830 if (rctx->family < CHIP_RV770) {
831 /* EXPORT_NORM can be enabled if:
832 * - 11-bit or smaller UNORM/SNORM/SRGB
833 * - BLEND_CLAMP is enabled
834 * - BLEND_FLOAT32 is disabled
835 */
836 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
837 (desc->channel[i].size < 12 &&
838 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
839 ntype != V_0280A0_NUMBER_UINT &&
840 ntype != V_0280A0_NUMBER_SINT) &&
841 G_0280A0_BLEND_CLAMP(color_info) &&
842 !G_0280A0_BLEND_FLOAT32(color_info))
843 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
844 } else {
845 /* EXPORT_NORM can be enabled if:
846 * - 11-bit or smaller UNORM/SNORM/SRGB
847 * - 16-bit or smaller FLOAT
848 */
849 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
850 ((desc->channel[i].size < 12 &&
851 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
852 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
853 (desc->channel[i].size < 17 &&
854 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
855 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
856 }
857
858 r600_pipe_state_add_reg(rstate,
859 R_028040_CB_COLOR0_BASE + cb * 4,
860 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
861 r600_pipe_state_add_reg(rstate,
862 R_0280A0_CB_COLOR0_INFO + cb * 4,
863 color_info, 0xFFFFFFFF, bo[0]);
864 r600_pipe_state_add_reg(rstate,
865 R_028060_CB_COLOR0_SIZE + cb * 4,
866 S_028060_PITCH_TILE_MAX(pitch) |
867 S_028060_SLICE_TILE_MAX(slice),
868 0xFFFFFFFF, NULL);
869 r600_pipe_state_add_reg(rstate,
870 R_028080_CB_COLOR0_VIEW + cb * 4,
871 0x00000000, 0xFFFFFFFF, NULL);
872 r600_pipe_state_add_reg(rstate,
873 R_0280E0_CB_COLOR0_FRAG + cb * 4,
874 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
875 r600_pipe_state_add_reg(rstate,
876 R_0280C0_CB_COLOR0_TILE + cb * 4,
877 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
878 r600_pipe_state_add_reg(rstate,
879 R_028100_CB_COLOR0_MASK + cb * 4,
880 0x00000000, 0xFFFFFFFF, NULL);
881 }
882
883 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
884 const struct pipe_framebuffer_state *state)
885 {
886 struct r600_resource_texture *rtex;
887 struct r600_resource *rbuffer;
888 struct r600_surface *surf;
889 unsigned level;
890 unsigned pitch, slice, format;
891 unsigned offset;
892
893 if (state->zsbuf == NULL)
894 return;
895
896 level = state->zsbuf->u.tex.level;
897
898 surf = (struct r600_surface *)state->zsbuf;
899 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
900
901 rbuffer = &rtex->resource;
902
903 /* XXX quite sure for dx10+ hw don't need any offset hacks */
904 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
905 level, state->zsbuf->u.tex.first_layer);
906 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
907 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
908 format = r600_translate_dbformat(state->zsbuf->texture->format);
909
910 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
911 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
912 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
913 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
914 0xFFFFFFFF, NULL);
915 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
916 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
917 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
918 0xFFFFFFFF, rbuffer->bo);
919 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
920 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
921 }
922
923 static void r600_set_framebuffer_state(struct pipe_context *ctx,
924 const struct pipe_framebuffer_state *state)
925 {
926 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
927 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
928 u32 shader_mask, tl, br, shader_control, target_mask;
929
930 if (rstate == NULL)
931 return;
932
933 r600_context_flush_dest_caches(&rctx->ctx);
934 rctx->ctx.num_dest_buffers = state->nr_cbufs;
935
936 /* unreference old buffer and reference new one */
937 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
938
939 util_copy_framebuffer_state(&rctx->framebuffer, state);
940
941 /* build states */
942 rctx->have_depth_fb = 0;
943 for (int i = 0; i < state->nr_cbufs; i++) {
944 r600_cb(rctx, rstate, state, i);
945 }
946 if (state->zsbuf) {
947 r600_db(rctx, rstate, state);
948 rctx->ctx.num_dest_buffers++;
949 }
950
951 target_mask = 0x00000000;
952 target_mask = 0xFFFFFFFF;
953 shader_mask = 0;
954 shader_control = 0;
955 for (int i = 0; i < state->nr_cbufs; i++) {
956 target_mask ^= 0xf << (i * 4);
957 shader_mask |= 0xf << (i * 4);
958 shader_control |= 1 << i;
959 }
960 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
961 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
962
963 r600_pipe_state_add_reg(rstate,
964 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
965 0xFFFFFFFF, NULL);
966 r600_pipe_state_add_reg(rstate,
967 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
968 0xFFFFFFFF, NULL);
969 r600_pipe_state_add_reg(rstate,
970 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
971 0xFFFFFFFF, NULL);
972 r600_pipe_state_add_reg(rstate,
973 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
974 0xFFFFFFFF, NULL);
975 r600_pipe_state_add_reg(rstate,
976 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
977 0xFFFFFFFF, NULL);
978 r600_pipe_state_add_reg(rstate,
979 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
980 0xFFFFFFFF, NULL);
981 r600_pipe_state_add_reg(rstate,
982 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
983 0xFFFFFFFF, NULL);
984 r600_pipe_state_add_reg(rstate,
985 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
986 0xFFFFFFFF, NULL);
987 r600_pipe_state_add_reg(rstate,
988 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
989 0xFFFFFFFF, NULL);
990 if (rctx->family >= CHIP_RV770) {
991 r600_pipe_state_add_reg(rstate,
992 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
993 0xFFFFFFFF, NULL);
994 }
995
996 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
997 shader_control, 0xFFFFFFFF, NULL);
998 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
999 0x00000000, target_mask, NULL);
1000 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1001 shader_mask, 0xFFFFFFFF, NULL);
1002 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1003 0x00000000, 0xFFFFFFFF, NULL);
1004 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1005 0x00000000, 0xFFFFFFFF, NULL);
1006 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1007 0x00000000, 0xFFFFFFFF, NULL);
1008 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1009 0x01000000, 0xFFFFFFFF, NULL);
1010 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1011 0x00000000, 0xFFFFFFFF, NULL);
1012 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1013 0x000000FF, 0xFFFFFFFF, NULL);
1014 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1015 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1016 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1017 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1018
1019 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1020 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1021 r600_context_pipe_state_set(&rctx->ctx, rstate);
1022
1023 if (state->zsbuf) {
1024 r600_polygon_offset_update(rctx);
1025 }
1026 }
1027
1028 static void r600_texture_barrier(struct pipe_context *ctx)
1029 {
1030 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1031
1032 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1033 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1034 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1035 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1036 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1037 }
1038
1039 void r600_init_state_functions(struct r600_pipe_context *rctx)
1040 {
1041 rctx->context.create_blend_state = r600_create_blend_state;
1042 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1043 rctx->context.create_fs_state = r600_create_shader_state;
1044 rctx->context.create_rasterizer_state = r600_create_rs_state;
1045 rctx->context.create_sampler_state = r600_create_sampler_state;
1046 rctx->context.create_sampler_view = r600_create_sampler_view;
1047 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1048 rctx->context.create_vs_state = r600_create_shader_state;
1049 rctx->context.bind_blend_state = r600_bind_blend_state;
1050 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1051 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1052 rctx->context.bind_fs_state = r600_bind_ps_shader;
1053 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1054 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1055 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1056 rctx->context.bind_vs_state = r600_bind_vs_shader;
1057 rctx->context.delete_blend_state = r600_delete_state;
1058 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1059 rctx->context.delete_fs_state = r600_delete_ps_shader;
1060 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1061 rctx->context.delete_sampler_state = r600_delete_state;
1062 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1063 rctx->context.delete_vs_state = r600_delete_vs_shader;
1064 rctx->context.set_blend_color = r600_set_blend_color;
1065 rctx->context.set_clip_state = r600_set_clip_state;
1066 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1067 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1068 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1069 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1070 rctx->context.set_sample_mask = r600_set_sample_mask;
1071 rctx->context.set_scissor_state = r600_set_scissor_state;
1072 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1073 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1074 rctx->context.set_index_buffer = r600_set_index_buffer;
1075 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1076 rctx->context.set_viewport_state = r600_set_viewport_state;
1077 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1078 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1079 rctx->context.texture_barrier = r600_texture_barrier;
1080 }
1081
1082 void r600_adjust_gprs(struct r600_pipe_context *rctx)
1083 {
1084 enum radeon_family family;
1085 struct r600_pipe_state rstate;
1086 unsigned num_ps_gprs = rctx->default_ps_gprs;
1087 unsigned num_vs_gprs = rctx->default_vs_gprs;
1088 unsigned tmp;
1089 int diff;
1090
1091 family = r600_get_family(rctx->radeon);
1092
1093 if (family >= CHIP_CEDAR)
1094 return;
1095
1096 if (!rctx->ps_shader && !rctx->vs_shader)
1097 return;
1098
1099 if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1100 {
1101 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1102 num_vs_gprs -= diff;
1103 num_ps_gprs += diff;
1104 }
1105
1106 if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1107 {
1108 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1109 num_ps_gprs -= diff;
1110 num_vs_gprs += diff;
1111 }
1112
1113 tmp = 0;
1114 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1115 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1116 rstate.nregs = 0;
1117 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0x0FFFFFFF, NULL);
1118
1119 r600_context_pipe_state_set(&rctx->ctx, &rstate);
1120 }
1121
1122 void r600_init_config(struct r600_pipe_context *rctx)
1123 {
1124 int ps_prio;
1125 int vs_prio;
1126 int gs_prio;
1127 int es_prio;
1128 int num_ps_gprs;
1129 int num_vs_gprs;
1130 int num_gs_gprs;
1131 int num_es_gprs;
1132 int num_temp_gprs;
1133 int num_ps_threads;
1134 int num_vs_threads;
1135 int num_gs_threads;
1136 int num_es_threads;
1137 int num_ps_stack_entries;
1138 int num_vs_stack_entries;
1139 int num_gs_stack_entries;
1140 int num_es_stack_entries;
1141 enum radeon_family family;
1142 struct r600_pipe_state *rstate = &rctx->config;
1143 u32 tmp;
1144
1145 family = r600_get_family(rctx->radeon);
1146 ps_prio = 0;
1147 vs_prio = 1;
1148 gs_prio = 2;
1149 es_prio = 3;
1150 switch (family) {
1151 case CHIP_R600:
1152 num_ps_gprs = 192;
1153 num_vs_gprs = 56;
1154 num_temp_gprs = 4;
1155 num_gs_gprs = 0;
1156 num_es_gprs = 0;
1157 num_ps_threads = 136;
1158 num_vs_threads = 48;
1159 num_gs_threads = 4;
1160 num_es_threads = 4;
1161 num_ps_stack_entries = 128;
1162 num_vs_stack_entries = 128;
1163 num_gs_stack_entries = 0;
1164 num_es_stack_entries = 0;
1165 break;
1166 case CHIP_RV630:
1167 case CHIP_RV635:
1168 num_ps_gprs = 84;
1169 num_vs_gprs = 36;
1170 num_temp_gprs = 4;
1171 num_gs_gprs = 0;
1172 num_es_gprs = 0;
1173 num_ps_threads = 144;
1174 num_vs_threads = 40;
1175 num_gs_threads = 4;
1176 num_es_threads = 4;
1177 num_ps_stack_entries = 40;
1178 num_vs_stack_entries = 40;
1179 num_gs_stack_entries = 32;
1180 num_es_stack_entries = 16;
1181 break;
1182 case CHIP_RV610:
1183 case CHIP_RV620:
1184 case CHIP_RS780:
1185 case CHIP_RS880:
1186 default:
1187 num_ps_gprs = 84;
1188 num_vs_gprs = 36;
1189 num_temp_gprs = 4;
1190 num_gs_gprs = 0;
1191 num_es_gprs = 0;
1192 num_ps_threads = 136;
1193 num_vs_threads = 48;
1194 num_gs_threads = 4;
1195 num_es_threads = 4;
1196 num_ps_stack_entries = 40;
1197 num_vs_stack_entries = 40;
1198 num_gs_stack_entries = 32;
1199 num_es_stack_entries = 16;
1200 break;
1201 case CHIP_RV670:
1202 num_ps_gprs = 144;
1203 num_vs_gprs = 40;
1204 num_temp_gprs = 4;
1205 num_gs_gprs = 0;
1206 num_es_gprs = 0;
1207 num_ps_threads = 136;
1208 num_vs_threads = 48;
1209 num_gs_threads = 4;
1210 num_es_threads = 4;
1211 num_ps_stack_entries = 40;
1212 num_vs_stack_entries = 40;
1213 num_gs_stack_entries = 32;
1214 num_es_stack_entries = 16;
1215 break;
1216 case CHIP_RV770:
1217 num_ps_gprs = 192;
1218 num_vs_gprs = 56;
1219 num_temp_gprs = 4;
1220 num_gs_gprs = 0;
1221 num_es_gprs = 0;
1222 num_ps_threads = 188;
1223 num_vs_threads = 60;
1224 num_gs_threads = 0;
1225 num_es_threads = 0;
1226 num_ps_stack_entries = 256;
1227 num_vs_stack_entries = 256;
1228 num_gs_stack_entries = 0;
1229 num_es_stack_entries = 0;
1230 break;
1231 case CHIP_RV730:
1232 case CHIP_RV740:
1233 num_ps_gprs = 84;
1234 num_vs_gprs = 36;
1235 num_temp_gprs = 4;
1236 num_gs_gprs = 0;
1237 num_es_gprs = 0;
1238 num_ps_threads = 188;
1239 num_vs_threads = 60;
1240 num_gs_threads = 0;
1241 num_es_threads = 0;
1242 num_ps_stack_entries = 128;
1243 num_vs_stack_entries = 128;
1244 num_gs_stack_entries = 0;
1245 num_es_stack_entries = 0;
1246 break;
1247 case CHIP_RV710:
1248 num_ps_gprs = 192;
1249 num_vs_gprs = 56;
1250 num_temp_gprs = 4;
1251 num_gs_gprs = 0;
1252 num_es_gprs = 0;
1253 num_ps_threads = 144;
1254 num_vs_threads = 48;
1255 num_gs_threads = 0;
1256 num_es_threads = 0;
1257 num_ps_stack_entries = 128;
1258 num_vs_stack_entries = 128;
1259 num_gs_stack_entries = 0;
1260 num_es_stack_entries = 0;
1261 break;
1262 }
1263
1264 rctx->default_ps_gprs = num_ps_gprs;
1265 rctx->default_vs_gprs = num_vs_gprs;
1266
1267 rstate->id = R600_PIPE_STATE_CONFIG;
1268
1269 /* SQ_CONFIG */
1270 tmp = 0;
1271 switch (family) {
1272 case CHIP_RV610:
1273 case CHIP_RV620:
1274 case CHIP_RS780:
1275 case CHIP_RS880:
1276 case CHIP_RV710:
1277 break;
1278 default:
1279 tmp |= S_008C00_VC_ENABLE(1);
1280 break;
1281 }
1282 tmp |= S_008C00_DX9_CONSTS(0);
1283 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1284 tmp |= S_008C00_PS_PRIO(ps_prio);
1285 tmp |= S_008C00_VS_PRIO(vs_prio);
1286 tmp |= S_008C00_GS_PRIO(gs_prio);
1287 tmp |= S_008C00_ES_PRIO(es_prio);
1288 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1289
1290 /* SQ_GPR_RESOURCE_MGMT_1 */
1291 tmp = 0;
1292 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1293 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1294 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1295 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1296
1297 /* SQ_GPR_RESOURCE_MGMT_2 */
1298 tmp = 0;
1299 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1300 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1301 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1302
1303 /* SQ_THREAD_RESOURCE_MGMT */
1304 tmp = 0;
1305 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1306 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1307 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1308 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1309 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1310
1311 /* SQ_STACK_RESOURCE_MGMT_1 */
1312 tmp = 0;
1313 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1314 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1315 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1316
1317 /* SQ_STACK_RESOURCE_MGMT_2 */
1318 tmp = 0;
1319 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1320 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1321 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1322
1323 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1324 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1325
1326 if (family >= CHIP_RV770) {
1327 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1328 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1329 S_009508_DISABLE_CUBE_ANISO(1) |
1330 S_009508_SYNC_GRADIENT(1) |
1331 S_009508_SYNC_WALKER(1) |
1332 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL);
1333 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1334 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1335 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1336 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1337 } else {
1338 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1339 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1340 S_009508_DISABLE_CUBE_ANISO(1) |
1341 S_009508_SYNC_GRADIENT(1) |
1342 S_009508_SYNC_WALKER(1) |
1343 S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL);
1344 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1345 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1346 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1347 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1348 }
1349 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1350 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1351 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1352 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1353 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1354 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1355 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1356 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1357 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1358 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1359 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1360 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1361 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1362 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1363 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1364 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1365 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1366 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1367 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1368 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1369 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1370 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1371 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1372 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1373 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1374 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1375
1376 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1377 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1378 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1379 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1380 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1381 r600_context_pipe_state_set(&rctx->ctx, rstate);
1382 }
1383
1384 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1385 {
1386 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1387 struct r600_pipe_state *rstate = &shader->rstate;
1388 struct r600_shader *rshader = &shader->shader;
1389 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1390 int pos_index = -1, face_index = -1;
1391
1392 rstate->nregs = 0;
1393
1394 for (i = 0; i < rshader->ninput; i++) {
1395 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1396 pos_index = i;
1397 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1398 face_index = i;
1399 }
1400
1401 db_shader_control = 0;
1402 for (i = 0; i < rshader->noutput; i++) {
1403 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1404 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1405 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1406 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
1407 }
1408 if (rshader->uses_kill)
1409 db_shader_control |= S_02880C_KILL_ENABLE(1);
1410
1411 exports_ps = 0;
1412 num_cout = 0;
1413 for (i = 0; i < rshader->noutput; i++) {
1414 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1415 rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1416 exports_ps |= 1;
1417 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1418 num_cout++;
1419 }
1420 }
1421 exports_ps |= S_028854_EXPORT_COLORS(num_cout);
1422 if (!exports_ps) {
1423 /* always at least export 1 component per pixel */
1424 exports_ps = 2;
1425 }
1426
1427 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
1428 S_0286CC_PERSP_GRADIENT_ENA(1);
1429 spi_input_z = 0;
1430 if (pos_index != -1) {
1431 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
1432 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
1433 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
1434 S_0286CC_BARYC_SAMPLE_CNTL(1));
1435 spi_input_z |= 1;
1436 }
1437
1438 spi_ps_in_control_1 = 0;
1439 if (face_index != -1) {
1440 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
1441 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
1442 }
1443
1444 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
1445 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
1446 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
1447 r600_pipe_state_add_reg(rstate,
1448 R_028840_SQ_PGM_START_PS,
1449 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1450 r600_pipe_state_add_reg(rstate,
1451 R_028850_SQ_PGM_RESOURCES_PS,
1452 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1453 S_028868_STACK_SIZE(rshader->bc.nstack),
1454 0xFFFFFFFF, NULL);
1455 r600_pipe_state_add_reg(rstate,
1456 R_028854_SQ_PGM_EXPORTS_PS,
1457 exports_ps, 0xFFFFFFFF, NULL);
1458 r600_pipe_state_add_reg(rstate,
1459 R_0288CC_SQ_PGM_CF_OFFSET_PS,
1460 0x00000000, 0xFFFFFFFF, NULL);
1461 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
1462 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
1463 S_028808_MULTIWRITE_ENABLE(1),
1464 NULL);
1465 /* only set some bits here, the other bits are set in the dsa state */
1466 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
1467 db_shader_control,
1468 S_02880C_Z_EXPORT_ENABLE(1) |
1469 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
1470 S_02880C_KILL_ENABLE(1),
1471 NULL);
1472
1473 r600_pipe_state_add_reg(rstate,
1474 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
1475 0xFFFFFFFF, NULL);
1476 }
1477
1478 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1479 {
1480 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1481 struct r600_pipe_state *rstate = &shader->rstate;
1482 struct r600_shader *rshader = &shader->shader;
1483 unsigned spi_vs_out_id[10];
1484 unsigned i, tmp;
1485
1486 /* clear previous register */
1487 rstate->nregs = 0;
1488
1489 /* so far never got proper semantic id from tgsi */
1490 /* FIXME better to move this in config things so they get emited
1491 * only one time per cs
1492 */
1493 for (i = 0; i < 10; i++) {
1494 spi_vs_out_id[i] = 0;
1495 }
1496 for (i = 0; i < 32; i++) {
1497 tmp = i << ((i & 3) * 8);
1498 spi_vs_out_id[i / 4] |= tmp;
1499 }
1500 for (i = 0; i < 10; i++) {
1501 r600_pipe_state_add_reg(rstate,
1502 R_028614_SPI_VS_OUT_ID_0 + i * 4,
1503 spi_vs_out_id[i], 0xFFFFFFFF, NULL);
1504 }
1505
1506 r600_pipe_state_add_reg(rstate,
1507 R_0286C4_SPI_VS_OUT_CONFIG,
1508 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
1509 0xFFFFFFFF, NULL);
1510 r600_pipe_state_add_reg(rstate,
1511 R_028868_SQ_PGM_RESOURCES_VS,
1512 S_028868_NUM_GPRS(rshader->bc.ngpr) |
1513 S_028868_STACK_SIZE(rshader->bc.nstack),
1514 0xFFFFFFFF, NULL);
1515 r600_pipe_state_add_reg(rstate,
1516 R_0288D0_SQ_PGM_CF_OFFSET_VS,
1517 0x00000000, 0xFFFFFFFF, NULL);
1518 r600_pipe_state_add_reg(rstate,
1519 R_028858_SQ_PGM_START_VS,
1520 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
1521
1522 r600_pipe_state_add_reg(rstate,
1523 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
1524 0xFFFFFFFF, NULL);
1525 }
1526
1527 void r600_fetch_shader(struct pipe_context *ctx,
1528 struct r600_vertex_element *ve)
1529 {
1530 struct r600_pipe_state *rstate;
1531 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1532
1533 rstate = &ve->rstate;
1534 rstate->id = R600_PIPE_STATE_FETCH_SHADER;
1535 rstate->nregs = 0;
1536 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
1537 0x00000000, 0xFFFFFFFF, NULL);
1538 r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
1539 0x00000000, 0xFFFFFFFF, NULL);
1540 r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
1541 r600_bo_offset(ve->fetch_shader) >> 8,
1542 0xFFFFFFFF, ve->fetch_shader);
1543 }
1544
1545 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1546 {
1547 struct pipe_depth_stencil_alpha_state dsa;
1548 struct r600_pipe_state *rstate;
1549 boolean quirk = false;
1550
1551 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1552 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1553 quirk = true;
1554
1555 memset(&dsa, 0, sizeof(dsa));
1556
1557 if (quirk) {
1558 dsa.depth.enabled = 1;
1559 dsa.depth.func = PIPE_FUNC_LEQUAL;
1560 dsa.stencil[0].enabled = 1;
1561 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1562 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1563 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1564 dsa.stencil[0].writemask = 0xff;
1565 }
1566
1567 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1568 r600_pipe_state_add_reg(rstate,
1569 R_02880C_DB_SHADER_CONTROL,
1570 0x0,
1571 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1572 r600_pipe_state_add_reg(rstate,
1573 R_028D0C_DB_RENDER_CONTROL,
1574 S_028D0C_DEPTH_COPY_ENABLE(1) |
1575 S_028D0C_STENCIL_COPY_ENABLE(1) |
1576 S_028D0C_COPY_CENTROID(1),
1577 S_028D0C_DEPTH_COPY_ENABLE(1) |
1578 S_028D0C_STENCIL_COPY_ENABLE(1) |
1579 S_028D0C_COPY_CENTROID(1), NULL);
1580 return rstate;
1581 }
1582
1583 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
1584 struct r600_pipe_resource_state *rstate)
1585 {
1586 rstate->id = R600_PIPE_STATE_RESOURCE;
1587
1588 rstate->bo[0] = NULL;
1589 rstate->val[0] = 0;
1590 rstate->val[1] = 0;
1591 rstate->val[2] = 0;
1592 rstate->val[3] = 0;
1593 rstate->val[4] = 0;
1594 rstate->val[5] = 0;
1595 rstate->val[6] = 0xc0000000;
1596 }
1597
1598 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
1599 struct r600_resource *rbuffer,
1600 unsigned offset, unsigned stride)
1601 {
1602 rstate->val[0] = offset;
1603 rstate->bo[0] = rbuffer->bo;
1604 rstate->val[1] = rbuffer->bo_size - offset - 1;
1605 rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1606 S_038008_STRIDE(stride);
1607 }