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r600g: bugfixing register remapping
[mesa.git] / src / gallium / drivers / r600 / r600_state.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 /* TODO:
25 * - fix mask for depth control & cull for query
26 */
27 #include <stdio.h>
28 #include <errno.h>
29 #include <pipe/p_defines.h>
30 #include <pipe/p_state.h>
31 #include <pipe/p_context.h>
32 #include <tgsi/tgsi_scan.h>
33 #include <tgsi/tgsi_parse.h>
34 #include <tgsi/tgsi_util.h>
35 #include <util/u_double_list.h>
36 #include <util/u_pack_color.h>
37 #include <util/u_memory.h>
38 #include <util/u_inlines.h>
39 #include <util/u_framebuffer.h>
40 #include <pipebuffer/pb_buffer.h>
41 #include "r600.h"
42 #include "r600d.h"
43 #include "r600_resource.h"
44 #include "r600_shader.h"
45 #include "r600_pipe.h"
46 #include "r600_state_inlines.h"
47
48 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
49 {
50 struct r600_pipe_state state;
51
52 state.id = R600_PIPE_STATE_POLYGON_OFFSET;
53 state.nregs = 0;
54 if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
55 float offset_units = rctx->rasterizer->offset_units;
56 unsigned offset_db_fmt_cntl = 0, depth;
57
58 switch (rctx->framebuffer.zsbuf->texture->format) {
59 case PIPE_FORMAT_Z24X8_UNORM:
60 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
61 depth = -24;
62 offset_units *= 2.0f;
63 break;
64 case PIPE_FORMAT_Z32_FLOAT:
65 depth = -23;
66 offset_units *= 1.0f;
67 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
68 break;
69 case PIPE_FORMAT_Z16_UNORM:
70 depth = -16;
71 offset_units *= 4.0f;
72 break;
73 default:
74 return;
75 }
76 /* FIXME some of those reg can be computed with cso */
77 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
78 r600_pipe_state_add_reg(&state,
79 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
80 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
81 r600_pipe_state_add_reg(&state,
82 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
83 fui(offset_units), 0xFFFFFFFF, NULL);
84 r600_pipe_state_add_reg(&state,
85 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
86 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
87 r600_pipe_state_add_reg(&state,
88 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
89 fui(offset_units), 0xFFFFFFFF, NULL);
90 r600_pipe_state_add_reg(&state,
91 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
92 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
93 r600_context_pipe_state_set(&rctx->ctx, &state);
94 }
95 }
96
97 /* FIXME optimize away spi update when it's not needed */
98 static void r600_spi_update(struct r600_pipe_context *rctx)
99 {
100 struct r600_pipe_shader *shader = rctx->ps_shader;
101 struct r600_pipe_state rstate;
102 struct r600_shader *rshader = &shader->shader;
103 unsigned i, tmp;
104
105 rstate.nregs = 0;
106 for (i = 0; i < rshader->ninput; i++) {
107 tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
108 if (rshader->input[i].centroid)
109 tmp |= S_028644_SEL_CENTROID(1);
110 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
111 tmp |= S_028644_SEL_LINEAR(1);
112
113 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
114 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
115 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
116 tmp |= S_028644_FLAT_SHADE(rctx->flatshade);
117 }
118 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
119 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
120 tmp |= S_028644_PT_SPRITE_TEX(1);
121 }
122 r600_pipe_state_add_reg(&rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
123 }
124 r600_context_pipe_state_set(&rctx->ctx, &rstate);
125 }
126
127 void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
128 {
129 struct r600_pipe_state *rstate;
130 struct r600_resource *rbuffer;
131 struct pipe_vertex_buffer *vertex_buffer;
132 unsigned i, offset;
133
134 /* we don't update until we know vertex elements */
135 if (rctx->vertex_elements == NULL || !rctx->nvertex_buffer)
136 return;
137
138 if (rctx->vertex_elements->incompatible_layout) {
139 /* translate rebind new vertex elements so
140 * return once translated
141 */
142 r600_begin_vertex_translate(rctx);
143 return;
144 }
145
146 if (rctx->any_user_vbs) {
147 r600_upload_user_buffers(rctx);
148 rctx->any_user_vbs = FALSE;
149 }
150
151 if (rctx->vertex_elements->vbuffer_need_offset) {
152 /* one resource per vertex elements */
153 rctx->nvs_resource = rctx->vertex_elements->count;
154 } else {
155 /* bind vertex buffer once */
156 rctx->nvs_resource = rctx->nvertex_buffer;
157 }
158
159 for (i = 0 ; i < rctx->nvs_resource; i++) {
160 rstate = &rctx->vs_resource[i];
161 rstate->id = R600_PIPE_STATE_RESOURCE;
162 rstate->nregs = 0;
163
164 if (rctx->vertex_elements->vbuffer_need_offset) {
165 /* one resource per vertex elements */
166 unsigned vbuffer_index;
167 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
168 vertex_buffer = &rctx->vertex_buffer[vbuffer_index];
169 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
170 offset = rctx->vertex_elements->vbuffer_offset[i];
171 } else {
172 /* bind vertex buffer once */
173 vertex_buffer = &rctx->vertex_buffer[i];
174 rbuffer = (struct r600_resource*)vertex_buffer->buffer;
175 offset = 0;
176 }
177 if (vertex_buffer == NULL || rbuffer == NULL)
178 continue;
179 offset += vertex_buffer->buffer_offset + r600_bo_offset(rbuffer->bo);
180
181 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
182 offset, 0xFFFFFFFF, rbuffer->bo);
183 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
184 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL);
185 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
186 S_038008_STRIDE(vertex_buffer->stride),
187 0xFFFFFFFF, NULL);
188 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
189 0x00000000, 0xFFFFFFFF, NULL);
190 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
191 0x00000000, 0xFFFFFFFF, NULL);
192 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
193 0x00000000, 0xFFFFFFFF, NULL);
194 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
195 0xC0000000, 0xFFFFFFFF, NULL);
196 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
197 }
198 }
199
200 static void r600_draw_common(struct r600_drawl *draw)
201 {
202 struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
203 struct r600_resource *rbuffer;
204 unsigned prim;
205 u32 vgt_dma_index_type, vgt_draw_initiator, mask;
206 struct r600_draw rdraw;
207 struct r600_pipe_state vgt;
208
209 switch (draw->index_size) {
210 case 2:
211 vgt_draw_initiator = 0;
212 vgt_dma_index_type = 0;
213 break;
214 case 4:
215 vgt_draw_initiator = 0;
216 vgt_dma_index_type = 1;
217 break;
218 case 0:
219 vgt_draw_initiator = 2;
220 vgt_dma_index_type = 0;
221 break;
222 default:
223 R600_ERR("unsupported index size %d\n", draw->index_size);
224 return;
225 }
226 if (r600_conv_pipe_prim(draw->mode, &prim))
227 return;
228 if (unlikely(rctx->ps_shader == NULL)) {
229 R600_ERR("missing vertex shader\n");
230 return;
231 }
232 if (unlikely(rctx->vs_shader == NULL)) {
233 R600_ERR("missing vertex shader\n");
234 return;
235 }
236 /* there should be enough input */
237 if (rctx->vertex_elements->count < rctx->vs_shader->shader.bc.nresource) {
238 R600_ERR("%d resources provided, expecting %d\n",
239 rctx->vertex_elements->count, rctx->vs_shader->shader.bc.nresource);
240 return;
241 }
242
243 r600_spi_update(rctx);
244
245 mask = 0;
246 for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
247 mask |= (0xF << (i * 4));
248 }
249
250 vgt.id = R600_PIPE_STATE_VGT;
251 vgt.nregs = 0;
252 r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
253 r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
254 r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
255 r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
256 r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
257 r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
258 r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
259 r600_context_pipe_state_set(&rctx->ctx, &vgt);
260
261 rdraw.vgt_num_indices = draw->count;
262 rdraw.vgt_num_instances = 1;
263 rdraw.vgt_index_type = vgt_dma_index_type;
264 rdraw.vgt_draw_initiator = vgt_draw_initiator;
265 rdraw.indices = NULL;
266 if (draw->index_buffer) {
267 rbuffer = (struct r600_resource*)draw->index_buffer;
268 rdraw.indices = rbuffer->bo;
269 rdraw.indices_bo_offset = draw->index_buffer_offset;
270 }
271 r600_context_draw(&rctx->ctx, &rdraw);
272 }
273
274 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
275 {
276 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
277 struct r600_drawl draw;
278
279 memset(&draw, 0, sizeof(struct r600_drawl));
280 draw.ctx = ctx;
281 draw.mode = info->mode;
282 draw.start = info->start;
283 draw.count = info->count;
284 if (info->indexed && rctx->index_buffer.buffer) {
285 draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
286 draw.min_index = info->min_index;
287 draw.max_index = info->max_index;
288 draw.index_bias = info->index_bias;
289
290 r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
291 &rctx->index_buffer.index_size,
292 &draw.start,
293 info->count);
294
295 draw.index_size = rctx->index_buffer.index_size;
296 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
297 draw.index_buffer_offset = draw.start * draw.index_size;
298 draw.start = 0;
299 r600_upload_index_buffer(rctx, &draw);
300 } else {
301 draw.index_size = 0;
302 draw.index_buffer = NULL;
303 draw.min_index = info->min_index;
304 draw.max_index = info->max_index;
305 draw.index_bias = info->start;
306 }
307 r600_draw_common(&draw);
308
309 pipe_resource_reference(&draw.index_buffer, NULL);
310 }
311
312 static void r600_set_blend_color(struct pipe_context *ctx,
313 const struct pipe_blend_color *state)
314 {
315 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
316 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
317
318 if (rstate == NULL)
319 return;
320
321 rstate->id = R600_PIPE_STATE_BLEND_COLOR;
322 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
323 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
324 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
325 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
326 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
327 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
328 r600_context_pipe_state_set(&rctx->ctx, rstate);
329 }
330
331 static void *r600_create_blend_state(struct pipe_context *ctx,
332 const struct pipe_blend_state *state)
333 {
334 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
335 struct r600_pipe_state *rstate;
336 u32 color_control, target_mask;
337
338 if (blend == NULL) {
339 return NULL;
340 }
341 rstate = &blend->rstate;
342
343 rstate->id = R600_PIPE_STATE_BLEND;
344
345 target_mask = 0;
346 color_control = S_028808_PER_MRT_BLEND(1);
347 if (state->logicop_enable) {
348 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
349 } else {
350 color_control |= (0xcc << 16);
351 }
352 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
353 if (state->independent_blend_enable) {
354 for (int i = 0; i < 8; i++) {
355 if (state->rt[i].blend_enable) {
356 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
357 }
358 target_mask |= (state->rt[i].colormask << (4 * i));
359 }
360 } else {
361 for (int i = 0; i < 8; i++) {
362 if (state->rt[0].blend_enable) {
363 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
364 }
365 target_mask |= (state->rt[0].colormask << (4 * i));
366 }
367 }
368 blend->cb_target_mask = target_mask;
369 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
370 color_control, 0xFFFFFFFF, NULL);
371
372 for (int i = 0; i < 8; i++) {
373 unsigned eqRGB = state->rt[i].rgb_func;
374 unsigned srcRGB = state->rt[i].rgb_src_factor;
375 unsigned dstRGB = state->rt[i].rgb_dst_factor;
376
377 unsigned eqA = state->rt[i].alpha_func;
378 unsigned srcA = state->rt[i].alpha_src_factor;
379 unsigned dstA = state->rt[i].alpha_dst_factor;
380 uint32_t bc = 0;
381
382 if (!state->rt[i].blend_enable)
383 continue;
384
385 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
386 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
387 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
388
389 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
390 bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
391 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
392 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
393 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
394 }
395
396 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
397 if (i == 0) {
398 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
399 }
400 }
401 return rstate;
402 }
403
404 static void *r600_create_dsa_state(struct pipe_context *ctx,
405 const struct pipe_depth_stencil_alpha_state *state)
406 {
407 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
408 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
409 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
410
411 if (rstate == NULL) {
412 return NULL;
413 }
414
415 rstate->id = R600_PIPE_STATE_DSA;
416 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
417 /* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
418 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
419 * be set if shader use texkill instruction
420 */
421 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
422 stencil_ref_mask = 0;
423 stencil_ref_mask_bf = 0;
424 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
425 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
426 S_028800_ZFUNC(state->depth.func);
427
428 /* stencil */
429 if (state->stencil[0].enabled) {
430 db_depth_control |= S_028800_STENCIL_ENABLE(1);
431 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
432 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
433 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
434 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
435
436
437 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
438 S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
439 if (state->stencil[1].enabled) {
440 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
441 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
442 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
443 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
444 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
445 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
446 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
447 }
448 }
449
450 /* alpha */
451 alpha_test_control = 0;
452 alpha_ref = 0;
453 if (state->alpha.enabled) {
454 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
455 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
456 alpha_ref = fui(state->alpha.ref_value);
457 }
458
459 /* misc */
460 db_render_control = 0;
461 db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
462 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
463 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
464 /* TODO db_render_override depends on query */
465 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
466 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
467 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
468 r600_pipe_state_add_reg(rstate,
469 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
470 0xFFFFFFFF & C_028430_STENCILREF, NULL);
471 r600_pipe_state_add_reg(rstate,
472 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
473 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
474 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
475 r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
476 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
477 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
478 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
479 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
480 r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
481 r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
482 r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
483 r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
484 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
485
486 return rstate;
487 }
488
489 static void *r600_create_rs_state(struct pipe_context *ctx,
490 const struct pipe_rasterizer_state *state)
491 {
492 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
493 struct r600_pipe_state *rstate;
494 unsigned tmp;
495 unsigned prov_vtx = 1, polygon_dual_mode;
496 unsigned clip_rule;
497
498 if (rs == NULL) {
499 return NULL;
500 }
501
502 rstate = &rs->rstate;
503 rs->flatshade = state->flatshade;
504 rs->sprite_coord_enable = state->sprite_coord_enable;
505
506 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
507 /* offset */
508 rs->offset_units = state->offset_units;
509 rs->offset_scale = state->offset_scale * 12.0f;
510
511 rstate->id = R600_PIPE_STATE_RASTERIZER;
512 if (state->flatshade_first)
513 prov_vtx = 0;
514 tmp = S_0286D4_FLAT_SHADE_ENA(1);
515 if (state->sprite_coord_enable) {
516 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
517 S_0286D4_PNT_SPRITE_OVRD_X(2) |
518 S_0286D4_PNT_SPRITE_OVRD_Y(3) |
519 S_0286D4_PNT_SPRITE_OVRD_Z(0) |
520 S_0286D4_PNT_SPRITE_OVRD_W(1);
521 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
522 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
523 }
524 }
525 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
526
527 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
528 state->fill_back != PIPE_POLYGON_MODE_FILL);
529 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
530 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
531 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
532 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
533 S_028814_FACE(!state->front_ccw) |
534 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
535 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
536 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
537 S_028814_POLY_MODE(polygon_dual_mode) |
538 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
539 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
540 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
541 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
542 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
543 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
544 /* point size 12.4 fixed point */
545 tmp = (unsigned)(state->point_size * 8.0);
546 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
547 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
548
549 tmp = (unsigned)state->line_width * 8;
550 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
551
552 r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
553 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
554 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
555
556 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
557 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
558 0xFFFFFFFF, NULL);
559
560 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
561 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
562 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
563 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
564 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
565 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
566
567 return rstate;
568 }
569
570 static void *r600_create_sampler_state(struct pipe_context *ctx,
571 const struct pipe_sampler_state *state)
572 {
573 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
574 union util_color uc;
575
576 if (rstate == NULL) {
577 return NULL;
578 }
579
580 rstate->id = R600_PIPE_STATE_SAMPLER;
581 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
582 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
583 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
584 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
585 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
586 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
587 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
588 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
589 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
590 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
591 /* FIXME LOD it depends on texture base level ... */
592 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
593 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
594 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
595 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
596 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
597 if (uc.ui) {
598 r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
599 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
600 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
601 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
602 }
603 return rstate;
604 }
605
606 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
607 struct pipe_resource *texture,
608 const struct pipe_sampler_view *state)
609 {
610 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
611 struct r600_pipe_state *rstate;
612 const struct util_format_description *desc;
613 struct r600_resource_texture *tmp;
614 struct r600_resource *rbuffer;
615 unsigned format;
616 uint32_t word4 = 0, yuv_format = 0, pitch = 0;
617 unsigned char swizzle[4], array_mode = 0, tile_type = 0;
618 struct r600_bo *bo[2];
619
620 if (resource == NULL)
621 return NULL;
622 rstate = &resource->state;
623
624 /* initialize base object */
625 resource->base = *state;
626 resource->base.texture = NULL;
627 pipe_reference(NULL, &texture->reference);
628 resource->base.texture = texture;
629 resource->base.reference.count = 1;
630 resource->base.context = ctx;
631
632 swizzle[0] = state->swizzle_r;
633 swizzle[1] = state->swizzle_g;
634 swizzle[2] = state->swizzle_b;
635 swizzle[3] = state->swizzle_a;
636 format = r600_translate_texformat(state->format,
637 swizzle,
638 &word4, &yuv_format);
639 if (format == ~0) {
640 format = 0;
641 }
642 desc = util_format_description(state->format);
643 if (desc == NULL) {
644 R600_ERR("unknow format %d\n", state->format);
645 }
646 tmp = (struct r600_resource_texture*)texture;
647 rbuffer = &tmp->resource;
648 bo[0] = rbuffer->bo;
649 bo[1] = rbuffer->bo;
650 /* FIXME depth texture decompression */
651 if (tmp->depth) {
652 r600_texture_depth_flush(ctx, texture);
653 tmp = (struct r600_resource_texture*)texture;
654 rbuffer = &tmp->flushed_depth_texture->resource;
655 bo[0] = rbuffer->bo;
656 bo[1] = rbuffer->bo;
657 }
658 pitch = align(tmp->pitch_in_pixels[0], 8);
659 if (tmp->tiled) {
660 array_mode = tmp->array_mode[0];
661 tile_type = tmp->tile_type;
662 }
663
664 /* FIXME properly handle first level != 0 */
665 r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
666 S_038000_DIM(r600_tex_dim(texture->target)) |
667 S_038000_TILE_MODE(array_mode) |
668 S_038000_TILE_TYPE(tile_type) |
669 S_038000_PITCH((pitch / 8) - 1) |
670 S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
671 r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
672 S_038004_TEX_HEIGHT(texture->height0 - 1) |
673 S_038004_TEX_DEPTH(texture->depth0 - 1) |
674 S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
675 r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
676 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
677 r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
678 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
679 r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
680 word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
681 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_NO_ZERO) |
682 S_038010_REQUEST_SIZE(1) |
683 S_038010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL);
684 r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
685 S_038014_LAST_LEVEL(state->u.tex.last_level) |
686 S_038014_BASE_ARRAY(0) |
687 S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
688 r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
689 S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
690
691 return &resource->base;
692 }
693
694 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
695 struct pipe_sampler_view **views)
696 {
697 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
698 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
699
700 for (int i = 0; i < count; i++) {
701 if (resource[i]) {
702 r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i);
703 }
704 }
705 }
706
707 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
708 struct pipe_sampler_view **views)
709 {
710 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
711 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
712 int i;
713
714 for (i = 0; i < count; i++) {
715 if (&rctx->ps_samplers.views[i]->base != views[i]) {
716 if (resource[i])
717 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
718 else
719 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
720
721 pipe_sampler_view_reference(
722 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
723 views[i]);
724
725 }
726 }
727 for (i = count; i < NUM_TEX_UNITS; i++) {
728 if (rctx->ps_samplers.views[i]) {
729 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, i);
730 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
731 }
732 }
733 rctx->ps_samplers.n_views = count;
734 }
735
736 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
737 {
738 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
739 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
740
741 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
742 rctx->ps_samplers.n_samplers = count;
743
744 for (int i = 0; i < count; i++) {
745 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
746 }
747 }
748
749 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
750 {
751 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
752 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
753
754 for (int i = 0; i < count; i++) {
755 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
756 }
757 }
758
759 static void r600_set_clip_state(struct pipe_context *ctx,
760 const struct pipe_clip_state *state)
761 {
762 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
763 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
764
765 if (rstate == NULL)
766 return;
767
768 rctx->clip = *state;
769 rstate->id = R600_PIPE_STATE_CLIP;
770 for (int i = 0; i < state->nr; i++) {
771 r600_pipe_state_add_reg(rstate,
772 R_028E20_PA_CL_UCP0_X + i * 16,
773 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
774 r600_pipe_state_add_reg(rstate,
775 R_028E24_PA_CL_UCP0_Y + i * 16,
776 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
777 r600_pipe_state_add_reg(rstate,
778 R_028E28_PA_CL_UCP0_Z + i * 16,
779 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
780 r600_pipe_state_add_reg(rstate,
781 R_028E2C_PA_CL_UCP0_W + i * 16,
782 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
783 }
784 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
785 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
786 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
787 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
788
789 free(rctx->states[R600_PIPE_STATE_CLIP]);
790 rctx->states[R600_PIPE_STATE_CLIP] = rstate;
791 r600_context_pipe_state_set(&rctx->ctx, rstate);
792 }
793
794 static void r600_set_polygon_stipple(struct pipe_context *ctx,
795 const struct pipe_poly_stipple *state)
796 {
797 }
798
799 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
800 {
801 }
802
803 static void r600_set_scissor_state(struct pipe_context *ctx,
804 const struct pipe_scissor_state *state)
805 {
806 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
807 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
808 u32 tl, br;
809
810 if (rstate == NULL)
811 return;
812
813 rstate->id = R600_PIPE_STATE_SCISSOR;
814 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
815 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
816 r600_pipe_state_add_reg(rstate,
817 R_028210_PA_SC_CLIPRECT_0_TL, tl,
818 0xFFFFFFFF, NULL);
819 r600_pipe_state_add_reg(rstate,
820 R_028214_PA_SC_CLIPRECT_0_BR, br,
821 0xFFFFFFFF, NULL);
822 r600_pipe_state_add_reg(rstate,
823 R_028218_PA_SC_CLIPRECT_1_TL, tl,
824 0xFFFFFFFF, NULL);
825 r600_pipe_state_add_reg(rstate,
826 R_02821C_PA_SC_CLIPRECT_1_BR, br,
827 0xFFFFFFFF, NULL);
828 r600_pipe_state_add_reg(rstate,
829 R_028220_PA_SC_CLIPRECT_2_TL, tl,
830 0xFFFFFFFF, NULL);
831 r600_pipe_state_add_reg(rstate,
832 R_028224_PA_SC_CLIPRECT_2_BR, br,
833 0xFFFFFFFF, NULL);
834 r600_pipe_state_add_reg(rstate,
835 R_028228_PA_SC_CLIPRECT_3_TL, tl,
836 0xFFFFFFFF, NULL);
837 r600_pipe_state_add_reg(rstate,
838 R_02822C_PA_SC_CLIPRECT_3_BR, br,
839 0xFFFFFFFF, NULL);
840
841 free(rctx->states[R600_PIPE_STATE_SCISSOR]);
842 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
843 r600_context_pipe_state_set(&rctx->ctx, rstate);
844 }
845
846 static void r600_set_stencil_ref(struct pipe_context *ctx,
847 const struct pipe_stencil_ref *state)
848 {
849 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
850 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
851 u32 tmp;
852
853 if (rstate == NULL)
854 return;
855
856 rctx->stencil_ref = *state;
857 rstate->id = R600_PIPE_STATE_STENCIL_REF;
858 tmp = S_028430_STENCILREF(state->ref_value[0]);
859 r600_pipe_state_add_reg(rstate,
860 R_028430_DB_STENCILREFMASK, tmp,
861 ~C_028430_STENCILREF, NULL);
862 tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
863 r600_pipe_state_add_reg(rstate,
864 R_028434_DB_STENCILREFMASK_BF, tmp,
865 ~C_028434_STENCILREF_BF, NULL);
866
867 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
868 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
869 r600_context_pipe_state_set(&rctx->ctx, rstate);
870 }
871
872 static void r600_set_viewport_state(struct pipe_context *ctx,
873 const struct pipe_viewport_state *state)
874 {
875 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
876 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
877
878 if (rstate == NULL)
879 return;
880
881 rctx->viewport = *state;
882 rstate->id = R600_PIPE_STATE_VIEWPORT;
883 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
884 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
885 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
886 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
887 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
888 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
889 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
890 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
891 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
892
893 free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
894 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
895 r600_context_pipe_state_set(&rctx->ctx, rstate);
896 }
897
898 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
899 const struct pipe_framebuffer_state *state, int cb)
900 {
901 struct r600_resource_texture *rtex;
902 struct r600_resource *rbuffer;
903 struct r600_surface *surf;
904 unsigned level = state->cbufs[cb]->u.tex.level;
905 unsigned pitch, slice;
906 unsigned color_info;
907 unsigned format, swap, ntype;
908 unsigned offset;
909 const struct util_format_description *desc;
910 struct r600_bo *bo[3];
911
912 surf = (struct r600_surface *)state->cbufs[cb];
913 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
914 rbuffer = &rtex->resource;
915 bo[0] = rbuffer->bo;
916 bo[1] = rbuffer->bo;
917 bo[2] = rbuffer->bo;
918
919 /* XXX quite sure for dx10+ hw don't need any offset hacks */
920 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture,
921 level, state->cbufs[cb]->u.tex.first_layer);
922 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
923 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
924 ntype = 0;
925 desc = util_format_description(rtex->resource.base.b.format);
926 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
927 ntype = V_0280A0_NUMBER_SRGB;
928 else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
929 switch(desc->channel[0].type) {
930 case UTIL_FORMAT_TYPE_UNSIGNED:
931 ntype = V_0280A0_NUMBER_UNORM;
932 break;
933
934 case UTIL_FORMAT_TYPE_SIGNED:
935 ntype = V_0280A0_NUMBER_SNORM;
936 break;
937 }
938 }
939
940 format = r600_translate_colorformat(rtex->resource.base.b.format);
941 swap = r600_translate_colorswap(rtex->resource.base.b.format);
942 color_info = S_0280A0_FORMAT(format) |
943 S_0280A0_COMP_SWAP(swap) |
944 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
945 S_0280A0_BLEND_CLAMP(1) |
946 S_0280A0_NUMBER_TYPE(ntype);
947 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
948 color_info |= S_0280A0_SOURCE_FORMAT(1);
949
950 r600_pipe_state_add_reg(rstate,
951 R_028040_CB_COLOR0_BASE + cb * 4,
952 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
953 r600_pipe_state_add_reg(rstate,
954 R_0280A0_CB_COLOR0_INFO + cb * 4,
955 color_info, 0xFFFFFFFF, bo[0]);
956 r600_pipe_state_add_reg(rstate,
957 R_028060_CB_COLOR0_SIZE + cb * 4,
958 S_028060_PITCH_TILE_MAX(pitch) |
959 S_028060_SLICE_TILE_MAX(slice),
960 0xFFFFFFFF, NULL);
961 r600_pipe_state_add_reg(rstate,
962 R_028080_CB_COLOR0_VIEW + cb * 4,
963 0x00000000, 0xFFFFFFFF, NULL);
964 r600_pipe_state_add_reg(rstate,
965 R_0280E0_CB_COLOR0_FRAG + cb * 4,
966 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
967 r600_pipe_state_add_reg(rstate,
968 R_0280C0_CB_COLOR0_TILE + cb * 4,
969 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
970 r600_pipe_state_add_reg(rstate,
971 R_028100_CB_COLOR0_MASK + cb * 4,
972 0x00000000, 0xFFFFFFFF, NULL);
973 }
974
975 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
976 const struct pipe_framebuffer_state *state)
977 {
978 struct r600_resource_texture *rtex;
979 struct r600_resource *rbuffer;
980 struct r600_surface *surf;
981 unsigned level;
982 unsigned pitch, slice, format;
983 unsigned offset;
984
985 if (state->zsbuf == NULL)
986 return;
987
988 level = state->zsbuf->u.tex.level;
989
990 surf = (struct r600_surface *)state->zsbuf;
991 rtex = (struct r600_resource_texture*)state->zsbuf->texture;
992 rtex->tiled = 1;
993 rtex->array_mode[level] = 2;
994 rtex->tile_type = 1;
995 rtex->depth = 1;
996 rbuffer = &rtex->resource;
997
998 /* XXX quite sure for dx10+ hw don't need any offset hacks */
999 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1000 level, state->zsbuf->u.tex.first_layer);
1001 pitch = rtex->pitch_in_pixels[level] / 8 - 1;
1002 slice = rtex->pitch_in_pixels[level] * surf->aligned_height / 64 - 1;
1003 format = r600_translate_dbformat(state->zsbuf->texture->format);
1004
1005 r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1006 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1007 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1008 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1009 0xFFFFFFFF, NULL);
1010 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1011 r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1012 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1013 0xFFFFFFFF, rbuffer->bo);
1014 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1015 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
1016 }
1017
1018 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1019 const struct pipe_framebuffer_state *state)
1020 {
1021 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1022 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1023 u32 shader_mask, tl, br, shader_control, target_mask;
1024
1025 if (rstate == NULL)
1026 return;
1027
1028 /* unreference old buffer and reference new one */
1029 rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1030
1031 util_copy_framebuffer_state(&rctx->framebuffer, state);
1032
1033 /* build states */
1034 for (int i = 0; i < state->nr_cbufs; i++) {
1035 r600_cb(rctx, rstate, state, i);
1036 }
1037 if (state->zsbuf) {
1038 r600_db(rctx, rstate, state);
1039 }
1040
1041 target_mask = 0x00000000;
1042 target_mask = 0xFFFFFFFF;
1043 shader_mask = 0;
1044 shader_control = 0;
1045 for (int i = 0; i < state->nr_cbufs; i++) {
1046 target_mask ^= 0xf << (i * 4);
1047 shader_mask |= 0xf << (i * 4);
1048 shader_control |= 1 << i;
1049 }
1050 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1051 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1052
1053 r600_pipe_state_add_reg(rstate,
1054 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1055 0xFFFFFFFF, NULL);
1056 r600_pipe_state_add_reg(rstate,
1057 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1058 0xFFFFFFFF, NULL);
1059 r600_pipe_state_add_reg(rstate,
1060 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1061 0xFFFFFFFF, NULL);
1062 r600_pipe_state_add_reg(rstate,
1063 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1064 0xFFFFFFFF, NULL);
1065 r600_pipe_state_add_reg(rstate,
1066 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1067 0xFFFFFFFF, NULL);
1068 r600_pipe_state_add_reg(rstate,
1069 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1070 0xFFFFFFFF, NULL);
1071 r600_pipe_state_add_reg(rstate,
1072 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1073 0xFFFFFFFF, NULL);
1074 r600_pipe_state_add_reg(rstate,
1075 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1076 0xFFFFFFFF, NULL);
1077 r600_pipe_state_add_reg(rstate,
1078 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1079 0xFFFFFFFF, NULL);
1080 if (rctx->family >= CHIP_RV770) {
1081 r600_pipe_state_add_reg(rstate,
1082 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1083 0xFFFFFFFF, NULL);
1084 }
1085
1086 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1087 shader_control, 0xFFFFFFFF, NULL);
1088 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1089 0x00000000, target_mask, NULL);
1090 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1091 shader_mask, 0xFFFFFFFF, NULL);
1092 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1093 0x00000000, 0xFFFFFFFF, NULL);
1094 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1095 0x00000000, 0xFFFFFFFF, NULL);
1096 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1097 0x00000000, 0xFFFFFFFF, NULL);
1098 r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1099 0x01000000, 0xFFFFFFFF, NULL);
1100 r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1101 0x00000000, 0xFFFFFFFF, NULL);
1102 r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1103 0x000000FF, 0xFFFFFFFF, NULL);
1104 r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1105 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1106 r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1107 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1108
1109 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1110 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1111 r600_context_pipe_state_set(&rctx->ctx, rstate);
1112
1113 if (state->zsbuf) {
1114 r600_polygon_offset_update(rctx);
1115 }
1116 }
1117
1118 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
1119 struct pipe_resource *buffer)
1120 {
1121 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1122 struct r600_resource *rbuffer = (struct r600_resource*)buffer;
1123 uint32_t offset;
1124
1125 /* Note that the state tracker can unbind constant buffers by
1126 * passing NULL here.
1127 */
1128 if (buffer == NULL) {
1129 return;
1130 }
1131
1132 r600_upload_const_buffer(rctx, buffer, &offset);
1133
1134 switch (shader) {
1135 case PIPE_SHADER_VERTEX:
1136 rctx->vs_const_buffer.nregs = 0;
1137 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1138 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1139 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1140 0xFFFFFFFF, NULL);
1141 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
1142 R_028980_ALU_CONST_CACHE_VS_0,
1143 (r600_bo_offset(rbuffer->bo) + offset) >> 8, 0xFFFFFFFF, rbuffer->bo);
1144 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
1145 break;
1146 case PIPE_SHADER_FRAGMENT:
1147 rctx->ps_const_buffer.nregs = 0;
1148 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1149 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1150 ALIGN_DIVUP(buffer->width0 >> 4, 16),
1151 0xFFFFFFFF, NULL);
1152 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
1153 R_028940_ALU_CONST_CACHE_PS_0,
1154 (r600_bo_offset(rbuffer->bo) + offset) >> 8, 0xFFFFFFFF, rbuffer->bo);
1155 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
1156 break;
1157 default:
1158 R600_ERR("unsupported %d\n", shader);
1159 return;
1160 }
1161 }
1162
1163 void r600_init_state_functions(struct r600_pipe_context *rctx)
1164 {
1165 rctx->context.create_blend_state = r600_create_blend_state;
1166 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1167 rctx->context.create_fs_state = r600_create_shader_state;
1168 rctx->context.create_rasterizer_state = r600_create_rs_state;
1169 rctx->context.create_sampler_state = r600_create_sampler_state;
1170 rctx->context.create_sampler_view = r600_create_sampler_view;
1171 rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1172 rctx->context.create_vs_state = r600_create_shader_state;
1173 rctx->context.bind_blend_state = r600_bind_blend_state;
1174 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
1175 rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1176 rctx->context.bind_fs_state = r600_bind_ps_shader;
1177 rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1178 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1179 rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1180 rctx->context.bind_vs_state = r600_bind_vs_shader;
1181 rctx->context.delete_blend_state = r600_delete_state;
1182 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1183 rctx->context.delete_fs_state = r600_delete_ps_shader;
1184 rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1185 rctx->context.delete_sampler_state = r600_delete_state;
1186 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1187 rctx->context.delete_vs_state = r600_delete_vs_shader;
1188 rctx->context.set_blend_color = r600_set_blend_color;
1189 rctx->context.set_clip_state = r600_set_clip_state;
1190 rctx->context.set_constant_buffer = r600_set_constant_buffer;
1191 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1192 rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1193 rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1194 rctx->context.set_sample_mask = r600_set_sample_mask;
1195 rctx->context.set_scissor_state = r600_set_scissor_state;
1196 rctx->context.set_stencil_ref = r600_set_stencil_ref;
1197 rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1198 rctx->context.set_index_buffer = r600_set_index_buffer;
1199 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1200 rctx->context.set_viewport_state = r600_set_viewport_state;
1201 rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1202 }
1203
1204 void r600_init_config(struct r600_pipe_context *rctx)
1205 {
1206 int ps_prio;
1207 int vs_prio;
1208 int gs_prio;
1209 int es_prio;
1210 int num_ps_gprs;
1211 int num_vs_gprs;
1212 int num_gs_gprs;
1213 int num_es_gprs;
1214 int num_temp_gprs;
1215 int num_ps_threads;
1216 int num_vs_threads;
1217 int num_gs_threads;
1218 int num_es_threads;
1219 int num_ps_stack_entries;
1220 int num_vs_stack_entries;
1221 int num_gs_stack_entries;
1222 int num_es_stack_entries;
1223 enum radeon_family family;
1224 struct r600_pipe_state *rstate = &rctx->config;
1225 u32 tmp;
1226
1227 family = r600_get_family(rctx->radeon);
1228 ps_prio = 0;
1229 vs_prio = 1;
1230 gs_prio = 2;
1231 es_prio = 3;
1232 switch (family) {
1233 case CHIP_R600:
1234 num_ps_gprs = 192;
1235 num_vs_gprs = 56;
1236 num_temp_gprs = 4;
1237 num_gs_gprs = 0;
1238 num_es_gprs = 0;
1239 num_ps_threads = 136;
1240 num_vs_threads = 48;
1241 num_gs_threads = 4;
1242 num_es_threads = 4;
1243 num_ps_stack_entries = 128;
1244 num_vs_stack_entries = 128;
1245 num_gs_stack_entries = 0;
1246 num_es_stack_entries = 0;
1247 break;
1248 case CHIP_RV630:
1249 case CHIP_RV635:
1250 num_ps_gprs = 84;
1251 num_vs_gprs = 36;
1252 num_temp_gprs = 4;
1253 num_gs_gprs = 0;
1254 num_es_gprs = 0;
1255 num_ps_threads = 144;
1256 num_vs_threads = 40;
1257 num_gs_threads = 4;
1258 num_es_threads = 4;
1259 num_ps_stack_entries = 40;
1260 num_vs_stack_entries = 40;
1261 num_gs_stack_entries = 32;
1262 num_es_stack_entries = 16;
1263 break;
1264 case CHIP_RV610:
1265 case CHIP_RV620:
1266 case CHIP_RS780:
1267 case CHIP_RS880:
1268 default:
1269 num_ps_gprs = 84;
1270 num_vs_gprs = 36;
1271 num_temp_gprs = 4;
1272 num_gs_gprs = 0;
1273 num_es_gprs = 0;
1274 num_ps_threads = 136;
1275 num_vs_threads = 48;
1276 num_gs_threads = 4;
1277 num_es_threads = 4;
1278 num_ps_stack_entries = 40;
1279 num_vs_stack_entries = 40;
1280 num_gs_stack_entries = 32;
1281 num_es_stack_entries = 16;
1282 break;
1283 case CHIP_RV670:
1284 num_ps_gprs = 144;
1285 num_vs_gprs = 40;
1286 num_temp_gprs = 4;
1287 num_gs_gprs = 0;
1288 num_es_gprs = 0;
1289 num_ps_threads = 136;
1290 num_vs_threads = 48;
1291 num_gs_threads = 4;
1292 num_es_threads = 4;
1293 num_ps_stack_entries = 40;
1294 num_vs_stack_entries = 40;
1295 num_gs_stack_entries = 32;
1296 num_es_stack_entries = 16;
1297 break;
1298 case CHIP_RV770:
1299 num_ps_gprs = 192;
1300 num_vs_gprs = 56;
1301 num_temp_gprs = 4;
1302 num_gs_gprs = 0;
1303 num_es_gprs = 0;
1304 num_ps_threads = 188;
1305 num_vs_threads = 60;
1306 num_gs_threads = 0;
1307 num_es_threads = 0;
1308 num_ps_stack_entries = 256;
1309 num_vs_stack_entries = 256;
1310 num_gs_stack_entries = 0;
1311 num_es_stack_entries = 0;
1312 break;
1313 case CHIP_RV730:
1314 case CHIP_RV740:
1315 num_ps_gprs = 84;
1316 num_vs_gprs = 36;
1317 num_temp_gprs = 4;
1318 num_gs_gprs = 0;
1319 num_es_gprs = 0;
1320 num_ps_threads = 188;
1321 num_vs_threads = 60;
1322 num_gs_threads = 0;
1323 num_es_threads = 0;
1324 num_ps_stack_entries = 128;
1325 num_vs_stack_entries = 128;
1326 num_gs_stack_entries = 0;
1327 num_es_stack_entries = 0;
1328 break;
1329 case CHIP_RV710:
1330 num_ps_gprs = 192;
1331 num_vs_gprs = 56;
1332 num_temp_gprs = 4;
1333 num_gs_gprs = 0;
1334 num_es_gprs = 0;
1335 num_ps_threads = 144;
1336 num_vs_threads = 48;
1337 num_gs_threads = 0;
1338 num_es_threads = 0;
1339 num_ps_stack_entries = 128;
1340 num_vs_stack_entries = 128;
1341 num_gs_stack_entries = 0;
1342 num_es_stack_entries = 0;
1343 break;
1344 }
1345
1346 rstate->id = R600_PIPE_STATE_CONFIG;
1347
1348 /* SQ_CONFIG */
1349 tmp = 0;
1350 switch (family) {
1351 case CHIP_RV610:
1352 case CHIP_RV620:
1353 case CHIP_RS780:
1354 case CHIP_RS880:
1355 case CHIP_RV710:
1356 break;
1357 default:
1358 tmp |= S_008C00_VC_ENABLE(1);
1359 break;
1360 }
1361 tmp |= S_008C00_DX9_CONSTS(0);
1362 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1363 tmp |= S_008C00_PS_PRIO(ps_prio);
1364 tmp |= S_008C00_VS_PRIO(vs_prio);
1365 tmp |= S_008C00_GS_PRIO(gs_prio);
1366 tmp |= S_008C00_ES_PRIO(es_prio);
1367 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1368
1369 /* SQ_GPR_RESOURCE_MGMT_1 */
1370 tmp = 0;
1371 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1372 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1373 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1374 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1375
1376 /* SQ_GPR_RESOURCE_MGMT_2 */
1377 tmp = 0;
1378 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1379 tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
1380 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1381
1382 /* SQ_THREAD_RESOURCE_MGMT */
1383 tmp = 0;
1384 tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1385 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1386 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1387 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1388 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1389
1390 /* SQ_STACK_RESOURCE_MGMT_1 */
1391 tmp = 0;
1392 tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1393 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1394 r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1395
1396 /* SQ_STACK_RESOURCE_MGMT_2 */
1397 tmp = 0;
1398 tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1399 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1400 r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1401
1402 r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1403 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1404
1405 if (family >= CHIP_RV770) {
1406 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1407 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
1408 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1409 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1410 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1411 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1412 } else {
1413 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1414 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
1415 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1416 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1417 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1418 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1419 }
1420 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1421 r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1422 r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1423 r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1424 r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1425 r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1426 r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1427 r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1428 r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1429 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1430 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1431 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1432 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1433 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1434 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1435 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1436 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1437 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1438 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1439 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1440 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1441 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1442 r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1443 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1444 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1445 r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1446
1447 r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1448 r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1449 r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1450 r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1451 r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1452 r600_context_pipe_state_set(&rctx->ctx, rstate);
1453 }
1454
1455 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
1456 {
1457 struct pipe_depth_stencil_alpha_state dsa;
1458 struct r600_pipe_state *rstate;
1459 boolean quirk = false;
1460
1461 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
1462 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
1463 quirk = true;
1464
1465 memset(&dsa, 0, sizeof(dsa));
1466
1467 if (quirk) {
1468 dsa.depth.enabled = 1;
1469 dsa.depth.func = PIPE_FUNC_LEQUAL;
1470 dsa.stencil[0].enabled = 1;
1471 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
1472 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
1473 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
1474 dsa.stencil[0].writemask = 0xff;
1475 }
1476
1477 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
1478 r600_pipe_state_add_reg(rstate,
1479 R_02880C_DB_SHADER_CONTROL,
1480 0x0,
1481 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
1482 r600_pipe_state_add_reg(rstate,
1483 R_028D0C_DB_RENDER_CONTROL,
1484 S_028D0C_DEPTH_COPY_ENABLE(1) |
1485 S_028D0C_STENCIL_COPY_ENABLE(1) |
1486 S_028D0C_COPY_CENTROID(1),
1487 S_028D0C_DEPTH_COPY_ENABLE(1) |
1488 S_028D0C_STENCIL_COPY_ENABLE(1) |
1489 S_028D0C_COPY_CENTROID(1), NULL);
1490 return rstate;
1491 }