src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "r600_formats.h"
  28 #include "r600_shader.h"
  29 #include "r600d.h"
  30
  31 #include "util/u_draw_quad.h"
  32 #include "util/u_format_s3tc.h"
  33 #include "util/u_index_modify.h"
  34 #include "util/u_memory.h"
  35 #include "util/u_upload_mgr.h"
  36 #include "util/u_math.h"
  37 #include "tgsi/tgsi_parse.h"
  38
  39 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
  40
  41 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw)
  42 {
  43         assert(!cb->buf);
  44         cb->buf = CALLOC(1, 4 * num_dw);
  45         cb->max_num_dw = num_dw;
  46 }
  47
  48 void r600_release_command_buffer(struct r600_command_buffer *cb)
  49 {
  50         FREE(cb->buf);
  51 }
  52
  53 void r600_init_atom(struct r600_context *rctx,
  54                     struct r600_atom *atom,
  55                     unsigned id,
  56                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  57                     unsigned num_dw)
  58 {
  59         assert(id < R600_NUM_ATOMS);
  60         assert(rctx->atoms[id] == NULL);
  61         rctx->atoms[id] = atom;
  62         atom->emit = (void*)emit;
  63         atom->num_dw = num_dw;
  64         atom->dirty = false;
  65 }
  66
  67 void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom)
  68 {
  69         r600_emit_command_buffer(rctx->b.rings.gfx.cs, ((struct r600_cso_state*)atom)->cb);
  70 }
  71
  72 void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom)
  73 {
  74         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
  75         struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom;
  76         unsigned alpha_ref = a->sx_alpha_ref;
  77
  78         if (rctx->b.chip_class >= EVERGREEN && a->cb0_export_16bpc) {
  79                 alpha_ref &= ~0x1FFF;
  80         }
  81
  82         r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL,
  83                                a->sx_alpha_test_control |
  84                                S_028410_ALPHA_TEST_BYPASS(a->bypass));
  85         r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref);
  86 }
  87
  88 static void r600_texture_barrier(struct pipe_context *ctx)
  89 {
  90         struct r600_context *rctx = (struct r600_context *)ctx;
  91
  92         rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
  93                        R600_CONTEXT_FLUSH_AND_INV_CB |
  94                        R600_CONTEXT_FLUSH_AND_INV |
  95                        R600_CONTEXT_WAIT_3D_IDLE;
  96 }
  97
  98 static unsigned r600_conv_pipe_prim(unsigned prim)
  99 {
 100         static const unsigned prim_conv[] = {
 101                 V_008958_DI_PT_POINTLIST,
 102                 V_008958_DI_PT_LINELIST,
 103                 V_008958_DI_PT_LINELOOP,
 104                 V_008958_DI_PT_LINESTRIP,
 105                 V_008958_DI_PT_TRILIST,
 106                 V_008958_DI_PT_TRISTRIP,
 107                 V_008958_DI_PT_TRIFAN,
 108                 V_008958_DI_PT_QUADLIST,
 109                 V_008958_DI_PT_QUADSTRIP,
 110                 V_008958_DI_PT_POLYGON,
 111                 V_008958_DI_PT_LINELIST_ADJ,
 112                 V_008958_DI_PT_LINESTRIP_ADJ,
 113                 V_008958_DI_PT_TRILIST_ADJ,
 114                 V_008958_DI_PT_TRISTRIP_ADJ,
 115                 V_008958_DI_PT_RECTLIST
 116         };
 117         return prim_conv[prim];
 118 }
 119
 120 /* common state between evergreen and r600 */
 121
 122 static void r600_bind_blend_state_internal(struct r600_context *rctx,
 123                 struct r600_blend_state *blend, bool blend_disable)
 124 {
 125         unsigned color_control;
 126         bool update_cb = false;
 127
 128         rctx->alpha_to_one = blend->alpha_to_one;
 129         rctx->dual_src_blend = blend->dual_src_blend;
 130
 131         if (!blend_disable) {
 132                 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer);
 133                 color_control = blend->cb_color_control;
 134         } else {
 135                 /* Blending is disabled. */
 136                 r600_set_cso_state_with_cb(&rctx->blend_state, blend, &blend->buffer_no_blend);
 137                 color_control = blend->cb_color_control_no_blend;
 138         }
 139
 140         /* Update derived states. */
 141         if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
 142                 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
 143                 update_cb = true;
 144         }
 145         if (rctx->b.chip_class <= R700 &&
 146             rctx->cb_misc_state.cb_color_control != color_control) {
 147                 rctx->cb_misc_state.cb_color_control = color_control;
 148                 update_cb = true;
 149         }
 150         if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
 151                 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
 152                 update_cb = true;
 153         }
 154         if (update_cb) {
 155                 rctx->cb_misc_state.atom.dirty = true;
 156         }
 157 }
 158
 159 static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 160 {
 161         struct r600_context *rctx = (struct r600_context *)ctx;
 162         struct r600_blend_state *blend = (struct r600_blend_state *)state;
 163
 164         if (blend == NULL)
 165                 return;
 166
 167         r600_bind_blend_state_internal(rctx, blend, rctx->force_blend_disable);
 168 }
 169
 170 static void r600_set_blend_color(struct pipe_context *ctx,
 171                                  const struct pipe_blend_color *state)
 172 {
 173         struct r600_context *rctx = (struct r600_context *)ctx;
 174
 175         rctx->blend_color.state = *state;
 176         rctx->blend_color.atom.dirty = true;
 177 }
 178
 179 void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom)
 180 {
 181         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 182         struct pipe_blend_color *state = &rctx->blend_color.state;
 183
 184         r600_write_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
 185         radeon_emit(cs, fui(state->color[0])); /* R_028414_CB_BLEND_RED */
 186         radeon_emit(cs, fui(state->color[1])); /* R_028418_CB_BLEND_GREEN */
 187         radeon_emit(cs, fui(state->color[2])); /* R_02841C_CB_BLEND_BLUE */
 188         radeon_emit(cs, fui(state->color[3])); /* R_028420_CB_BLEND_ALPHA */
 189 }
 190
 191 void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom)
 192 {
 193         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 194         struct r600_vgt_state *a = (struct r600_vgt_state *)atom;
 195
 196         r600_write_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en);
 197         r600_write_context_reg_seq(cs, R_028408_VGT_INDX_OFFSET, 2);
 198         radeon_emit(cs, a->vgt_indx_offset); /* R_028408_VGT_INDX_OFFSET */
 199         radeon_emit(cs, a->vgt_multi_prim_ib_reset_indx); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
 200 }
 201
 202 static void r600_set_clip_state(struct pipe_context *ctx,
 203                                 const struct pipe_clip_state *state)
 204 {
 205         struct r600_context *rctx = (struct r600_context *)ctx;
 206         struct pipe_constant_buffer cb;
 207
 208         rctx->clip_state.state = *state;
 209         rctx->clip_state.atom.dirty = true;
 210
 211         cb.buffer = NULL;
 212         cb.user_buffer = state->ucp;
 213         cb.buffer_offset = 0;
 214         cb.buffer_size = 4*4*8;
 215         ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
 216         pipe_resource_reference(&cb.buffer, NULL);
 217 }
 218
 219 static void r600_set_stencil_ref(struct pipe_context *ctx,
 220                                  const struct r600_stencil_ref *state)
 221 {
 222         struct r600_context *rctx = (struct r600_context *)ctx;
 223
 224         rctx->stencil_ref.state = *state;
 225         rctx->stencil_ref.atom.dirty = true;
 226 }
 227
 228 void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom)
 229 {
 230         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 231         struct r600_stencil_ref_state *a = (struct r600_stencil_ref_state*)atom;
 232
 233         r600_write_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
 234         radeon_emit(cs, /* R_028430_DB_STENCILREFMASK */
 235                          S_028430_STENCILREF(a->state.ref_value[0]) |
 236                          S_028430_STENCILMASK(a->state.valuemask[0]) |
 237                          S_028430_STENCILWRITEMASK(a->state.writemask[0]));
 238         radeon_emit(cs, /* R_028434_DB_STENCILREFMASK_BF */
 239                          S_028434_STENCILREF_BF(a->state.ref_value[1]) |
 240                          S_028434_STENCILMASK_BF(a->state.valuemask[1]) |
 241                          S_028434_STENCILWRITEMASK_BF(a->state.writemask[1]));
 242 }
 243
 244 static void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 245                                       const struct pipe_stencil_ref *state)
 246 {
 247         struct r600_context *rctx = (struct r600_context *)ctx;
 248         struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso;
 249         struct r600_stencil_ref ref;
 250
 251         rctx->stencil_ref.pipe_state = *state;
 252
 253         if (!dsa)
 254                 return;
 255
 256         ref.ref_value[0] = state->ref_value[0];
 257         ref.ref_value[1] = state->ref_value[1];
 258         ref.valuemask[0] = dsa->valuemask[0];
 259         ref.valuemask[1] = dsa->valuemask[1];
 260         ref.writemask[0] = dsa->writemask[0];
 261         ref.writemask[1] = dsa->writemask[1];
 262
 263         r600_set_stencil_ref(ctx, &ref);
 264 }
 265
 266 static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 267 {
 268         struct r600_context *rctx = (struct r600_context *)ctx;
 269         struct r600_dsa_state *dsa = state;
 270         struct r600_stencil_ref ref;
 271
 272         if (state == NULL)
 273                 return;
 274
 275         r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer);
 276
 277         ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0];
 278         ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1];
 279         ref.valuemask[0] = dsa->valuemask[0];
 280         ref.valuemask[1] = dsa->valuemask[1];
 281         ref.writemask[0] = dsa->writemask[0];
 282         ref.writemask[1] = dsa->writemask[1];
 283         if (rctx->zwritemask != dsa->zwritemask) {
 284                 rctx->zwritemask = dsa->zwritemask;
 285                 if (rctx->b.chip_class >= EVERGREEN) {
 286                         /* work around some issue when not writting to zbuffer
 287                          * we are having lockup on evergreen so do not enable
 288                          * hyperz when not writting zbuffer
 289                          */
 290                         rctx->db_misc_state.atom.dirty = true;
 291                 }
 292         }
 293
 294         r600_set_stencil_ref(ctx, &ref);
 295
 296         /* Update alphatest state. */
 297         if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control ||
 298             rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) {
 299                 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control;
 300                 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref;
 301                 rctx->alphatest_state.atom.dirty = true;
 302                 if (rctx->b.chip_class >= EVERGREEN) {
 303                         evergreen_update_db_shader_control(rctx);
 304                 } else {
 305                         r600_update_db_shader_control(rctx);
 306                 }
 307         }
 308 }
 309
 310 static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 311 {
 312         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 313         struct r600_context *rctx = (struct r600_context *)ctx;
 314
 315         if (state == NULL)
 316                 return;
 317
 318         rctx->rasterizer = rs;
 319
 320         r600_set_cso_state_with_cb(&rctx->rasterizer_state, rs, &rs->buffer);
 321
 322         if (rs->offset_enable &&
 323             (rs->offset_units != rctx->poly_offset_state.offset_units ||
 324              rs->offset_scale != rctx->poly_offset_state.offset_scale)) {
 325                 rctx->poly_offset_state.offset_units = rs->offset_units;
 326                 rctx->poly_offset_state.offset_scale = rs->offset_scale;
 327                 rctx->poly_offset_state.atom.dirty = true;
 328         }
 329
 330         /* Update clip_misc_state. */
 331         if (rctx->clip_misc_state.pa_cl_clip_cntl != rs->pa_cl_clip_cntl ||
 332             rctx->clip_misc_state.clip_plane_enable != rs->clip_plane_enable) {
 333                 rctx->clip_misc_state.pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 334                 rctx->clip_misc_state.clip_plane_enable = rs->clip_plane_enable;
 335                 rctx->clip_misc_state.atom.dirty = true;
 336         }
 337
 338         /* Workaround for a missing scissor enable on r600. */
 339         if (rctx->b.chip_class == R600 &&
 340             rs->scissor_enable != rctx->scissor.enable) {
 341                 rctx->scissor.enable = rs->scissor_enable;
 342                 rctx->scissor.atom.dirty = true;
 343         }
 344
 345         /* Re-emit PA_SC_LINE_STIPPLE. */
 346         rctx->last_primitive_type = -1;
 347 }
 348
 349 static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 350 {
 351         struct r600_rasterizer_state *rs = (struct r600_rasterizer_state *)state;
 352
 353         r600_release_command_buffer(&rs->buffer);
 354         FREE(rs);
 355 }
 356
 357 static void r600_sampler_view_destroy(struct pipe_context *ctx,
 358                                       struct pipe_sampler_view *state)
 359 {
 360         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 361
 362         pipe_resource_reference(&state->texture, NULL);
 363         FREE(resource);
 364 }
 365
 366 void r600_sampler_states_dirty(struct r600_context *rctx,
 367                                struct r600_sampler_states *state)
 368 {
 369         if (state->dirty_mask) {
 370                 if (state->dirty_mask & state->has_bordercolor_mask) {
 371                         rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
 372                 }
 373                 state->atom.num_dw =
 374                         util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
 375                         util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
 376                 state->atom.dirty = true;
 377         }
 378 }
 379
 380 static void r600_bind_sampler_states(struct pipe_context *pipe,
 381                                unsigned shader,
 382                                unsigned start,
 383                                unsigned count, void **states)
 384 {
 385         struct r600_context *rctx = (struct r600_context *)pipe;
 386         struct r600_textures_info *dst = &rctx->samplers[shader];
 387         struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
 388         int seamless_cube_map = -1;
 389         unsigned i;
 390         /* This sets 1-bit for states with index >= count. */
 391         uint32_t disable_mask = ~((1ull << count) - 1);
 392         /* These are the new states set by this function. */
 393         uint32_t new_mask = 0;
 394
 395         assert(start == 0); /* XXX fix below */
 396
 397         if (shader != PIPE_SHADER_VERTEX &&
 398             shader != PIPE_SHADER_FRAGMENT) {
 399                 return;
 400         }
 401
 402         for (i = 0; i < count; i++) {
 403                 struct r600_pipe_sampler_state *rstate = rstates[i];
 404
 405                 if (rstate == dst->states.states[i]) {
 406                         continue;
 407                 }
 408
 409                 if (rstate) {
 410                         if (rstate->border_color_use) {
 411                                 dst->states.has_bordercolor_mask |= 1 << i;
 412                         } else {
 413                                 dst->states.has_bordercolor_mask &= ~(1 << i);
 414                         }
 415                         seamless_cube_map = rstate->seamless_cube_map;
 416
 417                         new_mask |= 1 << i;
 418                 } else {
 419                         disable_mask |= 1 << i;
 420                 }
 421         }
 422
 423         memcpy(dst->states.states, rstates, sizeof(void*) * count);
 424         memset(dst->states.states + count, 0, sizeof(void*) * (NUM_TEX_UNITS - count));
 425
 426         dst->states.enabled_mask &= ~disable_mask;
 427         dst->states.dirty_mask &= dst->states.enabled_mask;
 428         dst->states.enabled_mask |= new_mask;
 429         dst->states.dirty_mask |= new_mask;
 430         dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
 431
 432         r600_sampler_states_dirty(rctx, &dst->states);
 433
 434         /* Seamless cubemap state. */
 435         if (rctx->b.chip_class <= R700 &&
 436             seamless_cube_map != -1 &&
 437             seamless_cube_map != rctx->seamless_cube_map.enabled) {
 438                 /* change in TA_CNTL_AUX need a pipeline flush */
 439                 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
 440                 rctx->seamless_cube_map.enabled = seamless_cube_map;
 441                 rctx->seamless_cube_map.atom.dirty = true;
 442         }
 443 }
 444
 445 static void r600_delete_sampler_state(struct pipe_context *ctx, void *state)
 446 {
 447         free(state);
 448 }
 449
 450 static void r600_delete_blend_state(struct pipe_context *ctx, void *state)
 451 {
 452         struct r600_blend_state *blend = (struct r600_blend_state*)state;
 453
 454         r600_release_command_buffer(&blend->buffer);
 455         r600_release_command_buffer(&blend->buffer_no_blend);
 456         FREE(blend);
 457 }
 458
 459 static void r600_delete_dsa_state(struct pipe_context *ctx, void *state)
 460 {
 461         struct r600_dsa_state *dsa = (struct r600_dsa_state *)state;
 462
 463         r600_release_command_buffer(&dsa->buffer);
 464         free(dsa);
 465 }
 466
 467 static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 468 {
 469         struct r600_context *rctx = (struct r600_context *)ctx;
 470
 471         r600_set_cso_state(&rctx->vertex_fetch_shader, state);
 472 }
 473
 474 static void r600_delete_vertex_elements(struct pipe_context *ctx, void *state)
 475 {
 476         struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state;
 477         pipe_resource_reference((struct pipe_resource**)&shader->buffer, NULL);
 478         FREE(shader);
 479 }
 480
 481 static void r600_set_index_buffer(struct pipe_context *ctx,
 482                            const struct pipe_index_buffer *ib)
 483 {
 484         struct r600_context *rctx = (struct r600_context *)ctx;
 485
 486         if (ib) {
 487                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 488                 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
 489                 r600_context_add_resource_size(ctx, ib->buffer);
 490         } else {
 491                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 492         }
 493 }
 494
 495 void r600_vertex_buffers_dirty(struct r600_context *rctx)
 496 {
 497         if (rctx->vertex_buffer_state.dirty_mask) {
 498                 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
 499                 rctx->vertex_buffer_state.atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 12 : 11) *
 500                                                util_bitcount(rctx->vertex_buffer_state.dirty_mask);
 501                 rctx->vertex_buffer_state.atom.dirty = true;
 502         }
 503 }
 504
 505 static void r600_set_vertex_buffers(struct pipe_context *ctx,
 506                                     unsigned start_slot, unsigned count,
 507                                     const struct pipe_vertex_buffer *input)
 508 {
 509         struct r600_context *rctx = (struct r600_context *)ctx;
 510         struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
 511         struct pipe_vertex_buffer *vb = state->vb + start_slot;
 512         unsigned i;
 513         uint32_t disable_mask = 0;
 514         /* These are the new buffers set by this function. */
 515         uint32_t new_buffer_mask = 0;
 516
 517         /* Set vertex buffers. */
 518         if (input) {
 519                 for (i = 0; i < count; i++) {
 520                         if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
 521                                 if (input[i].buffer) {
 522                                         vb[i].stride = input[i].stride;
 523                                         vb[i].buffer_offset = input[i].buffer_offset;
 524                                         pipe_resource_reference(&vb[i].buffer, input[i].buffer);
 525                                         new_buffer_mask |= 1 << i;
 526                                         r600_context_add_resource_size(ctx, input[i].buffer);
 527                                 } else {
 528                                         pipe_resource_reference(&vb[i].buffer, NULL);
 529                                         disable_mask |= 1 << i;
 530                                 }
 531                         }
 532                 }
 533         } else {
 534                 for (i = 0; i < count; i++) {
 535                         pipe_resource_reference(&vb[i].buffer, NULL);
 536                 }
 537                 disable_mask = ((1ull << count) - 1);
 538         }
 539
 540         disable_mask <<= start_slot;
 541         new_buffer_mask <<= start_slot;
 542
 543         rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
 544         rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
 545         rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
 546         rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
 547
 548         r600_vertex_buffers_dirty(rctx);
 549 }
 550
 551 void r600_sampler_views_dirty(struct r600_context *rctx,
 552                               struct r600_samplerview_state *state)
 553 {
 554         if (state->dirty_mask) {
 555                 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
 556                 state->atom.num_dw = (rctx->b.chip_class >= EVERGREEN ? 14 : 13) *
 557                                      util_bitcount(state->dirty_mask);
 558                 state->atom.dirty = true;
 559         }
 560 }
 561
 562 static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
 563                                    unsigned start, unsigned count,
 564                                    struct pipe_sampler_view **views)
 565 {
 566         struct r600_context *rctx = (struct r600_context *) pipe;
 567         struct r600_textures_info *dst = &rctx->samplers[shader];
 568         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
 569         uint32_t dirty_sampler_states_mask = 0;
 570         unsigned i;
 571         /* This sets 1-bit for textures with index >= count. */
 572         uint32_t disable_mask = ~((1ull << count) - 1);
 573         /* These are the new textures set by this function. */
 574         uint32_t new_mask = 0;
 575
 576         /* Set textures with index >= count to NULL. */
 577         uint32_t remaining_mask;
 578
 579         assert(start == 0); /* XXX fix below */
 580
 581         if (shader == PIPE_SHADER_COMPUTE) {
 582                 evergreen_set_cs_sampler_view(pipe, start, count, views);
 583                 return;
 584         }
 585
 586         remaining_mask = dst->views.enabled_mask & disable_mask;
 587
 588         while (remaining_mask) {
 589                 i = u_bit_scan(&remaining_mask);
 590                 assert(dst->views.views[i]);
 591
 592                 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 593         }
 594
 595         for (i = 0; i < count; i++) {
 596                 if (rviews[i] == dst->views.views[i]) {
 597                         continue;
 598                 }
 599
 600                 if (rviews[i]) {
 601                         struct r600_texture *rtex =
 602                                 (struct r600_texture*)rviews[i]->base.texture;
 603
 604                         if (rviews[i]->base.texture->target != PIPE_BUFFER) {
 605                                 if (rtex->is_depth && !rtex->is_flushing_texture) {
 606                                         dst->views.compressed_depthtex_mask |= 1 << i;
 607                                 } else {
 608                                         dst->views.compressed_depthtex_mask &= ~(1 << i);
 609                                 }
 610
 611                                 /* Track compressed colorbuffers. */
 612                                 if (rtex->cmask.size) {
 613                                         dst->views.compressed_colortex_mask |= 1 << i;
 614                                 } else {
 615                                         dst->views.compressed_colortex_mask &= ~(1 << i);
 616                                 }
 617                         }
 618                         /* Changing from array to non-arrays textures and vice versa requires
 619                          * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
 620                         if (rctx->b.chip_class <= R700 &&
 621                             (dst->states.enabled_mask & (1 << i)) &&
 622                             (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
 623                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
 624                                 dirty_sampler_states_mask |= 1 << i;
 625                         }
 626
 627                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
 628                         new_mask |= 1 << i;
 629                         r600_context_add_resource_size(pipe, views[i]->texture);
 630                 } else {
 631                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 632                         disable_mask |= 1 << i;
 633                 }
 634         }
 635
 636         dst->views.enabled_mask &= ~disable_mask;
 637         dst->views.dirty_mask &= dst->views.enabled_mask;
 638         dst->views.enabled_mask |= new_mask;
 639         dst->views.dirty_mask |= new_mask;
 640         dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
 641         dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
 642         dst->views.dirty_txq_constants = TRUE;
 643         dst->views.dirty_buffer_constants = TRUE;
 644         r600_sampler_views_dirty(rctx, &dst->views);
 645
 646         if (dirty_sampler_states_mask) {
 647                 dst->states.dirty_mask |= dirty_sampler_states_mask;
 648                 r600_sampler_states_dirty(rctx, &dst->states);
 649         }
 650 }
 651
 652 static void r600_set_viewport_states(struct pipe_context *ctx,
 653                                      unsigned start_slot,
 654                                      unsigned num_viewports,
 655                                      const struct pipe_viewport_state *state)
 656 {
 657         struct r600_context *rctx = (struct r600_context *)ctx;
 658
 659         rctx->viewport.state = *state;
 660         rctx->viewport.atom.dirty = true;
 661 }
 662
 663 void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
 664 {
 665         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
 666         struct pipe_viewport_state *state = &rctx->viewport.state;
 667
 668         r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
 669         radeon_emit(cs, fui(state->scale[0]));     /* R_02843C_PA_CL_VPORT_XSCALE_0  */
 670         radeon_emit(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
 671         radeon_emit(cs, fui(state->scale[1]));     /* R_028444_PA_CL_VPORT_YSCALE_0  */
 672         radeon_emit(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
 673         radeon_emit(cs, fui(state->scale[2]));     /* R_02844C_PA_CL_VPORT_ZSCALE_0  */
 674         radeon_emit(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
 675 }
 676
 677 /* Compute the key for the hw shader variant */
 678 static INLINE struct r600_shader_key r600_shader_selector_key(struct pipe_context * ctx,
 679                 struct r600_pipe_shader_selector * sel)
 680 {
 681         struct r600_context *rctx = (struct r600_context *)ctx;
 682         struct r600_shader_key key;
 683         memset(&key, 0, sizeof(key));
 684
 685         if (sel->type == PIPE_SHADER_FRAGMENT) {
 686                 key.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side;
 687                 key.alpha_to_one = rctx->alpha_to_one &&
 688                                    rctx->rasterizer && rctx->rasterizer->multisample_enable &&
 689                                    !rctx->framebuffer.cb0_is_integer;
 690                 key.nr_cbufs = rctx->framebuffer.state.nr_cbufs;
 691                 /* Dual-source blending only makes sense with nr_cbufs == 1. */
 692                 if (key.nr_cbufs == 1 && rctx->dual_src_blend)
 693                         key.nr_cbufs = 2;
 694         }
 695         return key;
 696 }
 697
 698 /* Select the hw shader variant depending on the current state.
 699  * (*dirty) is set to 1 if current variant was changed */
 700 static int r600_shader_select(struct pipe_context *ctx,
 701         struct r600_pipe_shader_selector* sel,
 702         bool *dirty)
 703 {
 704         struct r600_shader_key key;
 705         struct r600_context *rctx = (struct r600_context *)ctx;
 706         struct r600_pipe_shader * shader = NULL;
 707         int r;
 708
 709         memset(&key, 0, sizeof(key));
 710         key = r600_shader_selector_key(ctx, sel);
 711
 712         /* Check if we don't need to change anything.
 713          * This path is also used for most shaders that don't need multiple
 714          * variants, it will cost just a computation of the key and this
 715          * test. */
 716         if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
 717                 return 0;
 718         }
 719
 720         /* lookup if we have other variants in the list */
 721         if (sel->num_shaders > 1) {
 722                 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
 723
 724                 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
 725                         p = c;
 726                         c = c->next_variant;
 727                 }
 728
 729                 if (c) {
 730                         p->next_variant = c->next_variant;
 731                         shader = c;
 732                 }
 733         }
 734
 735         if (unlikely(!shader)) {
 736                 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
 737                 shader->selector = sel;
 738
 739                 r = r600_pipe_shader_create(ctx, shader, key);
 740                 if (unlikely(r)) {
 741                         R600_ERR("Failed to build shader variant (type=%u) %d\n",
 742                                  sel->type, r);
 743                         sel->current = NULL;
 744                         FREE(shader);
 745                         return r;
 746                 }
 747
 748                 /* We don't know the value of nr_ps_max_color_exports until we built
 749                  * at least one variant, so we may need to recompute the key after
 750                  * building first variant. */
 751                 if (sel->type == PIPE_SHADER_FRAGMENT &&
 752                                 sel->num_shaders == 0) {
 753                         sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
 754                         key = r600_shader_selector_key(ctx, sel);
 755                 }
 756
 757                 memcpy(&shader->key, &key, sizeof(key));
 758                 sel->num_shaders++;
 759         }
 760
 761         if (dirty)
 762                 *dirty = true;
 763
 764         shader->next_variant = sel->current;
 765         sel->current = shader;
 766
 767         if (rctx->ps_shader &&
 768             rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 769                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 770                 rctx->cb_misc_state.atom.dirty = true;
 771         }
 772         return 0;
 773 }
 774
 775 static void *r600_create_shader_state(struct pipe_context *ctx,
 776                                const struct pipe_shader_state *state,
 777                                unsigned pipe_shader_type)
 778 {
 779         struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
 780         int r;
 781
 782         sel->type = pipe_shader_type;
 783         sel->tokens = tgsi_dup_tokens(state->tokens);
 784         sel->so = state->stream_output;
 785
 786         r = r600_shader_select(ctx, sel, NULL);
 787         if (r)
 788             return NULL;
 789
 790         return sel;
 791 }
 792
 793 static void *r600_create_ps_state(struct pipe_context *ctx,
 794                                          const struct pipe_shader_state *state)
 795 {
 796         return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
 797 }
 798
 799 static void *r600_create_vs_state(struct pipe_context *ctx,
 800                                          const struct pipe_shader_state *state)
 801 {
 802         return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
 803 }
 804
 805 static void r600_bind_ps_state(struct pipe_context *ctx, void *state)
 806 {
 807         struct r600_context *rctx = (struct r600_context *)ctx;
 808
 809         if (!state)
 810                 state = rctx->dummy_pixel_shader;
 811
 812         rctx->pixel_shader.shader = rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
 813         rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
 814         rctx->pixel_shader.atom.dirty = true;
 815
 816         r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo);
 817
 818         if (rctx->b.chip_class <= R700) {
 819                 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
 820
 821                 if (rctx->cb_misc_state.multiwrite != multiwrite) {
 822                         rctx->cb_misc_state.multiwrite = multiwrite;
 823                         rctx->cb_misc_state.atom.dirty = true;
 824                 }
 825         }
 826
 827         if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 828                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 829                 rctx->cb_misc_state.atom.dirty = true;
 830         }
 831
 832         if (rctx->b.chip_class >= EVERGREEN) {
 833                 evergreen_update_db_shader_control(rctx);
 834         } else {
 835                 r600_update_db_shader_control(rctx);
 836         }
 837 }
 838
 839 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
 840 {
 841         struct r600_context *rctx = (struct r600_context *)ctx;
 842
 843         if (!state)
 844                 return;
 845
 846         rctx->vertex_shader.shader = rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
 847         rctx->vertex_shader.atom.dirty = true;
 848         rctx->b.streamout.stride_in_dw = rctx->vs_shader->so.stride;
 849
 850         r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo);
 851
 852         /* Update clip misc state. */
 853         if (rctx->vs_shader->current->pa_cl_vs_out_cntl != rctx->clip_misc_state.pa_cl_vs_out_cntl ||
 854             rctx->vs_shader->current->shader.clip_dist_write != rctx->clip_misc_state.clip_dist_write) {
 855                 rctx->clip_misc_state.pa_cl_vs_out_cntl = rctx->vs_shader->current->pa_cl_vs_out_cntl;
 856                 rctx->clip_misc_state.clip_dist_write = rctx->vs_shader->current->shader.clip_dist_write;
 857                 rctx->clip_misc_state.atom.dirty = true;
 858         }
 859 }
 860
 861 static void r600_delete_shader_selector(struct pipe_context *ctx,
 862                 struct r600_pipe_shader_selector *sel)
 863 {
 864         struct r600_pipe_shader *p = sel->current, *c;
 865         while (p) {
 866                 c = p->next_variant;
 867                 r600_pipe_shader_destroy(ctx, p);
 868                 free(p);
 869                 p = c;
 870         }
 871
 872         free(sel->tokens);
 873         free(sel);
 874 }
 875
 876
 877 static void r600_delete_ps_state(struct pipe_context *ctx, void *state)
 878 {
 879         struct r600_context *rctx = (struct r600_context *)ctx;
 880         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 881
 882         if (rctx->ps_shader == sel) {
 883                 rctx->ps_shader = NULL;
 884         }
 885
 886         r600_delete_shader_selector(ctx, sel);
 887 }
 888
 889 static void r600_delete_vs_state(struct pipe_context *ctx, void *state)
 890 {
 891         struct r600_context *rctx = (struct r600_context *)ctx;
 892         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 893
 894         if (rctx->vs_shader == sel) {
 895                 rctx->vs_shader = NULL;
 896         }
 897
 898         r600_delete_shader_selector(ctx, sel);
 899 }
 900
 901 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 902 {
 903         if (state->dirty_mask) {
 904                 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE;
 905                 state->atom.num_dw = rctx->b.chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
 906                                                                    : util_bitcount(state->dirty_mask)*19;
 907                 state->atom.dirty = true;
 908         }
 909 }
 910
 911 static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 912                                      struct pipe_constant_buffer *input)
 913 {
 914         struct r600_context *rctx = (struct r600_context *)ctx;
 915         struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
 916         struct pipe_constant_buffer *cb;
 917         const uint8_t *ptr;
 918
 919         /* Note that the state tracker can unbind constant buffers by
 920          * passing NULL here.
 921          */
 922         if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
 923                 state->enabled_mask &= ~(1 << index);
 924                 state->dirty_mask &= ~(1 << index);
 925                 pipe_resource_reference(&state->cb[index].buffer, NULL);
 926                 return;
 927         }
 928
 929         cb = &state->cb[index];
 930         cb->buffer_size = input->buffer_size;
 931
 932         ptr = input->user_buffer;
 933
 934         if (ptr) {
 935                 /* Upload the user buffer. */
 936                 if (R600_BIG_ENDIAN) {
 937                         uint32_t *tmpPtr;
 938                         unsigned i, size = input->buffer_size;
 939
 940                         if (!(tmpPtr = malloc(size))) {
 941                                 R600_ERR("Failed to allocate BE swap buffer.\n");
 942                                 return;
 943                         }
 944
 945                         for (i = 0; i < size / 4; ++i) {
 946                                 tmpPtr[i] = util_bswap32(((uint32_t *)ptr)[i]);
 947                         }
 948
 949                         u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
 950                         free(tmpPtr);
 951                 } else {
 952                         u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
 953                 }
 954                 /* account it in gtt */
 955                 rctx->b.gtt += input->buffer_size;
 956         } else {
 957                 /* Setup the hw buffer. */
 958                 cb->buffer_offset = input->buffer_offset;
 959                 pipe_resource_reference(&cb->buffer, input->buffer);
 960                 r600_context_add_resource_size(ctx, input->buffer);
 961         }
 962
 963         state->enabled_mask |= 1 << index;
 964         state->dirty_mask |= 1 << index;
 965         r600_constant_buffers_dirty(rctx, state);
 966 }
 967
 968 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
 969 {
 970         struct r600_context *rctx = (struct r600_context*)pipe;
 971
 972         if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask)
 973                 return;
 974
 975         rctx->sample_mask.sample_mask = sample_mask;
 976         rctx->sample_mask.atom.dirty = true;
 977 }
 978
 979 /*
 980  * On r600/700 hw we don't have vertex fetch swizzle, though TBO
 981  * doesn't require full swizzles it does need masking and setting alpha
 982  * to one, so we setup a set of 5 constants with the masks + alpha value
 983  * then in the shader, we AND the 4 components with 0xffffffff or 0,
 984  * then OR the alpha with the value given here.
 985  * We use a 6th constant to store the txq buffer size in
 986  */
 987 static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
 988 {
 989         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
 990         int bits;
 991         uint32_t array_size;
 992         struct pipe_constant_buffer cb;
 993         int i, j;
 994
 995         if (!samplers->views.dirty_buffer_constants)
 996                 return;
 997
 998         samplers->views.dirty_buffer_constants = FALSE;
 999
1000         bits = util_last_bit(samplers->views.enabled_mask);
1001         array_size = bits * 8 * sizeof(uint32_t) * 4;
1002         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1003         memset(samplers->buffer_constants, 0, array_size);
1004         for (i = 0; i < bits; i++) {
1005                 if (samplers->views.enabled_mask & (1 << i)) {
1006                         int offset = i * 8;
1007                         const struct util_format_description *desc;
1008                         desc = util_format_description(samplers->views.views[i]->base.format);
1009
1010                         for (j = 0; j < 4; j++)
1011                                 if (j < desc->nr_channels)
1012                                         samplers->buffer_constants[offset+j] = 0xffffffff;
1013                                 else
1014                                         samplers->buffer_constants[offset+j] = 0x0;
1015                         if (desc->nr_channels < 4) {
1016                                 if (desc->channel[0].pure_integer)
1017                                         samplers->buffer_constants[offset+4] = 1;
1018                                 else
1019                                         samplers->buffer_constants[offset+4] = 0x3f800000;
1020                         } else
1021                                 samplers->buffer_constants[offset + 4] = 0;
1022
1023                         samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1024                 }
1025         }
1026
1027         cb.buffer = NULL;
1028         cb.user_buffer = samplers->buffer_constants;
1029         cb.buffer_offset = 0;
1030         cb.buffer_size = array_size;
1031         rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1032         pipe_resource_reference(&cb.buffer, NULL);
1033 }
1034
1035 /* On evergreen we only need to store the buffer size for TXQ */
1036 static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
1037 {
1038         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1039         int bits;
1040         uint32_t array_size;
1041         struct pipe_constant_buffer cb;
1042         int i;
1043
1044         if (!samplers->views.dirty_buffer_constants)
1045                 return;
1046
1047         samplers->views.dirty_buffer_constants = FALSE;
1048
1049         bits = util_last_bit(samplers->views.enabled_mask);
1050         array_size = bits * sizeof(uint32_t) * 4;
1051         samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
1052         memset(samplers->buffer_constants, 0, array_size);
1053         for (i = 0; i < bits; i++)
1054                 if (samplers->views.enabled_mask & (1 << i))
1055                    samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
1056
1057         cb.buffer = NULL;
1058         cb.user_buffer = samplers->buffer_constants;
1059         cb.buffer_offset = 0;
1060         cb.buffer_size = array_size;
1061         rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
1062         pipe_resource_reference(&cb.buffer, NULL);
1063 }
1064
1065 static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
1066 {
1067         struct r600_textures_info *samplers = &rctx->samplers[shader_type];
1068         int bits;
1069         uint32_t array_size;
1070         struct pipe_constant_buffer cb;
1071         int i;
1072
1073         if (!samplers->views.dirty_txq_constants)
1074                 return;
1075
1076         samplers->views.dirty_txq_constants = FALSE;
1077
1078         bits = util_last_bit(samplers->views.enabled_mask);
1079         array_size = bits * sizeof(uint32_t) * 4;
1080         samplers->txq_constants = realloc(samplers->txq_constants, array_size);
1081         memset(samplers->txq_constants, 0, array_size);
1082         for (i = 0; i < bits; i++)
1083                 if (samplers->views.enabled_mask & (1 << i))
1084                         samplers->txq_constants[i] = samplers->views.views[i]->base.texture->array_size / 6;
1085
1086         cb.buffer = NULL;
1087         cb.user_buffer = samplers->txq_constants;
1088         cb.buffer_offset = 0;
1089         cb.buffer_size = array_size;
1090         rctx->b.b.set_constant_buffer(&rctx->b.b, shader_type, R600_TXQ_CONST_BUFFER, &cb);
1091         pipe_resource_reference(&cb.buffer, NULL);
1092 }
1093
1094 static bool r600_update_derived_state(struct r600_context *rctx)
1095 {
1096         struct pipe_context * ctx = (struct pipe_context*)rctx;
1097         bool ps_dirty = false;
1098         bool blend_disable;
1099
1100         if (!rctx->blitter->running) {
1101                 unsigned i;
1102
1103                 /* Decompress textures if needed. */
1104                 for (i = 0; i < PIPE_SHADER_TYPES; i++) {
1105                         struct r600_samplerview_state *views = &rctx->samplers[i].views;
1106                         if (views->compressed_depthtex_mask) {
1107                                 r600_decompress_depth_textures(rctx, views);
1108                         }
1109                         if (views->compressed_colortex_mask) {
1110                                 r600_decompress_color_textures(rctx, views);
1111                         }
1112                 }
1113         }
1114
1115         r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
1116
1117         if (rctx->ps_shader && rctx->rasterizer &&
1118             ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) ||
1119              (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
1120
1121                 if (rctx->b.chip_class >= EVERGREEN)
1122                         evergreen_update_ps_state(ctx, rctx->ps_shader->current);
1123                 else
1124                         r600_update_ps_state(ctx, rctx->ps_shader->current);
1125
1126                 ps_dirty = true;
1127         }
1128
1129         if (ps_dirty) {
1130                 rctx->pixel_shader.atom.num_dw = rctx->ps_shader->current->command_buffer.num_dw;
1131                 rctx->pixel_shader.atom.dirty = true;
1132         }
1133
1134         /* on R600 we stuff masks + txq info into one constant buffer */
1135         /* on evergreen we only need a txq info one */
1136         if (rctx->b.chip_class < EVERGREEN) {
1137                 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1138                         r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1139                 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1140                         r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1141         } else {
1142                 if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
1143                         eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
1144                 if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
1145                         eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
1146         }
1147
1148
1149         if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
1150                 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
1151         if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
1152                 r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_VERTEX);
1153
1154         if (rctx->b.chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
1155                 if (!r600_adjust_gprs(rctx)) {
1156                         /* discard rendering */
1157                         return false;
1158                 }
1159         }
1160
1161         blend_disable = (rctx->dual_src_blend &&
1162                         rctx->ps_shader->current->nr_ps_color_outputs < 2);
1163
1164         if (blend_disable != rctx->force_blend_disable) {
1165                 rctx->force_blend_disable = blend_disable;
1166                 r600_bind_blend_state_internal(rctx,
1167                                                rctx->blend_state.cso,
1168                                                blend_disable);
1169         }
1170         return true;
1171 }
1172
1173 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
1174 {
1175         static const int prim_conv[] = {
1176                 V_028A6C_OUTPRIM_TYPE_POINTLIST,
1177                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1178                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1179                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1180                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1181                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1182                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1183                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1184                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1185                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1186                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1187                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
1188                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1189                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
1190                 V_028A6C_OUTPRIM_TYPE_TRISTRIP
1191         };
1192         assert(mode < Elements(prim_conv));
1193
1194         return prim_conv[mode];
1195 }
1196
1197 void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1198 {
1199         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1200         struct r600_clip_misc_state *state = &rctx->clip_misc_state;
1201
1202         r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
1203                                state->pa_cl_clip_cntl |
1204                                (state->clip_dist_write ? 0 : state->clip_plane_enable & 0x3F));
1205         r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
1206                                state->pa_cl_vs_out_cntl |
1207                                (state->clip_plane_enable & state->clip_dist_write));
1208 }
1209
1210 static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
1211 {
1212         struct r600_context *rctx = (struct r600_context *)ctx;
1213         struct pipe_draw_info info = *dinfo;
1214         struct pipe_index_buffer ib = {};
1215         unsigned i;
1216         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1217
1218         if (!info.count && (info.indexed || !info.count_from_stream_output)) {
1219                 assert(0);
1220                 return;
1221         }
1222
1223         if (!rctx->vs_shader) {
1224                 assert(0);
1225                 return;
1226         }
1227
1228         /* make sure that the gfx ring is only one active */
1229         if (rctx->b.rings.dma.cs) {
1230                 rctx->b.rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
1231         }
1232
1233         if (!r600_update_derived_state(rctx)) {
1234                 /* useless to render because current rendering command
1235                  * can't be achieved
1236                  */
1237                 return;
1238         }
1239
1240         if (info.indexed) {
1241                 /* Initialize the index buffer struct. */
1242                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1243                 ib.user_buffer = rctx->index_buffer.user_buffer;
1244                 ib.index_size = rctx->index_buffer.index_size;
1245                 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1246
1247                 /* Translate 8-bit indices to 16-bit. */
1248                 if (ib.index_size == 1) {
1249                         struct pipe_resource *out_buffer = NULL;
1250                         unsigned out_offset;
1251                         void *ptr;
1252
1253                         u_upload_alloc(rctx->uploader, 0, info.count * 2,
1254                                        &out_offset, &out_buffer, &ptr);
1255
1256                         util_shorten_ubyte_elts_to_userptr(
1257                                                 &rctx->b.b, &ib, 0, ib.offset, info.count, ptr);
1258
1259                         pipe_resource_reference(&ib.buffer, NULL);
1260                         ib.user_buffer = NULL;
1261                         ib.buffer = out_buffer;
1262                         ib.offset = out_offset;
1263                         ib.index_size = 2;
1264                 }
1265
1266                 /* Upload the index buffer.
1267                  * The upload is skipped for small index counts on little-endian machines
1268                  * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1269                  * Note: Instanced rendering in combination with immediate indices hangs. */
1270                 if (ib.user_buffer && (R600_BIG_ENDIAN || info.instance_count > 1 ||
1271                                        info.count*ib.index_size > 20)) {
1272                         u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1273                                       ib.user_buffer, &ib.offset, &ib.buffer);
1274                         ib.user_buffer = NULL;
1275                 }
1276         } else {
1277                 info.index_bias = info.start;
1278         }
1279
1280         /* Set the index offset and primitive restart. */
1281         if (rctx->vgt_state.vgt_multi_prim_ib_reset_en != info.primitive_restart ||
1282             rctx->vgt_state.vgt_multi_prim_ib_reset_indx != info.restart_index ||
1283             rctx->vgt_state.vgt_indx_offset != info.index_bias) {
1284                 rctx->vgt_state.vgt_multi_prim_ib_reset_en = info.primitive_restart;
1285                 rctx->vgt_state.vgt_multi_prim_ib_reset_indx = info.restart_index;
1286                 rctx->vgt_state.vgt_indx_offset = info.index_bias;
1287                 rctx->vgt_state.atom.dirty = true;
1288         }
1289
1290         /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1291         if (rctx->b.chip_class == R600) {
1292                 rctx->b.flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
1293                 rctx->cb_misc_state.atom.dirty = true;
1294         }
1295
1296         /* Emit states. */
1297         r600_need_cs_space(rctx, ib.user_buffer ? 5 : 0, TRUE);
1298         r600_flush_emit(rctx);
1299
1300         for (i = 0; i < R600_NUM_ATOMS; i++) {
1301                 if (rctx->atoms[i] == NULL || !rctx->atoms[i]->dirty) {
1302                         continue;
1303                 }
1304                 r600_emit_atom(rctx, rctx->atoms[i]);
1305         }
1306
1307         /* Update start instance. */
1308         if (rctx->last_start_instance != info.start_instance) {
1309                 r600_write_ctl_const(cs, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1310                 rctx->last_start_instance = info.start_instance;
1311         }
1312
1313         /* Update the primitive type. */
1314         if (rctx->last_primitive_type != info.mode) {
1315                 unsigned ls_mask = 0;
1316
1317                 if (info.mode == PIPE_PRIM_LINES)
1318                         ls_mask = 1;
1319                 else if (info.mode == PIPE_PRIM_LINE_STRIP ||
1320                          info.mode == PIPE_PRIM_LINE_LOOP)
1321                         ls_mask = 2;
1322
1323                 r600_write_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
1324                                        S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1325                                        (rctx->rasterizer ? rctx->rasterizer->pa_sc_line_stipple : 0));
1326                 r600_write_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
1327                                        r600_conv_prim_to_gs_out(info.mode));
1328                 r600_write_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE,
1329                                       r600_conv_pipe_prim(info.mode));
1330
1331                 rctx->last_primitive_type = info.mode;
1332         }
1333
1334         /* Draw packets. */
1335         cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1336         cs->buf[cs->cdw++] = info.instance_count;
1337         if (info.indexed) {
1338                 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1339                 cs->buf[cs->cdw++] = ib.index_size == 4 ?
1340                                         (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1341                                         (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1342
1343                 if (ib.user_buffer) {
1344                         unsigned size_bytes = info.count*ib.index_size;
1345                         unsigned size_dw = align(size_bytes, 4) / 4;
1346                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_IMMD, 1 + size_dw, rctx->predicate_drawing);
1347                         cs->buf[cs->cdw++] = info.count;
1348                         cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_IMMEDIATE;
1349                         memcpy(cs->buf+cs->cdw, ib.user_buffer, size_bytes);
1350                         cs->cdw += size_dw;
1351                 } else {
1352                         uint64_t va = r600_resource_va(ctx->screen, ib.buffer) + ib.offset;
1353                         cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1354                         cs->buf[cs->cdw++] = va;
1355                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1356                         cs->buf[cs->cdw++] = info.count;
1357                         cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1358                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1359                         cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1360                 }
1361         } else {
1362                 if (info.count_from_stream_output) {
1363                         struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output;
1364                         uint64_t va = r600_resource_va(&rctx->screen->b.b, (void*)t->buf_filled_size) + t->buf_filled_size_offset;
1365
1366                         r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw);
1367
1368                         cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0);
1369                         cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG;
1370                         cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL;     /* src address lo */
1371                         cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */
1372                         cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */
1373                         cs->buf[cs->cdw++] = 0; /* unused */
1374
1375                         cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0);
1376                         cs->buf[cs->cdw++] = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, t->buf_filled_size, RADEON_USAGE_READ);
1377                 }
1378
1379                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1380                 cs->buf[cs->cdw++] = info.count;
1381                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1382                                         (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1383         }
1384
1385         if (rctx->screen->trace_bo) {
1386                 r600_trace_emit(rctx);
1387         }
1388
1389         /* Set the depth buffer as dirty. */
1390         if (rctx->framebuffer.state.zsbuf) {
1391                 struct pipe_surface *surf = rctx->framebuffer.state.zsbuf;
1392                 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1393
1394                 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1395         }
1396         if (rctx->framebuffer.compressed_cb_mask) {
1397                 struct pipe_surface *surf;
1398                 struct r600_texture *rtex;
1399                 unsigned mask = rctx->framebuffer.compressed_cb_mask;
1400
1401                 do {
1402                         unsigned i = u_bit_scan(&mask);
1403                         surf = rctx->framebuffer.state.cbufs[i];
1404                         rtex = (struct r600_texture*)surf->texture;
1405
1406                         rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1407
1408                 } while (mask);
1409         }
1410
1411         pipe_resource_reference(&ib.buffer, NULL);
1412         rctx->num_draw_calls++;
1413 }
1414
1415 void r600_draw_rectangle(struct blitter_context *blitter,
1416                          int x1, int y1, int x2, int y2, float depth,
1417                          enum blitter_attrib_type type, const union pipe_color_union *attrib)
1418 {
1419         struct r600_context *rctx = (struct r600_context*)util_blitter_get_pipe(blitter);
1420         struct pipe_viewport_state viewport;
1421         struct pipe_resource *buf = NULL;
1422         unsigned offset = 0;
1423         float *vb;
1424
1425         if (type == UTIL_BLITTER_ATTRIB_TEXCOORD) {
1426                 util_blitter_draw_rectangle(blitter, x1, y1, x2, y2, depth, type, attrib);
1427                 return;
1428         }
1429
1430         /* Some operations (like color resolve on r6xx) don't work
1431          * with the conventional primitive types.
1432          * One that works is PT_RECTLIST, which we use here. */
1433
1434         /* setup viewport */
1435         viewport.scale[0] = 1.0f;
1436         viewport.scale[1] = 1.0f;
1437         viewport.scale[2] = 1.0f;
1438         viewport.scale[3] = 1.0f;
1439         viewport.translate[0] = 0.0f;
1440         viewport.translate[1] = 0.0f;
1441         viewport.translate[2] = 0.0f;
1442         viewport.translate[3] = 0.0f;
1443         rctx->b.b.set_viewport_states(&rctx->b.b, 0, 1, &viewport);
1444
1445         /* Upload vertices. The hw rectangle has only 3 vertices,
1446          * I guess the 4th one is derived from the first 3.
1447          * The vertex specification should match u_blitter's vertex element state. */
1448         u_upload_alloc(rctx->uploader, 0, sizeof(float) * 24, &offset, &buf, (void**)&vb);
1449         vb[0] = x1;
1450         vb[1] = y1;
1451         vb[2] = depth;
1452         vb[3] = 1;
1453
1454         vb[8] = x1;
1455         vb[9] = y2;
1456         vb[10] = depth;
1457         vb[11] = 1;
1458
1459         vb[16] = x2;
1460         vb[17] = y1;
1461         vb[18] = depth;
1462         vb[19] = 1;
1463
1464         if (attrib) {
1465                 memcpy(vb+4, attrib->f, sizeof(float)*4);
1466                 memcpy(vb+12, attrib->f, sizeof(float)*4);
1467                 memcpy(vb+20, attrib->f, sizeof(float)*4);
1468         }
1469
1470         /* draw */
1471         util_draw_vertex_buffer(&rctx->b.b, NULL, buf, rctx->blitter->vb_slot, offset,
1472                                 R600_PRIM_RECTANGLE_LIST, 3, 2);
1473         pipe_resource_reference(&buf, NULL);
1474 }
1475
1476 uint32_t r600_translate_stencil_op(int s_op)
1477 {
1478         switch (s_op) {
1479         case PIPE_STENCIL_OP_KEEP:
1480                 return V_028800_STENCIL_KEEP;
1481         case PIPE_STENCIL_OP_ZERO:
1482                 return V_028800_STENCIL_ZERO;
1483         case PIPE_STENCIL_OP_REPLACE:
1484                 return V_028800_STENCIL_REPLACE;
1485         case PIPE_STENCIL_OP_INCR:
1486                 return V_028800_STENCIL_INCR;
1487         case PIPE_STENCIL_OP_DECR:
1488                 return V_028800_STENCIL_DECR;
1489         case PIPE_STENCIL_OP_INCR_WRAP:
1490                 return V_028800_STENCIL_INCR_WRAP;
1491         case PIPE_STENCIL_OP_DECR_WRAP:
1492                 return V_028800_STENCIL_DECR_WRAP;
1493         case PIPE_STENCIL_OP_INVERT:
1494                 return V_028800_STENCIL_INVERT;
1495         default:
1496                 R600_ERR("Unknown stencil op %d", s_op);
1497                 assert(0);
1498                 break;
1499         }
1500         return 0;
1501 }
1502
1503 uint32_t r600_translate_fill(uint32_t func)
1504 {
1505         switch(func) {
1506         case PIPE_POLYGON_MODE_FILL:
1507                 return 2;
1508         case PIPE_POLYGON_MODE_LINE:
1509                 return 1;
1510         case PIPE_POLYGON_MODE_POINT:
1511                 return 0;
1512         default:
1513                 assert(0);
1514                 return 0;
1515         }
1516 }
1517
1518 unsigned r600_tex_wrap(unsigned wrap)
1519 {
1520         switch (wrap) {
1521         default:
1522         case PIPE_TEX_WRAP_REPEAT:
1523                 return V_03C000_SQ_TEX_WRAP;
1524         case PIPE_TEX_WRAP_CLAMP:
1525                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1526         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1527                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1528         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1529                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1530         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1531                 return V_03C000_SQ_TEX_MIRROR;
1532         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1533                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1534         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1535                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1536         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1537                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1538         }
1539 }
1540
1541 unsigned r600_tex_filter(unsigned filter)
1542 {
1543         switch (filter) {
1544         default:
1545         case PIPE_TEX_FILTER_NEAREST:
1546                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1547         case PIPE_TEX_FILTER_LINEAR:
1548                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1549         }
1550 }
1551
1552 unsigned r600_tex_mipfilter(unsigned filter)
1553 {
1554         switch (filter) {
1555         case PIPE_TEX_MIPFILTER_NEAREST:
1556                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1557         case PIPE_TEX_MIPFILTER_LINEAR:
1558                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1559         default:
1560         case PIPE_TEX_MIPFILTER_NONE:
1561                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1562         }
1563 }
1564
1565 unsigned r600_tex_compare(unsigned compare)
1566 {
1567         switch (compare) {
1568         default:
1569         case PIPE_FUNC_NEVER:
1570                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1571         case PIPE_FUNC_LESS:
1572                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1573         case PIPE_FUNC_EQUAL:
1574                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1575         case PIPE_FUNC_LEQUAL:
1576                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1577         case PIPE_FUNC_GREATER:
1578                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1579         case PIPE_FUNC_NOTEQUAL:
1580                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1581         case PIPE_FUNC_GEQUAL:
1582                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1583         case PIPE_FUNC_ALWAYS:
1584                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1585         }
1586 }
1587
1588 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
1589 {
1590         return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
1591                wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
1592                (linear_filter &&
1593                 (wrap == PIPE_TEX_WRAP_CLAMP ||
1594                  wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
1595 }
1596
1597 bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
1598 {
1599         bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
1600                              state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
1601
1602         return (state->border_color.ui[0] || state->border_color.ui[1] ||
1603                 state->border_color.ui[2] || state->border_color.ui[3]) &&
1604                (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
1605                 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
1606                 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
1607 }
1608
1609 void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a)
1610 {
1611         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
1612         struct r600_pipe_shader *shader = ((struct r600_shader_state*)a)->shader->current;
1613
1614         r600_emit_command_buffer(cs, &shader->command_buffer);
1615
1616         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1617         radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, shader->bo, RADEON_USAGE_READ));
1618 }
1619
1620 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1621                                                 struct pipe_resource *texture,
1622                                                 const struct pipe_surface *templ,
1623                                                 unsigned width, unsigned height)
1624 {
1625         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1626
1627         assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1628         assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1629         assert(templ->u.tex.first_layer == templ->u.tex.last_layer);
1630         if (surface == NULL)
1631                 return NULL;
1632         pipe_reference_init(&surface->base.reference, 1);
1633         pipe_resource_reference(&surface->base.texture, texture);
1634         surface->base.context = pipe;
1635         surface->base.format = templ->format;
1636         surface->base.width = width;
1637         surface->base.height = height;
1638         surface->base.u = templ->u;
1639         return &surface->base;
1640 }
1641
1642 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1643                                                 struct pipe_resource *tex,
1644                                                 const struct pipe_surface *templ)
1645 {
1646         unsigned level = templ->u.tex.level;
1647
1648         return r600_create_surface_custom(pipe, tex, templ,
1649                                           u_minify(tex->width0, level),
1650                                           u_minify(tex->height0, level));
1651 }
1652
1653 static void r600_surface_destroy(struct pipe_context *pipe,
1654                                  struct pipe_surface *surface)
1655 {
1656         struct r600_surface *surf = (struct r600_surface*)surface;
1657         pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, NULL);
1658         pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, NULL);
1659         pipe_resource_reference(&surface->texture, NULL);
1660         FREE(surface);
1661 }
1662
1663 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
1664                                    const unsigned char *swizzle_view,
1665                                    boolean vtx)
1666 {
1667         unsigned i;
1668         unsigned char swizzle[4];
1669         unsigned result = 0;
1670         const uint32_t tex_swizzle_shift[4] = {
1671                 16, 19, 22, 25,
1672         };
1673         const uint32_t vtx_swizzle_shift[4] = {
1674                 3, 6, 9, 12,
1675         };
1676         const uint32_t swizzle_bit[4] = {
1677                 0, 1, 2, 3,
1678         };
1679         const uint32_t *swizzle_shift = tex_swizzle_shift;
1680
1681         if (vtx)
1682                 swizzle_shift = vtx_swizzle_shift;
1683
1684         if (swizzle_view) {
1685                 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
1686         } else {
1687                 memcpy(swizzle, swizzle_format, 4);
1688         }
1689
1690         /* Get swizzle. */
1691         for (i = 0; i < 4; i++) {
1692                 switch (swizzle[i]) {
1693                 case UTIL_FORMAT_SWIZZLE_Y:
1694                         result |= swizzle_bit[1] << swizzle_shift[i];
1695                         break;
1696                 case UTIL_FORMAT_SWIZZLE_Z:
1697                         result |= swizzle_bit[2] << swizzle_shift[i];
1698                         break;
1699                 case UTIL_FORMAT_SWIZZLE_W:
1700                         result |= swizzle_bit[3] << swizzle_shift[i];
1701                         break;
1702                 case UTIL_FORMAT_SWIZZLE_0:
1703                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
1704                         break;
1705                 case UTIL_FORMAT_SWIZZLE_1:
1706                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
1707                         break;
1708                 default: /* UTIL_FORMAT_SWIZZLE_X */
1709                         result |= swizzle_bit[0] << swizzle_shift[i];
1710                 }
1711         }
1712         return result;
1713 }
1714
1715 /* texture format translate */
1716 uint32_t r600_translate_texformat(struct pipe_screen *screen,
1717                                   enum pipe_format format,
1718                                   const unsigned char *swizzle_view,
1719                                   uint32_t *word4_p, uint32_t *yuv_format_p)
1720 {
1721         struct r600_screen *rscreen = (struct r600_screen *)screen;
1722         uint32_t result = 0, word4 = 0, yuv_format = 0;
1723         const struct util_format_description *desc;
1724         boolean uniform = TRUE;
1725         bool enable_s3tc = rscreen->b.info.drm_minor >= 9;
1726         bool is_srgb_valid = FALSE;
1727         const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
1728         const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
1729
1730         int i;
1731         const uint32_t sign_bit[4] = {
1732                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
1733                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
1734                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
1735                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
1736         };
1737         desc = util_format_description(format);
1738
1739         /* Depth and stencil swizzling is handled separately. */
1740         if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) {
1741                 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
1742         }
1743
1744         /* Colorspace (return non-RGB formats directly). */
1745         switch (desc->colorspace) {
1746         /* Depth stencil formats */
1747         case UTIL_FORMAT_COLORSPACE_ZS:
1748                 switch (format) {
1749                 /* Depth sampler formats. */
1750                 case PIPE_FORMAT_Z16_UNORM:
1751                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1752                         result = FMT_16;
1753                         goto out_word4;
1754                 case PIPE_FORMAT_Z24X8_UNORM:
1755                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1756                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1757                         result = FMT_8_24;
1758                         goto out_word4;
1759                 case PIPE_FORMAT_X8Z24_UNORM:
1760                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1761                         if (rscreen->b.chip_class < EVERGREEN)
1762                                 goto out_unknown;
1763                         word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1764                         result = FMT_24_8;
1765                         goto out_word4;
1766                 case PIPE_FORMAT_Z32_FLOAT:
1767                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1768                         result = FMT_32_FLOAT;
1769                         goto out_word4;
1770                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1771                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1772                         result = FMT_X24_8_32_FLOAT;
1773                         goto out_word4;
1774                 /* Stencil sampler formats. */
1775                 case PIPE_FORMAT_S8_UINT:
1776                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1777                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1778                         result = FMT_8;
1779                         goto out_word4;
1780                 case PIPE_FORMAT_X24S8_UINT:
1781                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1782                         word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1783                         result = FMT_8_24;
1784                         goto out_word4;
1785                 case PIPE_FORMAT_S8X24_UINT:
1786                         if (rscreen->b.chip_class < EVERGREEN)
1787                                 goto out_unknown;
1788                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1789                         word4 |= r600_get_swizzle_combined(swizzle_xxxx, swizzle_view, FALSE);
1790                         result = FMT_24_8;
1791                         goto out_word4;
1792                 case PIPE_FORMAT_X32_S8X24_UINT:
1793                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1794                         word4 |= r600_get_swizzle_combined(swizzle_yyyy, swizzle_view, FALSE);
1795                         result = FMT_X24_8_32_FLOAT;
1796                         goto out_word4;
1797                 default:
1798                         goto out_unknown;
1799                 }
1800
1801         case UTIL_FORMAT_COLORSPACE_YUV:
1802                 yuv_format |= (1 << 30);
1803                 switch (format) {
1804                 case PIPE_FORMAT_UYVY:
1805                 case PIPE_FORMAT_YUYV:
1806                 default:
1807                         break;
1808                 }
1809                 goto out_unknown; /* XXX */
1810
1811         case UTIL_FORMAT_COLORSPACE_SRGB:
1812                 word4 |= S_038010_FORCE_DEGAMMA(1);
1813                 break;
1814
1815         default:
1816                 break;
1817         }
1818
1819         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1820                 if (!enable_s3tc)
1821                         goto out_unknown;
1822
1823                 switch (format) {
1824                 case PIPE_FORMAT_RGTC1_SNORM:
1825                 case PIPE_FORMAT_LATC1_SNORM:
1826                         word4 |= sign_bit[0];
1827                 case PIPE_FORMAT_RGTC1_UNORM:
1828                 case PIPE_FORMAT_LATC1_UNORM:
1829                         result = FMT_BC4;
1830                         goto out_word4;
1831                 case PIPE_FORMAT_RGTC2_SNORM:
1832                 case PIPE_FORMAT_LATC2_SNORM:
1833                         word4 |= sign_bit[0] | sign_bit[1];
1834                 case PIPE_FORMAT_RGTC2_UNORM:
1835                 case PIPE_FORMAT_LATC2_UNORM:
1836                         result = FMT_BC5;
1837                         goto out_word4;
1838                 default:
1839                         goto out_unknown;
1840                 }
1841         }
1842
1843         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1844
1845                 if (!enable_s3tc)
1846                         goto out_unknown;
1847
1848                 if (!util_format_s3tc_enabled) {
1849                         goto out_unknown;
1850                 }
1851
1852                 switch (format) {
1853                 case PIPE_FORMAT_DXT1_RGB:
1854                 case PIPE_FORMAT_DXT1_RGBA:
1855                 case PIPE_FORMAT_DXT1_SRGB:
1856                 case PIPE_FORMAT_DXT1_SRGBA:
1857                         result = FMT_BC1;
1858                         is_srgb_valid = TRUE;
1859                         goto out_word4;
1860                 case PIPE_FORMAT_DXT3_RGBA:
1861                 case PIPE_FORMAT_DXT3_SRGBA:
1862                         result = FMT_BC2;
1863                         is_srgb_valid = TRUE;
1864                         goto out_word4;
1865                 case PIPE_FORMAT_DXT5_RGBA:
1866                 case PIPE_FORMAT_DXT5_SRGBA:
1867                         result = FMT_BC3;
1868                         is_srgb_valid = TRUE;
1869                         goto out_word4;
1870                 default:
1871                         goto out_unknown;
1872                 }
1873         }
1874
1875         if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1876                 switch (format) {
1877                 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1878                 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1879                         result = FMT_GB_GR;
1880                         goto out_word4;
1881                 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1882                 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1883                         result = FMT_BG_RG;
1884                         goto out_word4;
1885                 default:
1886                         goto out_unknown;
1887                 }
1888         }
1889
1890         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1891                 result = FMT_5_9_9_9_SHAREDEXP;
1892                 goto out_word4;
1893         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1894                 result = FMT_10_11_11_FLOAT;
1895                 goto out_word4;
1896         }
1897
1898
1899         for (i = 0; i < desc->nr_channels; i++) {
1900                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1901                         word4 |= sign_bit[i];
1902                 }
1903         }
1904
1905         /* R8G8Bx_SNORM - XXX CxV8U8 */
1906
1907         /* See whether the components are of the same size. */
1908         for (i = 1; i < desc->nr_channels; i++) {
1909                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1910         }
1911
1912         /* Non-uniform formats. */
1913         if (!uniform) {
1914                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1915                     desc->channel[0].pure_integer)
1916                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1917                 switch(desc->nr_channels) {
1918                 case 3:
1919                         if (desc->channel[0].size == 5 &&
1920                             desc->channel[1].size == 6 &&
1921                             desc->channel[2].size == 5) {
1922                                 result = FMT_5_6_5;
1923                                 goto out_word4;
1924                         }
1925                         goto out_unknown;
1926                 case 4:
1927                         if (desc->channel[0].size == 5 &&
1928                             desc->channel[1].size == 5 &&
1929                             desc->channel[2].size == 5 &&
1930                             desc->channel[3].size == 1) {
1931                                 result = FMT_1_5_5_5;
1932                                 goto out_word4;
1933                         }
1934                         if (desc->channel[0].size == 10 &&
1935                             desc->channel[1].size == 10 &&
1936                             desc->channel[2].size == 10 &&
1937                             desc->channel[3].size == 2) {
1938                                 result = FMT_2_10_10_10;
1939                                 goto out_word4;
1940                         }
1941                         goto out_unknown;
1942                 }
1943                 goto out_unknown;
1944         }
1945
1946         /* Find the first non-VOID channel. */
1947         for (i = 0; i < 4; i++) {
1948                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1949                         break;
1950                 }
1951         }
1952
1953         if (i == 4)
1954                 goto out_unknown;
1955
1956         /* uniform formats */
1957         switch (desc->channel[i].type) {
1958         case UTIL_FORMAT_TYPE_UNSIGNED:
1959         case UTIL_FORMAT_TYPE_SIGNED:
1960 #if 0
1961                 if (!desc->channel[i].normalized &&
1962                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1963                         goto out_unknown;
1964                 }
1965 #endif
1966                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB &&
1967                     desc->channel[i].pure_integer)
1968                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1969
1970                 switch (desc->channel[i].size) {
1971                 case 4:
1972                         switch (desc->nr_channels) {
1973                         case 2:
1974                                 result = FMT_4_4;
1975                                 goto out_word4;
1976                         case 4:
1977                                 result = FMT_4_4_4_4;
1978                                 goto out_word4;
1979                         }
1980                         goto out_unknown;
1981                 case 8:
1982                         switch (desc->nr_channels) {
1983                         case 1:
1984                                 result = FMT_8;
1985                                 goto out_word4;
1986                         case 2:
1987                                 result = FMT_8_8;
1988                                 goto out_word4;
1989                         case 4:
1990                                 result = FMT_8_8_8_8;
1991                                 is_srgb_valid = TRUE;
1992                                 goto out_word4;
1993                         }
1994                         goto out_unknown;
1995                 case 16:
1996                         switch (desc->nr_channels) {
1997                         case 1:
1998                                 result = FMT_16;
1999                                 goto out_word4;
2000                         case 2:
2001                                 result = FMT_16_16;
2002                                 goto out_word4;
2003                         case 4:
2004                                 result = FMT_16_16_16_16;
2005                                 goto out_word4;
2006                         }
2007                         goto out_unknown;
2008                 case 32:
2009                         switch (desc->nr_channels) {
2010                         case 1:
2011                                 result = FMT_32;
2012                                 goto out_word4;
2013                         case 2:
2014                                 result = FMT_32_32;
2015                                 goto out_word4;
2016                         case 4:
2017                                 result = FMT_32_32_32_32;
2018                                 goto out_word4;
2019                         }
2020                 }
2021                 goto out_unknown;
2022
2023         case UTIL_FORMAT_TYPE_FLOAT:
2024                 switch (desc->channel[i].size) {
2025                 case 16:
2026                         switch (desc->nr_channels) {
2027                         case 1:
2028                                 result = FMT_16_FLOAT;
2029                                 goto out_word4;
2030                         case 2:
2031                                 result = FMT_16_16_FLOAT;
2032                                 goto out_word4;
2033                         case 4:
2034                                 result = FMT_16_16_16_16_FLOAT;
2035                                 goto out_word4;
2036                         }
2037                         goto out_unknown;
2038                 case 32:
2039                         switch (desc->nr_channels) {
2040                         case 1:
2041                                 result = FMT_32_FLOAT;
2042                                 goto out_word4;
2043                         case 2:
2044                                 result = FMT_32_32_FLOAT;
2045                                 goto out_word4;
2046                         case 4:
2047                                 result = FMT_32_32_32_32_FLOAT;
2048                                 goto out_word4;
2049                         }
2050                 }
2051                 goto out_unknown;
2052         }
2053
2054 out_word4:
2055
2056         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid)
2057                 return ~0;
2058         if (word4_p)
2059                 *word4_p = word4;
2060         if (yuv_format_p)
2061                 *yuv_format_p = yuv_format;
2062         return result;
2063 out_unknown:
2064         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2065         return ~0;
2066 }
2067
2068 /* keep this at the end of this file, please */
2069 void r600_init_common_state_functions(struct r600_context *rctx)
2070 {
2071         rctx->b.b.create_fs_state = r600_create_ps_state;
2072         rctx->b.b.create_vs_state = r600_create_vs_state;
2073         rctx->b.b.create_vertex_elements_state = r600_create_vertex_fetch_shader;
2074         rctx->b.b.bind_blend_state = r600_bind_blend_state;
2075         rctx->b.b.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2076         rctx->b.b.bind_sampler_states = r600_bind_sampler_states;
2077         rctx->b.b.bind_fs_state = r600_bind_ps_state;
2078         rctx->b.b.bind_rasterizer_state = r600_bind_rs_state;
2079         rctx->b.b.bind_vertex_elements_state = r600_bind_vertex_elements;
2080         rctx->b.b.bind_vs_state = r600_bind_vs_state;
2081         rctx->b.b.delete_blend_state = r600_delete_blend_state;
2082         rctx->b.b.delete_depth_stencil_alpha_state = r600_delete_dsa_state;
2083         rctx->b.b.delete_fs_state = r600_delete_ps_state;
2084         rctx->b.b.delete_rasterizer_state = r600_delete_rs_state;
2085         rctx->b.b.delete_sampler_state = r600_delete_sampler_state;
2086         rctx->b.b.delete_vertex_elements_state = r600_delete_vertex_elements;
2087         rctx->b.b.delete_vs_state = r600_delete_vs_state;
2088         rctx->b.b.set_blend_color = r600_set_blend_color;
2089         rctx->b.b.set_clip_state = r600_set_clip_state;
2090         rctx->b.b.set_constant_buffer = r600_set_constant_buffer;
2091         rctx->b.b.set_sample_mask = r600_set_sample_mask;
2092         rctx->b.b.set_stencil_ref = r600_set_pipe_stencil_ref;
2093         rctx->b.b.set_viewport_states = r600_set_viewport_states;
2094         rctx->b.b.set_vertex_buffers = r600_set_vertex_buffers;
2095         rctx->b.b.set_index_buffer = r600_set_index_buffer;
2096         rctx->b.b.set_sampler_views = r600_set_sampler_views;
2097         rctx->b.b.sampler_view_destroy = r600_sampler_view_destroy;
2098         rctx->b.b.texture_barrier = r600_texture_barrier;
2099         rctx->b.b.set_stream_output_targets = r600_set_streamout_targets;
2100         rctx->b.b.create_surface = r600_create_surface;
2101         rctx->b.b.surface_destroy = r600_surface_destroy;
2102         rctx->b.b.draw_vbo = r600_draw_vbo;
2103 }
2104
2105 void r600_trace_emit(struct r600_context *rctx)
2106 {
2107         struct r600_screen *rscreen = rctx->screen;
2108         struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
2109         uint64_t va;
2110         uint32_t reloc;
2111
2112         va = r600_resource_va(&rscreen->b.b, (void*)rscreen->trace_bo);
2113         reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, rscreen->trace_bo, RADEON_USAGE_READWRITE);
2114         radeon_emit(cs, PKT3(PKT3_MEM_WRITE, 3, 0));
2115         radeon_emit(cs, va & 0xFFFFFFFFUL);
2116         radeon_emit(cs, (va >> 32UL) & 0xFFUL);
2117         radeon_emit(cs, cs->cdw);
2118         radeon_emit(cs, rscreen->cs_count);
2119         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2120         radeon_emit(cs, reloc);
2121 }