2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include "r600_formats.h"
28 #include "r600_shader.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_index_modify.h"
33 #include "util/u_memory.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_math.h"
36 #include "tgsi/tgsi_parse.h"
38 void r600_init_command_buffer(struct r600_command_buffer
*cb
, unsigned num_dw
)
41 cb
->buf
= CALLOC(1, 4 * num_dw
);
42 cb
->max_num_dw
= num_dw
;
45 void r600_release_command_buffer(struct r600_command_buffer
*cb
)
50 void r600_init_atom(struct r600_context
*rctx
,
51 struct r600_atom
*atom
,
53 void (*emit
)(struct r600_context
*ctx
, struct r600_atom
*state
),
56 assert(id
< R600_NUM_ATOMS
);
57 assert(rctx
->atoms
[id
] == NULL
);
58 rctx
->atoms
[id
] = atom
;
59 atom
->emit
= (void*)emit
;
60 atom
->num_dw
= num_dw
;
64 void r600_emit_cso_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
66 r600_emit_command_buffer(rctx
->b
.rings
.gfx
.cs
, ((struct r600_cso_state
*)atom
)->cb
);
69 void r600_emit_alphatest_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
71 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
72 struct r600_alphatest_state
*a
= (struct r600_alphatest_state
*)atom
;
73 unsigned alpha_ref
= a
->sx_alpha_ref
;
75 if (rctx
->b
.chip_class
>= EVERGREEN
&& a
->cb0_export_16bpc
) {
79 r600_write_context_reg(cs
, R_028410_SX_ALPHA_TEST_CONTROL
,
80 a
->sx_alpha_test_control
|
81 S_028410_ALPHA_TEST_BYPASS(a
->bypass
));
82 r600_write_context_reg(cs
, R_028438_SX_ALPHA_REF
, alpha_ref
);
85 static void r600_texture_barrier(struct pipe_context
*ctx
)
87 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
89 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
90 R600_CONTEXT_FLUSH_AND_INV_CB
|
91 R600_CONTEXT_FLUSH_AND_INV
|
92 R600_CONTEXT_WAIT_3D_IDLE
;
95 static unsigned r600_conv_pipe_prim(unsigned prim
)
97 static const unsigned prim_conv
[] = {
98 V_008958_DI_PT_POINTLIST
,
99 V_008958_DI_PT_LINELIST
,
100 V_008958_DI_PT_LINELOOP
,
101 V_008958_DI_PT_LINESTRIP
,
102 V_008958_DI_PT_TRILIST
,
103 V_008958_DI_PT_TRISTRIP
,
104 V_008958_DI_PT_TRIFAN
,
105 V_008958_DI_PT_QUADLIST
,
106 V_008958_DI_PT_QUADSTRIP
,
107 V_008958_DI_PT_POLYGON
,
108 V_008958_DI_PT_LINELIST_ADJ
,
109 V_008958_DI_PT_LINESTRIP_ADJ
,
110 V_008958_DI_PT_TRILIST_ADJ
,
111 V_008958_DI_PT_TRISTRIP_ADJ
,
112 V_008958_DI_PT_RECTLIST
114 return prim_conv
[prim
];
117 /* common state between evergreen and r600 */
119 static void r600_bind_blend_state_internal(struct r600_context
*rctx
,
120 struct r600_blend_state
*blend
, bool blend_disable
)
122 unsigned color_control
;
123 bool update_cb
= false;
125 rctx
->alpha_to_one
= blend
->alpha_to_one
;
126 rctx
->dual_src_blend
= blend
->dual_src_blend
;
128 if (!blend_disable
) {
129 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer
);
130 color_control
= blend
->cb_color_control
;
132 /* Blending is disabled. */
133 r600_set_cso_state_with_cb(&rctx
->blend_state
, blend
, &blend
->buffer_no_blend
);
134 color_control
= blend
->cb_color_control_no_blend
;
137 /* Update derived states. */
138 if (rctx
->cb_misc_state
.blend_colormask
!= blend
->cb_target_mask
) {
139 rctx
->cb_misc_state
.blend_colormask
= blend
->cb_target_mask
;
142 if (rctx
->b
.chip_class
<= R700
&&
143 rctx
->cb_misc_state
.cb_color_control
!= color_control
) {
144 rctx
->cb_misc_state
.cb_color_control
= color_control
;
147 if (rctx
->cb_misc_state
.dual_src_blend
!= blend
->dual_src_blend
) {
148 rctx
->cb_misc_state
.dual_src_blend
= blend
->dual_src_blend
;
152 rctx
->cb_misc_state
.atom
.dirty
= true;
156 static void r600_bind_blend_state(struct pipe_context
*ctx
, void *state
)
158 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
159 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
162 r600_set_cso_state_with_cb(&rctx
->blend_state
, NULL
, NULL
);
166 r600_bind_blend_state_internal(rctx
, blend
, rctx
->force_blend_disable
);
169 static void r600_set_blend_color(struct pipe_context
*ctx
,
170 const struct pipe_blend_color
*state
)
172 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
174 rctx
->blend_color
.state
= *state
;
175 rctx
->blend_color
.atom
.dirty
= true;
178 void r600_emit_blend_color(struct r600_context
*rctx
, struct r600_atom
*atom
)
180 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
181 struct pipe_blend_color
*state
= &rctx
->blend_color
.state
;
183 r600_write_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
184 radeon_emit(cs
, fui(state
->color
[0])); /* R_028414_CB_BLEND_RED */
185 radeon_emit(cs
, fui(state
->color
[1])); /* R_028418_CB_BLEND_GREEN */
186 radeon_emit(cs
, fui(state
->color
[2])); /* R_02841C_CB_BLEND_BLUE */
187 radeon_emit(cs
, fui(state
->color
[3])); /* R_028420_CB_BLEND_ALPHA */
190 void r600_emit_vgt_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
192 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
193 struct r600_vgt_state
*a
= (struct r600_vgt_state
*)atom
;
195 r600_write_context_reg(cs
, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN
, a
->vgt_multi_prim_ib_reset_en
);
196 r600_write_context_reg_seq(cs
, R_028408_VGT_INDX_OFFSET
, 2);
197 radeon_emit(cs
, a
->vgt_indx_offset
); /* R_028408_VGT_INDX_OFFSET */
198 radeon_emit(cs
, a
->vgt_multi_prim_ib_reset_indx
); /* R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX */
199 if (a
->last_draw_was_indirect
) {
200 a
->last_draw_was_indirect
= false;
201 r600_write_ctl_const(cs
, R_03CFF0_SQ_VTX_BASE_VTX_LOC
, 0);
205 static void r600_set_clip_state(struct pipe_context
*ctx
,
206 const struct pipe_clip_state
*state
)
208 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
209 struct pipe_constant_buffer cb
;
211 rctx
->clip_state
.state
= *state
;
212 rctx
->clip_state
.atom
.dirty
= true;
215 cb
.user_buffer
= state
->ucp
;
216 cb
.buffer_offset
= 0;
217 cb
.buffer_size
= 4*4*8;
218 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, R600_UCP_CONST_BUFFER
, &cb
);
219 pipe_resource_reference(&cb
.buffer
, NULL
);
222 static void r600_set_stencil_ref(struct pipe_context
*ctx
,
223 const struct r600_stencil_ref
*state
)
225 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
227 rctx
->stencil_ref
.state
= *state
;
228 rctx
->stencil_ref
.atom
.dirty
= true;
231 void r600_emit_stencil_ref(struct r600_context
*rctx
, struct r600_atom
*atom
)
233 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
234 struct r600_stencil_ref_state
*a
= (struct r600_stencil_ref_state
*)atom
;
236 r600_write_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
237 radeon_emit(cs
, /* R_028430_DB_STENCILREFMASK */
238 S_028430_STENCILREF(a
->state
.ref_value
[0]) |
239 S_028430_STENCILMASK(a
->state
.valuemask
[0]) |
240 S_028430_STENCILWRITEMASK(a
->state
.writemask
[0]));
241 radeon_emit(cs
, /* R_028434_DB_STENCILREFMASK_BF */
242 S_028434_STENCILREF_BF(a
->state
.ref_value
[1]) |
243 S_028434_STENCILMASK_BF(a
->state
.valuemask
[1]) |
244 S_028434_STENCILWRITEMASK_BF(a
->state
.writemask
[1]));
247 static void r600_set_pipe_stencil_ref(struct pipe_context
*ctx
,
248 const struct pipe_stencil_ref
*state
)
250 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
251 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)rctx
->dsa_state
.cso
;
252 struct r600_stencil_ref ref
;
254 rctx
->stencil_ref
.pipe_state
= *state
;
259 ref
.ref_value
[0] = state
->ref_value
[0];
260 ref
.ref_value
[1] = state
->ref_value
[1];
261 ref
.valuemask
[0] = dsa
->valuemask
[0];
262 ref
.valuemask
[1] = dsa
->valuemask
[1];
263 ref
.writemask
[0] = dsa
->writemask
[0];
264 ref
.writemask
[1] = dsa
->writemask
[1];
266 r600_set_stencil_ref(ctx
, &ref
);
269 static void r600_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
271 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
272 struct r600_dsa_state
*dsa
= state
;
273 struct r600_stencil_ref ref
;
276 r600_set_cso_state_with_cb(&rctx
->dsa_state
, NULL
, NULL
);
280 r600_set_cso_state_with_cb(&rctx
->dsa_state
, dsa
, &dsa
->buffer
);
282 ref
.ref_value
[0] = rctx
->stencil_ref
.pipe_state
.ref_value
[0];
283 ref
.ref_value
[1] = rctx
->stencil_ref
.pipe_state
.ref_value
[1];
284 ref
.valuemask
[0] = dsa
->valuemask
[0];
285 ref
.valuemask
[1] = dsa
->valuemask
[1];
286 ref
.writemask
[0] = dsa
->writemask
[0];
287 ref
.writemask
[1] = dsa
->writemask
[1];
288 if (rctx
->zwritemask
!= dsa
->zwritemask
) {
289 rctx
->zwritemask
= dsa
->zwritemask
;
290 if (rctx
->b
.chip_class
>= EVERGREEN
) {
291 /* work around some issue when not writting to zbuffer
292 * we are having lockup on evergreen so do not enable
293 * hyperz when not writting zbuffer
295 rctx
->db_misc_state
.atom
.dirty
= true;
299 r600_set_stencil_ref(ctx
, &ref
);
301 /* Update alphatest state. */
302 if (rctx
->alphatest_state
.sx_alpha_test_control
!= dsa
->sx_alpha_test_control
||
303 rctx
->alphatest_state
.sx_alpha_ref
!= dsa
->alpha_ref
) {
304 rctx
->alphatest_state
.sx_alpha_test_control
= dsa
->sx_alpha_test_control
;
305 rctx
->alphatest_state
.sx_alpha_ref
= dsa
->alpha_ref
;
306 rctx
->alphatest_state
.atom
.dirty
= true;
310 static void r600_bind_rs_state(struct pipe_context
*ctx
, void *state
)
312 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
313 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
318 rctx
->rasterizer
= rs
;
320 r600_set_cso_state_with_cb(&rctx
->rasterizer_state
, rs
, &rs
->buffer
);
322 if (rs
->offset_enable
&&
323 (rs
->offset_units
!= rctx
->poly_offset_state
.offset_units
||
324 rs
->offset_scale
!= rctx
->poly_offset_state
.offset_scale
)) {
325 rctx
->poly_offset_state
.offset_units
= rs
->offset_units
;
326 rctx
->poly_offset_state
.offset_scale
= rs
->offset_scale
;
327 rctx
->poly_offset_state
.atom
.dirty
= true;
330 /* Update clip_misc_state. */
331 if (rctx
->clip_misc_state
.pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
||
332 rctx
->clip_misc_state
.clip_plane_enable
!= rs
->clip_plane_enable
) {
333 rctx
->clip_misc_state
.pa_cl_clip_cntl
= rs
->pa_cl_clip_cntl
;
334 rctx
->clip_misc_state
.clip_plane_enable
= rs
->clip_plane_enable
;
335 rctx
->clip_misc_state
.atom
.dirty
= true;
338 /* Workaround for a missing scissor enable on r600. */
339 if (rctx
->b
.chip_class
== R600
&&
340 rs
->scissor_enable
!= rctx
->scissor
[0].enable
) {
341 rctx
->scissor
[0].enable
= rs
->scissor_enable
;
342 rctx
->scissor
[0].atom
.dirty
= true;
345 /* Re-emit PA_SC_LINE_STIPPLE. */
346 rctx
->last_primitive_type
= -1;
349 static void r600_delete_rs_state(struct pipe_context
*ctx
, void *state
)
351 struct r600_rasterizer_state
*rs
= (struct r600_rasterizer_state
*)state
;
353 r600_release_command_buffer(&rs
->buffer
);
357 static void r600_sampler_view_destroy(struct pipe_context
*ctx
,
358 struct pipe_sampler_view
*state
)
360 struct r600_pipe_sampler_view
*view
= (struct r600_pipe_sampler_view
*)state
;
362 if (view
->tex_resource
->gpu_address
&&
363 view
->tex_resource
->b
.b
.target
== PIPE_BUFFER
)
364 LIST_DELINIT(&view
->list
);
366 pipe_resource_reference(&state
->texture
, NULL
);
370 void r600_sampler_states_dirty(struct r600_context
*rctx
,
371 struct r600_sampler_states
*state
)
373 if (state
->dirty_mask
) {
374 if (state
->dirty_mask
& state
->has_bordercolor_mask
) {
375 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
378 util_bitcount(state
->dirty_mask
& state
->has_bordercolor_mask
) * 11 +
379 util_bitcount(state
->dirty_mask
& ~state
->has_bordercolor_mask
) * 5;
380 state
->atom
.dirty
= true;
384 static void r600_bind_sampler_states(struct pipe_context
*pipe
,
387 unsigned count
, void **states
)
389 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
390 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
391 struct r600_pipe_sampler_state
**rstates
= (struct r600_pipe_sampler_state
**)states
;
392 int seamless_cube_map
= -1;
394 /* This sets 1-bit for states with index >= count. */
395 uint32_t disable_mask
= ~((1ull << count
) - 1);
396 /* These are the new states set by this function. */
397 uint32_t new_mask
= 0;
399 assert(start
== 0); /* XXX fix below */
401 if (shader
!= PIPE_SHADER_VERTEX
&&
402 shader
!= PIPE_SHADER_FRAGMENT
) {
406 for (i
= 0; i
< count
; i
++) {
407 struct r600_pipe_sampler_state
*rstate
= rstates
[i
];
409 if (rstate
== dst
->states
.states
[i
]) {
414 if (rstate
->border_color_use
) {
415 dst
->states
.has_bordercolor_mask
|= 1 << i
;
417 dst
->states
.has_bordercolor_mask
&= ~(1 << i
);
419 seamless_cube_map
= rstate
->seamless_cube_map
;
423 disable_mask
|= 1 << i
;
427 memcpy(dst
->states
.states
, rstates
, sizeof(void*) * count
);
428 memset(dst
->states
.states
+ count
, 0, sizeof(void*) * (NUM_TEX_UNITS
- count
));
430 dst
->states
.enabled_mask
&= ~disable_mask
;
431 dst
->states
.dirty_mask
&= dst
->states
.enabled_mask
;
432 dst
->states
.enabled_mask
|= new_mask
;
433 dst
->states
.dirty_mask
|= new_mask
;
434 dst
->states
.has_bordercolor_mask
&= dst
->states
.enabled_mask
;
436 r600_sampler_states_dirty(rctx
, &dst
->states
);
438 /* Seamless cubemap state. */
439 if (rctx
->b
.chip_class
<= R700
&&
440 seamless_cube_map
!= -1 &&
441 seamless_cube_map
!= rctx
->seamless_cube_map
.enabled
) {
442 /* change in TA_CNTL_AUX need a pipeline flush */
443 rctx
->b
.flags
|= R600_CONTEXT_WAIT_3D_IDLE
;
444 rctx
->seamless_cube_map
.enabled
= seamless_cube_map
;
445 rctx
->seamless_cube_map
.atom
.dirty
= true;
449 static void r600_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
454 static void r600_delete_blend_state(struct pipe_context
*ctx
, void *state
)
456 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
457 struct r600_blend_state
*blend
= (struct r600_blend_state
*)state
;
459 if (rctx
->blend_state
.cso
== state
) {
460 ctx
->bind_blend_state(ctx
, NULL
);
463 r600_release_command_buffer(&blend
->buffer
);
464 r600_release_command_buffer(&blend
->buffer_no_blend
);
468 static void r600_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
470 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
471 struct r600_dsa_state
*dsa
= (struct r600_dsa_state
*)state
;
473 if (rctx
->dsa_state
.cso
== state
) {
474 ctx
->bind_depth_stencil_alpha_state(ctx
, NULL
);
477 r600_release_command_buffer(&dsa
->buffer
);
481 static void r600_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
483 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
485 r600_set_cso_state(&rctx
->vertex_fetch_shader
, state
);
488 static void r600_delete_vertex_elements(struct pipe_context
*ctx
, void *state
)
490 struct r600_fetch_shader
*shader
= (struct r600_fetch_shader
*)state
;
491 pipe_resource_reference((struct pipe_resource
**)&shader
->buffer
, NULL
);
495 static void r600_set_index_buffer(struct pipe_context
*ctx
,
496 const struct pipe_index_buffer
*ib
)
498 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
501 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
502 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
503 r600_context_add_resource_size(ctx
, ib
->buffer
);
505 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
509 void r600_vertex_buffers_dirty(struct r600_context
*rctx
)
511 if (rctx
->vertex_buffer_state
.dirty_mask
) {
512 rctx
->b
.flags
|= R600_CONTEXT_INV_VERTEX_CACHE
;
513 rctx
->vertex_buffer_state
.atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 12 : 11) *
514 util_bitcount(rctx
->vertex_buffer_state
.dirty_mask
);
515 rctx
->vertex_buffer_state
.atom
.dirty
= true;
519 static void r600_set_vertex_buffers(struct pipe_context
*ctx
,
520 unsigned start_slot
, unsigned count
,
521 const struct pipe_vertex_buffer
*input
)
523 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
524 struct r600_vertexbuf_state
*state
= &rctx
->vertex_buffer_state
;
525 struct pipe_vertex_buffer
*vb
= state
->vb
+ start_slot
;
527 uint32_t disable_mask
= 0;
528 /* These are the new buffers set by this function. */
529 uint32_t new_buffer_mask
= 0;
531 /* Set vertex buffers. */
533 for (i
= 0; i
< count
; i
++) {
534 if (memcmp(&input
[i
], &vb
[i
], sizeof(struct pipe_vertex_buffer
))) {
535 if (input
[i
].buffer
) {
536 vb
[i
].stride
= input
[i
].stride
;
537 vb
[i
].buffer_offset
= input
[i
].buffer_offset
;
538 pipe_resource_reference(&vb
[i
].buffer
, input
[i
].buffer
);
539 new_buffer_mask
|= 1 << i
;
540 r600_context_add_resource_size(ctx
, input
[i
].buffer
);
542 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
543 disable_mask
|= 1 << i
;
548 for (i
= 0; i
< count
; i
++) {
549 pipe_resource_reference(&vb
[i
].buffer
, NULL
);
551 disable_mask
= ((1ull << count
) - 1);
554 disable_mask
<<= start_slot
;
555 new_buffer_mask
<<= start_slot
;
557 rctx
->vertex_buffer_state
.enabled_mask
&= ~disable_mask
;
558 rctx
->vertex_buffer_state
.dirty_mask
&= rctx
->vertex_buffer_state
.enabled_mask
;
559 rctx
->vertex_buffer_state
.enabled_mask
|= new_buffer_mask
;
560 rctx
->vertex_buffer_state
.dirty_mask
|= new_buffer_mask
;
562 r600_vertex_buffers_dirty(rctx
);
565 void r600_sampler_views_dirty(struct r600_context
*rctx
,
566 struct r600_samplerview_state
*state
)
568 if (state
->dirty_mask
) {
569 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
570 state
->atom
.num_dw
= (rctx
->b
.chip_class
>= EVERGREEN
? 14 : 13) *
571 util_bitcount(state
->dirty_mask
);
572 state
->atom
.dirty
= true;
576 static void r600_set_sampler_views(struct pipe_context
*pipe
, unsigned shader
,
577 unsigned start
, unsigned count
,
578 struct pipe_sampler_view
**views
)
580 struct r600_context
*rctx
= (struct r600_context
*) pipe
;
581 struct r600_textures_info
*dst
= &rctx
->samplers
[shader
];
582 struct r600_pipe_sampler_view
**rviews
= (struct r600_pipe_sampler_view
**)views
;
583 uint32_t dirty_sampler_states_mask
= 0;
585 /* This sets 1-bit for textures with index >= count. */
586 uint32_t disable_mask
= ~((1ull << count
) - 1);
587 /* These are the new textures set by this function. */
588 uint32_t new_mask
= 0;
590 /* Set textures with index >= count to NULL. */
591 uint32_t remaining_mask
;
593 assert(start
== 0); /* XXX fix below */
595 if (shader
== PIPE_SHADER_COMPUTE
) {
596 evergreen_set_cs_sampler_view(pipe
, start
, count
, views
);
600 remaining_mask
= dst
->views
.enabled_mask
& disable_mask
;
602 while (remaining_mask
) {
603 i
= u_bit_scan(&remaining_mask
);
604 assert(dst
->views
.views
[i
]);
606 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
609 for (i
= 0; i
< count
; i
++) {
610 if (rviews
[i
] == dst
->views
.views
[i
]) {
615 struct r600_texture
*rtex
=
616 (struct r600_texture
*)rviews
[i
]->base
.texture
;
618 if (rviews
[i
]->base
.texture
->target
!= PIPE_BUFFER
) {
619 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
620 dst
->views
.compressed_depthtex_mask
|= 1 << i
;
622 dst
->views
.compressed_depthtex_mask
&= ~(1 << i
);
625 /* Track compressed colorbuffers. */
626 if (rtex
->cmask
.size
) {
627 dst
->views
.compressed_colortex_mask
|= 1 << i
;
629 dst
->views
.compressed_colortex_mask
&= ~(1 << i
);
632 /* Changing from array to non-arrays textures and vice versa requires
633 * updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
634 if (rctx
->b
.chip_class
<= R700
&&
635 (dst
->states
.enabled_mask
& (1 << i
)) &&
636 (rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_1D_ARRAY
||
637 rviews
[i
]->base
.texture
->target
== PIPE_TEXTURE_2D_ARRAY
) != dst
->is_array_sampler
[i
]) {
638 dirty_sampler_states_mask
|= 1 << i
;
641 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], views
[i
]);
643 r600_context_add_resource_size(pipe
, views
[i
]->texture
);
645 pipe_sampler_view_reference((struct pipe_sampler_view
**)&dst
->views
.views
[i
], NULL
);
646 disable_mask
|= 1 << i
;
650 dst
->views
.enabled_mask
&= ~disable_mask
;
651 dst
->views
.dirty_mask
&= dst
->views
.enabled_mask
;
652 dst
->views
.enabled_mask
|= new_mask
;
653 dst
->views
.dirty_mask
|= new_mask
;
654 dst
->views
.compressed_depthtex_mask
&= dst
->views
.enabled_mask
;
655 dst
->views
.compressed_colortex_mask
&= dst
->views
.enabled_mask
;
656 dst
->views
.dirty_buffer_constants
= TRUE
;
657 r600_sampler_views_dirty(rctx
, &dst
->views
);
659 if (dirty_sampler_states_mask
) {
660 dst
->states
.dirty_mask
|= dirty_sampler_states_mask
;
661 r600_sampler_states_dirty(rctx
, &dst
->states
);
665 static void r600_set_viewport_states(struct pipe_context
*ctx
,
667 unsigned num_viewports
,
668 const struct pipe_viewport_state
*state
)
670 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
673 for (i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
674 rctx
->viewport
[i
].state
= state
[i
- start_slot
];
675 rctx
->viewport
[i
].atom
.dirty
= true;
679 void r600_emit_viewport_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
681 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
682 struct r600_viewport_state
*rstate
= (struct r600_viewport_state
*)atom
;
683 struct pipe_viewport_state
*state
= &rstate
->state
;
684 int offset
= rstate
->idx
* 6 * 4;
686 r600_write_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE_0
+ offset
, 6);
687 radeon_emit(cs
, fui(state
->scale
[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
688 radeon_emit(cs
, fui(state
->translate
[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
689 radeon_emit(cs
, fui(state
->scale
[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
690 radeon_emit(cs
, fui(state
->translate
[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
691 radeon_emit(cs
, fui(state
->scale
[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
692 radeon_emit(cs
, fui(state
->translate
[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
695 /* Compute the key for the hw shader variant */
696 static INLINE
struct r600_shader_key
r600_shader_selector_key(struct pipe_context
* ctx
,
697 struct r600_pipe_shader_selector
* sel
)
699 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
700 struct r600_shader_key key
;
701 memset(&key
, 0, sizeof(key
));
703 if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
704 key
.color_two_side
= rctx
->rasterizer
&& rctx
->rasterizer
->two_side
;
705 key
.alpha_to_one
= rctx
->alpha_to_one
&&
706 rctx
->rasterizer
&& rctx
->rasterizer
->multisample_enable
&&
707 !rctx
->framebuffer
.cb0_is_integer
;
708 key
.nr_cbufs
= rctx
->framebuffer
.state
.nr_cbufs
;
709 /* Dual-source blending only makes sense with nr_cbufs == 1. */
710 if (key
.nr_cbufs
== 1 && rctx
->dual_src_blend
)
712 } else if (sel
->type
== PIPE_SHADER_VERTEX
) {
713 key
.vs_as_es
= (rctx
->gs_shader
!= NULL
);
714 if (rctx
->ps_shader
->current
->shader
.gs_prim_id_input
&& !rctx
->gs_shader
) {
715 key
.vs_as_gs_a
= true;
716 key
.vs_prim_id_out
= rctx
->ps_shader
->current
->shader
.input
[rctx
->ps_shader
->current
->shader
.ps_prim_id_input
].spi_sid
;
722 /* Select the hw shader variant depending on the current state.
723 * (*dirty) is set to 1 if current variant was changed */
724 static int r600_shader_select(struct pipe_context
*ctx
,
725 struct r600_pipe_shader_selector
* sel
,
728 struct r600_shader_key key
;
729 struct r600_pipe_shader
* shader
= NULL
;
732 memset(&key
, 0, sizeof(key
));
733 key
= r600_shader_selector_key(ctx
, sel
);
735 /* Check if we don't need to change anything.
736 * This path is also used for most shaders that don't need multiple
737 * variants, it will cost just a computation of the key and this
739 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
743 /* lookup if we have other variants in the list */
744 if (sel
->num_shaders
> 1) {
745 struct r600_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
747 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
753 p
->next_variant
= c
->next_variant
;
758 if (unlikely(!shader
)) {
759 shader
= CALLOC(1, sizeof(struct r600_pipe_shader
));
760 shader
->selector
= sel
;
762 r
= r600_pipe_shader_create(ctx
, shader
, key
);
764 R600_ERR("Failed to build shader variant (type=%u) %d\n",
771 /* We don't know the value of nr_ps_max_color_exports until we built
772 * at least one variant, so we may need to recompute the key after
773 * building first variant. */
774 if (sel
->type
== PIPE_SHADER_FRAGMENT
&&
775 sel
->num_shaders
== 0) {
776 sel
->nr_ps_max_color_exports
= shader
->shader
.nr_ps_max_color_exports
;
777 key
= r600_shader_selector_key(ctx
, sel
);
780 memcpy(&shader
->key
, &key
, sizeof(key
));
787 shader
->next_variant
= sel
->current
;
788 sel
->current
= shader
;
793 static void *r600_create_shader_state(struct pipe_context
*ctx
,
794 const struct pipe_shader_state
*state
,
795 unsigned pipe_shader_type
)
797 struct r600_pipe_shader_selector
*sel
= CALLOC_STRUCT(r600_pipe_shader_selector
);
799 sel
->type
= pipe_shader_type
;
800 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
801 sel
->so
= state
->stream_output
;
805 static void *r600_create_ps_state(struct pipe_context
*ctx
,
806 const struct pipe_shader_state
*state
)
808 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
811 static void *r600_create_vs_state(struct pipe_context
*ctx
,
812 const struct pipe_shader_state
*state
)
814 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
817 static void *r600_create_gs_state(struct pipe_context
*ctx
,
818 const struct pipe_shader_state
*state
)
820 return r600_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
823 static void r600_bind_ps_state(struct pipe_context
*ctx
, void *state
)
825 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
828 state
= rctx
->dummy_pixel_shader
;
830 rctx
->ps_shader
= (struct r600_pipe_shader_selector
*)state
;
833 static void r600_bind_vs_state(struct pipe_context
*ctx
, void *state
)
835 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
840 rctx
->vs_shader
= (struct r600_pipe_shader_selector
*)state
;
841 rctx
->b
.streamout
.stride_in_dw
= rctx
->vs_shader
->so
.stride
;
844 static void r600_bind_gs_state(struct pipe_context
*ctx
, void *state
)
846 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
848 rctx
->gs_shader
= (struct r600_pipe_shader_selector
*)state
;
852 rctx
->b
.streamout
.stride_in_dw
= rctx
->gs_shader
->so
.stride
;
855 static void r600_delete_shader_selector(struct pipe_context
*ctx
,
856 struct r600_pipe_shader_selector
*sel
)
858 struct r600_pipe_shader
*p
= sel
->current
, *c
;
861 r600_pipe_shader_destroy(ctx
, p
);
871 static void r600_delete_ps_state(struct pipe_context
*ctx
, void *state
)
873 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
874 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
876 if (rctx
->ps_shader
== sel
) {
877 rctx
->ps_shader
= NULL
;
880 r600_delete_shader_selector(ctx
, sel
);
883 static void r600_delete_vs_state(struct pipe_context
*ctx
, void *state
)
885 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
886 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
888 if (rctx
->vs_shader
== sel
) {
889 rctx
->vs_shader
= NULL
;
892 r600_delete_shader_selector(ctx
, sel
);
896 static void r600_delete_gs_state(struct pipe_context
*ctx
, void *state
)
898 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
899 struct r600_pipe_shader_selector
*sel
= (struct r600_pipe_shader_selector
*)state
;
901 if (rctx
->gs_shader
== sel
) {
902 rctx
->gs_shader
= NULL
;
905 r600_delete_shader_selector(ctx
, sel
);
909 void r600_constant_buffers_dirty(struct r600_context
*rctx
, struct r600_constbuf_state
*state
)
911 if (state
->dirty_mask
) {
912 rctx
->b
.flags
|= R600_CONTEXT_INV_CONST_CACHE
;
913 state
->atom
.num_dw
= rctx
->b
.chip_class
>= EVERGREEN
? util_bitcount(state
->dirty_mask
)*20
914 : util_bitcount(state
->dirty_mask
)*19;
915 state
->atom
.dirty
= true;
919 static void r600_set_constant_buffer(struct pipe_context
*ctx
, uint shader
, uint index
,
920 struct pipe_constant_buffer
*input
)
922 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
923 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
924 struct pipe_constant_buffer
*cb
;
927 /* Note that the state tracker can unbind constant buffers by
930 if (unlikely(!input
|| (!input
->buffer
&& !input
->user_buffer
))) {
931 state
->enabled_mask
&= ~(1 << index
);
932 state
->dirty_mask
&= ~(1 << index
);
933 pipe_resource_reference(&state
->cb
[index
].buffer
, NULL
);
937 cb
= &state
->cb
[index
];
938 cb
->buffer_size
= input
->buffer_size
;
940 ptr
= input
->user_buffer
;
943 /* Upload the user buffer. */
944 if (R600_BIG_ENDIAN
) {
946 unsigned i
, size
= input
->buffer_size
;
948 if (!(tmpPtr
= malloc(size
))) {
949 R600_ERR("Failed to allocate BE swap buffer.\n");
953 for (i
= 0; i
< size
/ 4; ++i
) {
954 tmpPtr
[i
] = util_cpu_to_le32(((uint32_t *)ptr
)[i
]);
957 u_upload_data(rctx
->b
.uploader
, 0, size
, tmpPtr
, &cb
->buffer_offset
, &cb
->buffer
);
960 u_upload_data(rctx
->b
.uploader
, 0, input
->buffer_size
, ptr
, &cb
->buffer_offset
, &cb
->buffer
);
962 /* account it in gtt */
963 rctx
->b
.gtt
+= input
->buffer_size
;
965 /* Setup the hw buffer. */
966 cb
->buffer_offset
= input
->buffer_offset
;
967 pipe_resource_reference(&cb
->buffer
, input
->buffer
);
968 r600_context_add_resource_size(ctx
, input
->buffer
);
971 state
->enabled_mask
|= 1 << index
;
972 state
->dirty_mask
|= 1 << index
;
973 r600_constant_buffers_dirty(rctx
, state
);
976 static void r600_set_sample_mask(struct pipe_context
*pipe
, unsigned sample_mask
)
978 struct r600_context
*rctx
= (struct r600_context
*)pipe
;
980 if (rctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
983 rctx
->sample_mask
.sample_mask
= sample_mask
;
984 rctx
->sample_mask
.atom
.dirty
= true;
988 * On r600/700 hw we don't have vertex fetch swizzle, though TBO
989 * doesn't require full swizzles it does need masking and setting alpha
990 * to one, so we setup a set of 5 constants with the masks + alpha value
991 * then in the shader, we AND the 4 components with 0xffffffff or 0,
992 * then OR the alpha with the value given here.
993 * We use a 6th constant to store the txq buffer size in
994 * we use 7th slot for number of cube layers in a cube map array.
996 static void r600_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
998 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1000 uint32_t array_size
;
1001 struct pipe_constant_buffer cb
;
1004 if (!samplers
->views
.dirty_buffer_constants
)
1007 samplers
->views
.dirty_buffer_constants
= FALSE
;
1009 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1010 array_size
= bits
* 8 * sizeof(uint32_t) * 4;
1011 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1012 memset(samplers
->buffer_constants
, 0, array_size
);
1013 for (i
= 0; i
< bits
; i
++) {
1014 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1016 const struct util_format_description
*desc
;
1017 desc
= util_format_description(samplers
->views
.views
[i
]->base
.format
);
1019 for (j
= 0; j
< 4; j
++)
1020 if (j
< desc
->nr_channels
)
1021 samplers
->buffer_constants
[offset
+j
] = 0xffffffff;
1023 samplers
->buffer_constants
[offset
+j
] = 0x0;
1024 if (desc
->nr_channels
< 4) {
1025 if (desc
->channel
[0].pure_integer
)
1026 samplers
->buffer_constants
[offset
+4] = 1;
1028 samplers
->buffer_constants
[offset
+4] = fui(1.0);
1030 samplers
->buffer_constants
[offset
+ 4] = 0;
1032 samplers
->buffer_constants
[offset
+ 5] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1033 samplers
->buffer_constants
[offset
+ 6] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1038 cb
.user_buffer
= samplers
->buffer_constants
;
1039 cb
.buffer_offset
= 0;
1040 cb
.buffer_size
= array_size
;
1041 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1042 pipe_resource_reference(&cb
.buffer
, NULL
);
1045 /* On evergreen we store two values
1046 * 1. buffer size for TXQ
1047 * 2. number of cube layers in a cube map array.
1049 static void eg_setup_buffer_constants(struct r600_context
*rctx
, int shader_type
)
1051 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader_type
];
1053 uint32_t array_size
;
1054 struct pipe_constant_buffer cb
;
1057 if (!samplers
->views
.dirty_buffer_constants
)
1060 samplers
->views
.dirty_buffer_constants
= FALSE
;
1062 bits
= util_last_bit(samplers
->views
.enabled_mask
);
1063 array_size
= bits
* 2 * sizeof(uint32_t) * 4;
1064 samplers
->buffer_constants
= realloc(samplers
->buffer_constants
, array_size
);
1065 memset(samplers
->buffer_constants
, 0, array_size
);
1066 for (i
= 0; i
< bits
; i
++) {
1067 if (samplers
->views
.enabled_mask
& (1 << i
)) {
1068 uint32_t offset
= i
* 2;
1069 samplers
->buffer_constants
[offset
] = samplers
->views
.views
[i
]->base
.texture
->width0
/ util_format_get_blocksize(samplers
->views
.views
[i
]->base
.format
);
1070 samplers
->buffer_constants
[offset
+ 1] = samplers
->views
.views
[i
]->base
.texture
->array_size
/ 6;
1075 cb
.user_buffer
= samplers
->buffer_constants
;
1076 cb
.buffer_offset
= 0;
1077 cb
.buffer_size
= array_size
;
1078 rctx
->b
.b
.set_constant_buffer(&rctx
->b
.b
, shader_type
, R600_BUFFER_INFO_CONST_BUFFER
, &cb
);
1079 pipe_resource_reference(&cb
.buffer
, NULL
);
1082 /* set sample xy locations as array of fragment shader constants */
1083 void r600_set_sample_locations_constant_buffer(struct r600_context
*rctx
)
1085 struct pipe_constant_buffer constbuf
= {0};
1086 float values
[4*16] = {0.0f
};
1088 struct pipe_context
*ctx
= &rctx
->b
.b
;
1090 assert(rctx
->framebuffer
.nr_samples
<= Elements(values
)/4);
1091 for (i
= 0; i
< rctx
->framebuffer
.nr_samples
; i
++) {
1092 ctx
->get_sample_position(ctx
, rctx
->framebuffer
.nr_samples
, i
, &values
[4*i
]);
1093 /* Also fill in center-zeroed positions used for interpolateAtSample */
1094 values
[4*i
+ 2] = values
[4*i
+ 0] - 0.5f
;
1095 values
[4*i
+ 3] = values
[4*i
+ 1] - 0.5f
;
1098 constbuf
.user_buffer
= values
;
1099 constbuf
.buffer_size
= rctx
->framebuffer
.nr_samples
* 4 * 4;
1100 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_FRAGMENT
,
1101 R600_SAMPLE_POSITIONS_CONST_BUFFER
, &constbuf
);
1102 pipe_resource_reference(&constbuf
.buffer
, NULL
);
1105 static void update_shader_atom(struct pipe_context
*ctx
,
1106 struct r600_shader_state
*state
,
1107 struct r600_pipe_shader
*shader
)
1109 state
->shader
= shader
;
1111 state
->atom
.num_dw
= shader
->command_buffer
.num_dw
;
1112 state
->atom
.dirty
= true;
1113 r600_context_add_resource_size(ctx
, (struct pipe_resource
*)shader
->bo
);
1115 state
->atom
.num_dw
= 0;
1116 state
->atom
.dirty
= false;
1120 static void update_gs_block_state(struct r600_context
*rctx
, unsigned enable
)
1122 if (rctx
->shader_stages
.geom_enable
!= enable
) {
1123 rctx
->shader_stages
.geom_enable
= enable
;
1124 rctx
->shader_stages
.atom
.dirty
= true;
1127 if (rctx
->gs_rings
.enable
!= enable
) {
1128 rctx
->gs_rings
.enable
= enable
;
1129 rctx
->gs_rings
.atom
.dirty
= true;
1131 if (enable
&& !rctx
->gs_rings
.esgs_ring
.buffer
) {
1132 unsigned size
= 0x1C000;
1133 rctx
->gs_rings
.esgs_ring
.buffer
=
1134 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1135 PIPE_USAGE_DEFAULT
, size
);
1136 rctx
->gs_rings
.esgs_ring
.buffer_size
= size
;
1140 rctx
->gs_rings
.gsvs_ring
.buffer
=
1141 pipe_buffer_create(rctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1142 PIPE_USAGE_DEFAULT
, size
);
1143 rctx
->gs_rings
.gsvs_ring
.buffer_size
= size
;
1147 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1148 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.esgs_ring
);
1149 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1150 R600_GS_RING_CONST_BUFFER
, &rctx
->gs_rings
.gsvs_ring
);
1152 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_GEOMETRY
,
1153 R600_GS_RING_CONST_BUFFER
, NULL
);
1154 r600_set_constant_buffer(&rctx
->b
.b
, PIPE_SHADER_VERTEX
,
1155 R600_GS_RING_CONST_BUFFER
, NULL
);
1160 static bool r600_update_derived_state(struct r600_context
*rctx
)
1162 struct pipe_context
* ctx
= (struct pipe_context
*)rctx
;
1163 bool ps_dirty
= false, vs_dirty
= false, gs_dirty
= false;
1165 bool need_buf_const
;
1166 if (!rctx
->blitter
->running
) {
1169 /* Decompress textures if needed. */
1170 for (i
= 0; i
< PIPE_SHADER_TYPES
; i
++) {
1171 struct r600_samplerview_state
*views
= &rctx
->samplers
[i
].views
;
1172 if (views
->compressed_depthtex_mask
) {
1173 r600_decompress_depth_textures(rctx
, views
);
1175 if (views
->compressed_colortex_mask
) {
1176 r600_decompress_color_textures(rctx
, views
);
1181 r600_shader_select(ctx
, rctx
->ps_shader
, &ps_dirty
);
1182 if (unlikely(!rctx
->ps_shader
->current
))
1185 update_gs_block_state(rctx
, rctx
->gs_shader
!= NULL
);
1187 if (rctx
->gs_shader
) {
1188 r600_shader_select(ctx
, rctx
->gs_shader
, &gs_dirty
);
1189 if (unlikely(!rctx
->gs_shader
->current
))
1192 if (!rctx
->shader_stages
.geom_enable
) {
1193 rctx
->shader_stages
.geom_enable
= true;
1194 rctx
->shader_stages
.atom
.dirty
= true;
1197 /* gs_shader provides GS and VS (copy shader) */
1198 if (unlikely(rctx
->geometry_shader
.shader
!= rctx
->gs_shader
->current
)) {
1199 update_shader_atom(ctx
, &rctx
->geometry_shader
, rctx
->gs_shader
->current
);
1200 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->gs_shader
->current
->gs_copy_shader
);
1201 /* Update clip misc state. */
1202 if (rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1203 rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1204 rctx
->clip_misc_state
.clip_disable
!= rctx
->gs_shader
->current
->shader
.vs_position_window_space
) {
1205 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->gs_shader
->current
->gs_copy_shader
->pa_cl_vs_out_cntl
;
1206 rctx
->clip_misc_state
.clip_dist_write
= rctx
->gs_shader
->current
->gs_copy_shader
->shader
.clip_dist_write
;
1207 rctx
->clip_misc_state
.clip_disable
= rctx
->gs_shader
->current
->shader
.vs_position_window_space
;
1208 rctx
->clip_misc_state
.atom
.dirty
= true;
1212 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1213 if (unlikely(!rctx
->vs_shader
->current
))
1216 /* vs_shader is used as ES */
1217 if (unlikely(vs_dirty
|| rctx
->export_shader
.shader
!= rctx
->vs_shader
->current
)) {
1218 update_shader_atom(ctx
, &rctx
->export_shader
, rctx
->vs_shader
->current
);
1221 if (unlikely(rctx
->geometry_shader
.shader
)) {
1222 update_shader_atom(ctx
, &rctx
->geometry_shader
, NULL
);
1223 update_shader_atom(ctx
, &rctx
->export_shader
, NULL
);
1224 rctx
->shader_stages
.geom_enable
= false;
1225 rctx
->shader_stages
.atom
.dirty
= true;
1228 r600_shader_select(ctx
, rctx
->vs_shader
, &vs_dirty
);
1229 if (unlikely(!rctx
->vs_shader
->current
))
1232 if (unlikely(vs_dirty
|| rctx
->vertex_shader
.shader
!= rctx
->vs_shader
->current
)) {
1233 update_shader_atom(ctx
, &rctx
->vertex_shader
, rctx
->vs_shader
->current
);
1235 /* Update clip misc state. */
1236 if (rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
!= rctx
->clip_misc_state
.pa_cl_vs_out_cntl
||
1237 rctx
->vs_shader
->current
->shader
.clip_dist_write
!= rctx
->clip_misc_state
.clip_dist_write
||
1238 rctx
->clip_misc_state
.clip_disable
!= rctx
->vs_shader
->current
->shader
.vs_position_window_space
) {
1239 rctx
->clip_misc_state
.pa_cl_vs_out_cntl
= rctx
->vs_shader
->current
->pa_cl_vs_out_cntl
;
1240 rctx
->clip_misc_state
.clip_dist_write
= rctx
->vs_shader
->current
->shader
.clip_dist_write
;
1241 rctx
->clip_misc_state
.clip_disable
= rctx
->vs_shader
->current
->shader
.vs_position_window_space
;
1242 rctx
->clip_misc_state
.atom
.dirty
= true;
1248 if (unlikely(ps_dirty
|| rctx
->pixel_shader
.shader
!= rctx
->ps_shader
->current
||
1249 rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
||
1250 rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)) {
1252 if (rctx
->cb_misc_state
.nr_ps_color_outputs
!= rctx
->ps_shader
->current
->nr_ps_color_outputs
) {
1253 rctx
->cb_misc_state
.nr_ps_color_outputs
= rctx
->ps_shader
->current
->nr_ps_color_outputs
;
1254 rctx
->cb_misc_state
.atom
.dirty
= true;
1257 if (rctx
->b
.chip_class
<= R700
) {
1258 bool multiwrite
= rctx
->ps_shader
->current
->shader
.fs_write_all
;
1260 if (rctx
->cb_misc_state
.multiwrite
!= multiwrite
) {
1261 rctx
->cb_misc_state
.multiwrite
= multiwrite
;
1262 rctx
->cb_misc_state
.atom
.dirty
= true;
1266 if (unlikely(!ps_dirty
&& rctx
->ps_shader
&& rctx
->rasterizer
&&
1267 ((rctx
->rasterizer
->sprite_coord_enable
!= rctx
->ps_shader
->current
->sprite_coord_enable
) ||
1268 (rctx
->rasterizer
->flatshade
!= rctx
->ps_shader
->current
->flatshade
)))) {
1270 if (rctx
->b
.chip_class
>= EVERGREEN
)
1271 evergreen_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1273 r600_update_ps_state(ctx
, rctx
->ps_shader
->current
);
1276 rctx
->shader_stages
.atom
.dirty
= true;
1277 update_shader_atom(ctx
, &rctx
->pixel_shader
, rctx
->ps_shader
->current
);
1280 if (rctx
->b
.chip_class
>= EVERGREEN
) {
1281 evergreen_update_db_shader_control(rctx
);
1283 r600_update_db_shader_control(rctx
);
1286 /* on R600 we stuff masks + txq info into one constant buffer */
1287 /* on evergreen we only need a txq info one */
1288 if (rctx
->ps_shader
) {
1289 need_buf_const
= rctx
->ps_shader
->current
->shader
.uses_tex_buffers
|| rctx
->ps_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1290 if (need_buf_const
) {
1291 if (rctx
->b
.chip_class
< EVERGREEN
)
1292 r600_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1294 eg_setup_buffer_constants(rctx
, PIPE_SHADER_FRAGMENT
);
1298 if (rctx
->vs_shader
) {
1299 need_buf_const
= rctx
->vs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->vs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1300 if (need_buf_const
) {
1301 if (rctx
->b
.chip_class
< EVERGREEN
)
1302 r600_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1304 eg_setup_buffer_constants(rctx
, PIPE_SHADER_VERTEX
);
1308 if (rctx
->gs_shader
) {
1309 need_buf_const
= rctx
->gs_shader
->current
->shader
.uses_tex_buffers
|| rctx
->gs_shader
->current
->shader
.has_txq_cube_array_z_comp
;
1310 if (need_buf_const
) {
1311 if (rctx
->b
.chip_class
< EVERGREEN
)
1312 r600_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1314 eg_setup_buffer_constants(rctx
, PIPE_SHADER_GEOMETRY
);
1318 if (rctx
->b
.chip_class
< EVERGREEN
&& rctx
->ps_shader
&& rctx
->vs_shader
) {
1319 if (!r600_adjust_gprs(rctx
)) {
1320 /* discard rendering */
1325 blend_disable
= (rctx
->dual_src_blend
&&
1326 rctx
->ps_shader
->current
->nr_ps_color_outputs
< 2);
1328 if (blend_disable
!= rctx
->force_blend_disable
) {
1329 rctx
->force_blend_disable
= blend_disable
;
1330 r600_bind_blend_state_internal(rctx
,
1331 rctx
->blend_state
.cso
,
1338 void r600_emit_clip_misc_state(struct r600_context
*rctx
, struct r600_atom
*atom
)
1340 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1341 struct r600_clip_misc_state
*state
= &rctx
->clip_misc_state
;
1343 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
1344 state
->pa_cl_clip_cntl
|
1345 (state
->clip_dist_write
? 0 : state
->clip_plane_enable
& 0x3F) |
1346 S_028810_CLIP_DISABLE(state
->clip_disable
));
1347 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
1348 state
->pa_cl_vs_out_cntl
|
1349 (state
->clip_plane_enable
& state
->clip_dist_write
));
1352 static void r600_draw_vbo(struct pipe_context
*ctx
, const struct pipe_draw_info
*dinfo
)
1354 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
1355 struct pipe_draw_info info
= *dinfo
;
1356 struct pipe_index_buffer ib
= {};
1358 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1360 if (!info
.indirect
&& !info
.count
&& (info
.indexed
|| !info
.count_from_stream_output
)) {
1364 if (!rctx
->vs_shader
|| !rctx
->ps_shader
) {
1369 /* make sure that the gfx ring is only one active */
1370 if (rctx
->b
.rings
.dma
.cs
&& rctx
->b
.rings
.dma
.cs
->cdw
) {
1371 rctx
->b
.rings
.dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
1374 if (!r600_update_derived_state(rctx
)) {
1375 /* useless to render because current rendering command
1382 /* Initialize the index buffer struct. */
1383 pipe_resource_reference(&ib
.buffer
, rctx
->index_buffer
.buffer
);
1384 ib
.user_buffer
= rctx
->index_buffer
.user_buffer
;
1385 ib
.index_size
= rctx
->index_buffer
.index_size
;
1386 ib
.offset
= rctx
->index_buffer
.offset
;
1387 if (!info
.indirect
) {
1388 ib
.offset
+= info
.start
* ib
.index_size
;
1391 /* Translate 8-bit indices to 16-bit. */
1392 if (unlikely(ib
.index_size
== 1)) {
1393 struct pipe_resource
*out_buffer
= NULL
;
1394 unsigned out_offset
;
1396 unsigned start
, count
;
1398 if (likely(!info
.indirect
)) {
1403 /* Have to get start/count from indirect buffer, slow path ahead... */
1404 struct r600_resource
*indirect_resource
= (struct r600_resource
*)info
.indirect
;
1405 unsigned *data
= r600_buffer_map_sync_with_rings(&rctx
->b
, indirect_resource
,
1406 PIPE_TRANSFER_READ
);
1408 data
+= info
.indirect_offset
/ sizeof(unsigned);
1409 start
= data
[2] * ib
.index_size
;
1411 rctx
->b
.ws
->buffer_unmap(indirect_resource
->cs_buf
);
1419 u_upload_alloc(rctx
->b
.uploader
, start
, count
* 2,
1420 &out_offset
, &out_buffer
, &ptr
);
1422 util_shorten_ubyte_elts_to_userptr(
1423 &rctx
->b
.b
, &ib
, 0, ib
.offset
+ start
, count
, ptr
);
1425 pipe_resource_reference(&ib
.buffer
, NULL
);
1426 ib
.user_buffer
= NULL
;
1427 ib
.buffer
= out_buffer
;
1428 ib
.offset
= out_offset
;
1432 /* Upload the index buffer.
1433 * The upload is skipped for small index counts on little-endian machines
1434 * and the indices are emitted via PKT3_DRAW_INDEX_IMMD.
1435 * Indirect draws never use immediate indices.
1436 * Note: Instanced rendering in combination with immediate indices hangs. */
1437 if (ib
.user_buffer
&& (R600_BIG_ENDIAN
|| info
.indirect
||
1438 info
.instance_count
> 1 ||
1439 info
.count
*ib
.index_size
> 20)) {
1440 u_upload_data(rctx
->b
.uploader
, 0, info
.count
* ib
.index_size
,
1441 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
1442 ib
.user_buffer
= NULL
;
1445 info
.index_bias
= info
.start
;
1448 /* Set the index offset and primitive restart. */
1449 if (rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
!= info
.primitive_restart
||
1450 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
!= info
.restart_index
||
1451 rctx
->vgt_state
.vgt_indx_offset
!= info
.index_bias
||
1452 (rctx
->vgt_state
.last_draw_was_indirect
&& !info
.indirect
)) {
1453 rctx
->vgt_state
.vgt_multi_prim_ib_reset_en
= info
.primitive_restart
;
1454 rctx
->vgt_state
.vgt_multi_prim_ib_reset_indx
= info
.restart_index
;
1455 rctx
->vgt_state
.vgt_indx_offset
= info
.index_bias
;
1456 rctx
->vgt_state
.atom
.dirty
= true;
1459 /* Workaround for hardware deadlock on certain R600 ASICs: write into a CB register. */
1460 if (rctx
->b
.chip_class
== R600
) {
1461 rctx
->b
.flags
|= R600_CONTEXT_PS_PARTIAL_FLUSH
;
1462 rctx
->cb_misc_state
.atom
.dirty
= true;
1466 r600_need_cs_space(rctx
, ib
.user_buffer
? 5 : 0, TRUE
);
1467 r600_flush_emit(rctx
);
1469 for (i
= 0; i
< R600_NUM_ATOMS
; i
++) {
1470 if (rctx
->atoms
[i
] == NULL
|| !rctx
->atoms
[i
]->dirty
) {
1473 r600_emit_atom(rctx
, rctx
->atoms
[i
]);
1476 if (rctx
->b
.chip_class
== CAYMAN
) {
1477 /* Copied from radeonsi. */
1478 unsigned primgroup_size
= 128; /* recommended without a GS */
1479 bool ia_switch_on_eop
= false;
1480 bool partial_vs_wave
= false;
1482 if (rctx
->gs_shader
)
1483 primgroup_size
= 64; /* recommended with a GS */
1485 if ((rctx
->rasterizer
&& rctx
->rasterizer
->pa_sc_line_stipple
) ||
1486 (rctx
->b
.screen
->debug_flags
& DBG_SWITCH_ON_EOP
)) {
1487 ia_switch_on_eop
= true;
1490 if (rctx
->b
.streamout
.streamout_enabled
||
1491 rctx
->b
.streamout
.prims_gen_query_enabled
)
1492 partial_vs_wave
= true;
1494 r600_write_context_reg(cs
, CM_R_028AA8_IA_MULTI_VGT_PARAM
,
1495 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop
) |
1496 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave
) |
1497 S_028AA8_PRIMGROUP_SIZE(primgroup_size
- 1));
1500 /* On R6xx, CULL_FRONT=1 culls all points, lines, and rectangles,
1501 * even though it should have no effect on those. */
1502 if (rctx
->b
.chip_class
== R600
&& rctx
->rasterizer
) {
1503 unsigned su_sc_mode_cntl
= rctx
->rasterizer
->pa_su_sc_mode_cntl
;
1504 unsigned prim
= info
.mode
;
1506 if (rctx
->gs_shader
) {
1507 prim
= rctx
->gs_shader
->current
->shader
.gs_output_prim
;
1509 prim
= r600_conv_prim_to_gs_out(prim
); /* decrease the number of types to 3 */
1511 if (prim
== V_028A6C_OUTPRIM_TYPE_POINTLIST
||
1512 prim
== V_028A6C_OUTPRIM_TYPE_LINESTRIP
||
1513 info
.mode
== R600_PRIM_RECTANGLE_LIST
) {
1514 su_sc_mode_cntl
&= C_028814_CULL_FRONT
;
1516 r600_write_context_reg(cs
, R_028814_PA_SU_SC_MODE_CNTL
, su_sc_mode_cntl
);
1519 /* Update start instance. */
1520 if (!info
.indirect
&& rctx
->last_start_instance
!= info
.start_instance
) {
1521 r600_write_ctl_const(cs
, R_03CFF4_SQ_VTX_START_INST_LOC
, info
.start_instance
);
1522 rctx
->last_start_instance
= info
.start_instance
;
1525 /* Update the primitive type. */
1526 if (rctx
->last_primitive_type
!= info
.mode
) {
1527 unsigned ls_mask
= 0;
1529 if (info
.mode
== PIPE_PRIM_LINES
)
1531 else if (info
.mode
== PIPE_PRIM_LINE_STRIP
||
1532 info
.mode
== PIPE_PRIM_LINE_LOOP
)
1535 r600_write_context_reg(cs
, R_028A0C_PA_SC_LINE_STIPPLE
,
1536 S_028A0C_AUTO_RESET_CNTL(ls_mask
) |
1537 (rctx
->rasterizer
? rctx
->rasterizer
->pa_sc_line_stipple
: 0));
1538 r600_write_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
,
1539 r600_conv_pipe_prim(info
.mode
));
1541 rctx
->last_primitive_type
= info
.mode
;
1545 if (!info
.indirect
) {
1546 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NUM_INSTANCES
, 0, rctx
->b
.predicate_drawing
);
1547 cs
->buf
[cs
->cdw
++] = info
.instance_count
;
1550 if (unlikely(info
.indirect
)) {
1551 uint64_t va
= r600_resource(info
.indirect
)->gpu_address
;
1552 assert(rctx
->b
.chip_class
>= EVERGREEN
);
1554 // Invalidate so non-indirect draw calls reset this state
1555 rctx
->vgt_state
.last_draw_was_indirect
= true;
1556 rctx
->last_start_instance
= -1;
1558 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_SET_BASE
, 2, rctx
->b
.predicate_drawing
);
1559 cs
->buf
[cs
->cdw
++] = EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE
;
1560 cs
->buf
[cs
->cdw
++] = va
;
1561 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1563 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1564 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1565 (struct r600_resource
*)info
.indirect
,
1566 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
1570 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_INDEX_TYPE
, 0, rctx
->b
.predicate_drawing
);
1571 cs
->buf
[cs
->cdw
++] = ib
.index_size
== 4 ?
1572 (VGT_INDEX_32
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_32_BIT
: 0)) :
1573 (VGT_INDEX_16
| (R600_BIG_ENDIAN
? VGT_DMA_SWAP_16_BIT
: 0));
1575 if (ib
.user_buffer
) {
1576 unsigned size_bytes
= info
.count
*ib
.index_size
;
1577 unsigned size_dw
= align(size_bytes
, 4) / 4;
1578 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_IMMD
, 1 + size_dw
, rctx
->b
.predicate_drawing
);
1579 cs
->buf
[cs
->cdw
++] = info
.count
;
1580 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_IMMEDIATE
;
1581 memcpy(cs
->buf
+cs
->cdw
, ib
.user_buffer
, size_bytes
);
1584 uint64_t va
= r600_resource(ib
.buffer
)->gpu_address
+ ib
.offset
;
1586 if (likely(!info
.indirect
)) {
1587 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX
, 3, rctx
->b
.predicate_drawing
);
1588 cs
->buf
[cs
->cdw
++] = va
;
1589 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1590 cs
->buf
[cs
->cdw
++] = info
.count
;
1591 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1592 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1593 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1594 (struct r600_resource
*)ib
.buffer
,
1595 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
1598 uint32_t max_size
= (ib
.buffer
->width0
- ib
.offset
) / ib
.index_size
;
1600 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_INDEX_BASE
, 1, rctx
->b
.predicate_drawing
);
1601 cs
->buf
[cs
->cdw
++] = va
;
1602 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFF;
1604 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, rctx
->b
.predicate_drawing
);
1605 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1606 (struct r600_resource
*)ib
.buffer
,
1607 RADEON_USAGE_READ
, RADEON_PRIO_MIN
);
1609 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_INDEX_BUFFER_SIZE
, 0, rctx
->b
.predicate_drawing
);
1610 cs
->buf
[cs
->cdw
++] = max_size
;
1612 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_DRAW_INDEX_INDIRECT
, 1, rctx
->b
.predicate_drawing
);
1613 cs
->buf
[cs
->cdw
++] = info
.indirect_offset
;
1614 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_DMA
;
1618 if (unlikely(info
.count_from_stream_output
)) {
1619 struct r600_so_target
*t
= (struct r600_so_target
*)info
.count_from_stream_output
;
1620 uint64_t va
= t
->buf_filled_size
->gpu_address
+ t
->buf_filled_size_offset
;
1622 r600_write_context_reg(cs
, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE
, t
->stride_in_dw
);
1624 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_COPY_DW
, 4, 0);
1625 cs
->buf
[cs
->cdw
++] = COPY_DW_SRC_IS_MEM
| COPY_DW_DST_IS_REG
;
1626 cs
->buf
[cs
->cdw
++] = va
& 0xFFFFFFFFUL
; /* src address lo */
1627 cs
->buf
[cs
->cdw
++] = (va
>> 32UL) & 0xFFUL
; /* src address hi */
1628 cs
->buf
[cs
->cdw
++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE
>> 2; /* dst register */
1629 cs
->buf
[cs
->cdw
++] = 0; /* unused */
1631 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_NOP
, 0, 0);
1632 cs
->buf
[cs
->cdw
++] = r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
,
1633 t
->buf_filled_size
, RADEON_USAGE_READ
,
1637 if (likely(!info
.indirect
)) {
1638 cs
->buf
[cs
->cdw
++] = PKT3(PKT3_DRAW_INDEX_AUTO
, 1, rctx
->b
.predicate_drawing
);
1639 cs
->buf
[cs
->cdw
++] = info
.count
;
1642 cs
->buf
[cs
->cdw
++] = PKT3(EG_PKT3_DRAW_INDIRECT
, 1, rctx
->b
.predicate_drawing
);
1643 cs
->buf
[cs
->cdw
++] = info
.indirect_offset
;
1645 cs
->buf
[cs
->cdw
++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX
|
1646 (info
.count_from_stream_output
? S_0287F0_USE_OPAQUE(1) : 0);
1649 if (rctx
->screen
->b
.trace_bo
) {
1650 r600_trace_emit(rctx
);
1653 /* Set the depth buffer as dirty. */
1654 if (rctx
->framebuffer
.state
.zsbuf
) {
1655 struct pipe_surface
*surf
= rctx
->framebuffer
.state
.zsbuf
;
1656 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
1658 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1660 if (rctx
->framebuffer
.compressed_cb_mask
) {
1661 struct pipe_surface
*surf
;
1662 struct r600_texture
*rtex
;
1663 unsigned mask
= rctx
->framebuffer
.compressed_cb_mask
;
1666 unsigned i
= u_bit_scan(&mask
);
1667 surf
= rctx
->framebuffer
.state
.cbufs
[i
];
1668 rtex
= (struct r600_texture
*)surf
->texture
;
1670 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
1675 pipe_resource_reference(&ib
.buffer
, NULL
);
1676 rctx
->b
.num_draw_calls
++;
1679 uint32_t r600_translate_stencil_op(int s_op
)
1682 case PIPE_STENCIL_OP_KEEP
:
1683 return V_028800_STENCIL_KEEP
;
1684 case PIPE_STENCIL_OP_ZERO
:
1685 return V_028800_STENCIL_ZERO
;
1686 case PIPE_STENCIL_OP_REPLACE
:
1687 return V_028800_STENCIL_REPLACE
;
1688 case PIPE_STENCIL_OP_INCR
:
1689 return V_028800_STENCIL_INCR
;
1690 case PIPE_STENCIL_OP_DECR
:
1691 return V_028800_STENCIL_DECR
;
1692 case PIPE_STENCIL_OP_INCR_WRAP
:
1693 return V_028800_STENCIL_INCR_WRAP
;
1694 case PIPE_STENCIL_OP_DECR_WRAP
:
1695 return V_028800_STENCIL_DECR_WRAP
;
1696 case PIPE_STENCIL_OP_INVERT
:
1697 return V_028800_STENCIL_INVERT
;
1699 R600_ERR("Unknown stencil op %d", s_op
);
1706 uint32_t r600_translate_fill(uint32_t func
)
1709 case PIPE_POLYGON_MODE_FILL
:
1711 case PIPE_POLYGON_MODE_LINE
:
1713 case PIPE_POLYGON_MODE_POINT
:
1721 unsigned r600_tex_wrap(unsigned wrap
)
1725 case PIPE_TEX_WRAP_REPEAT
:
1726 return V_03C000_SQ_TEX_WRAP
;
1727 case PIPE_TEX_WRAP_CLAMP
:
1728 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER
;
1729 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1730 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL
;
1731 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1732 return V_03C000_SQ_TEX_CLAMP_BORDER
;
1733 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1734 return V_03C000_SQ_TEX_MIRROR
;
1735 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1736 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1737 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1738 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1739 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1740 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER
;
1744 unsigned r600_tex_filter(unsigned filter
)
1748 case PIPE_TEX_FILTER_NEAREST
:
1749 return V_03C000_SQ_TEX_XY_FILTER_POINT
;
1750 case PIPE_TEX_FILTER_LINEAR
:
1751 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR
;
1755 unsigned r600_tex_mipfilter(unsigned filter
)
1758 case PIPE_TEX_MIPFILTER_NEAREST
:
1759 return V_03C000_SQ_TEX_Z_FILTER_POINT
;
1760 case PIPE_TEX_MIPFILTER_LINEAR
:
1761 return V_03C000_SQ_TEX_Z_FILTER_LINEAR
;
1763 case PIPE_TEX_MIPFILTER_NONE
:
1764 return V_03C000_SQ_TEX_Z_FILTER_NONE
;
1768 unsigned r600_tex_compare(unsigned compare
)
1772 case PIPE_FUNC_NEVER
:
1773 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER
;
1774 case PIPE_FUNC_LESS
:
1775 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS
;
1776 case PIPE_FUNC_EQUAL
:
1777 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1778 case PIPE_FUNC_LEQUAL
:
1779 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1780 case PIPE_FUNC_GREATER
:
1781 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER
;
1782 case PIPE_FUNC_NOTEQUAL
:
1783 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1784 case PIPE_FUNC_GEQUAL
:
1785 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1786 case PIPE_FUNC_ALWAYS
:
1787 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1791 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
1793 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
1794 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
1796 (wrap
== PIPE_TEX_WRAP_CLAMP
||
1797 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
1800 bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
1802 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
1803 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
1805 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
1806 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
1807 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
1808 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
1809 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
1812 void r600_emit_shader(struct r600_context
*rctx
, struct r600_atom
*a
)
1815 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
1816 struct r600_pipe_shader
*shader
= ((struct r600_shader_state
*)a
)->shader
;
1821 r600_emit_command_buffer(cs
, &shader
->command_buffer
);
1822 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
1823 radeon_emit(cs
, r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, shader
->bo
,
1824 RADEON_USAGE_READ
, RADEON_PRIO_SHADER_DATA
));
1827 unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format
,
1828 const unsigned char *swizzle_view
,
1832 unsigned char swizzle
[4];
1833 unsigned result
= 0;
1834 const uint32_t tex_swizzle_shift
[4] = {
1837 const uint32_t vtx_swizzle_shift
[4] = {
1840 const uint32_t swizzle_bit
[4] = {
1843 const uint32_t *swizzle_shift
= tex_swizzle_shift
;
1846 swizzle_shift
= vtx_swizzle_shift
;
1849 util_format_compose_swizzles(swizzle_format
, swizzle_view
, swizzle
);
1851 memcpy(swizzle
, swizzle_format
, 4);
1855 for (i
= 0; i
< 4; i
++) {
1856 switch (swizzle
[i
]) {
1857 case UTIL_FORMAT_SWIZZLE_Y
:
1858 result
|= swizzle_bit
[1] << swizzle_shift
[i
];
1860 case UTIL_FORMAT_SWIZZLE_Z
:
1861 result
|= swizzle_bit
[2] << swizzle_shift
[i
];
1863 case UTIL_FORMAT_SWIZZLE_W
:
1864 result
|= swizzle_bit
[3] << swizzle_shift
[i
];
1866 case UTIL_FORMAT_SWIZZLE_0
:
1867 result
|= V_038010_SQ_SEL_0
<< swizzle_shift
[i
];
1869 case UTIL_FORMAT_SWIZZLE_1
:
1870 result
|= V_038010_SQ_SEL_1
<< swizzle_shift
[i
];
1872 default: /* UTIL_FORMAT_SWIZZLE_X */
1873 result
|= swizzle_bit
[0] << swizzle_shift
[i
];
1879 /* texture format translate */
1880 uint32_t r600_translate_texformat(struct pipe_screen
*screen
,
1881 enum pipe_format format
,
1882 const unsigned char *swizzle_view
,
1883 uint32_t *word4_p
, uint32_t *yuv_format_p
)
1885 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1886 uint32_t result
= 0, word4
= 0, yuv_format
= 0;
1887 const struct util_format_description
*desc
;
1888 boolean uniform
= TRUE
;
1889 bool enable_s3tc
= rscreen
->b
.info
.drm_minor
>= 9;
1890 bool is_srgb_valid
= FALSE
;
1891 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
1892 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
1895 const uint32_t sign_bit
[4] = {
1896 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED
),
1897 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED
),
1898 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED
),
1899 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED
)
1901 desc
= util_format_description(format
);
1903 /* Depth and stencil swizzling is handled separately. */
1904 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
) {
1905 word4
|= r600_get_swizzle_combined(desc
->swizzle
, swizzle_view
, FALSE
);
1908 /* Colorspace (return non-RGB formats directly). */
1909 switch (desc
->colorspace
) {
1910 /* Depth stencil formats */
1911 case UTIL_FORMAT_COLORSPACE_ZS
:
1913 /* Depth sampler formats. */
1914 case PIPE_FORMAT_Z16_UNORM
:
1915 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1918 case PIPE_FORMAT_Z24X8_UNORM
:
1919 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1920 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1923 case PIPE_FORMAT_X8Z24_UNORM
:
1924 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1925 if (rscreen
->b
.chip_class
< EVERGREEN
)
1927 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1930 case PIPE_FORMAT_Z32_FLOAT
:
1931 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1932 result
= FMT_32_FLOAT
;
1934 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1935 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1936 result
= FMT_X24_8_32_FLOAT
;
1938 /* Stencil sampler formats. */
1939 case PIPE_FORMAT_S8_UINT
:
1940 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1941 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1944 case PIPE_FORMAT_X24S8_UINT
:
1945 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1946 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1949 case PIPE_FORMAT_S8X24_UINT
:
1950 if (rscreen
->b
.chip_class
< EVERGREEN
)
1952 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1953 word4
|= r600_get_swizzle_combined(swizzle_xxxx
, swizzle_view
, FALSE
);
1956 case PIPE_FORMAT_X32_S8X24_UINT
:
1957 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
1958 word4
|= r600_get_swizzle_combined(swizzle_yyyy
, swizzle_view
, FALSE
);
1959 result
= FMT_X24_8_32_FLOAT
;
1965 case UTIL_FORMAT_COLORSPACE_YUV
:
1966 yuv_format
|= (1 << 30);
1968 case PIPE_FORMAT_UYVY
:
1969 case PIPE_FORMAT_YUYV
:
1973 goto out_unknown
; /* XXX */
1975 case UTIL_FORMAT_COLORSPACE_SRGB
:
1976 word4
|= S_038010_FORCE_DEGAMMA(1);
1983 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1988 case PIPE_FORMAT_RGTC1_SNORM
:
1989 case PIPE_FORMAT_LATC1_SNORM
:
1990 word4
|= sign_bit
[0];
1991 case PIPE_FORMAT_RGTC1_UNORM
:
1992 case PIPE_FORMAT_LATC1_UNORM
:
1995 case PIPE_FORMAT_RGTC2_SNORM
:
1996 case PIPE_FORMAT_LATC2_SNORM
:
1997 word4
|= sign_bit
[0] | sign_bit
[1];
1998 case PIPE_FORMAT_RGTC2_UNORM
:
1999 case PIPE_FORMAT_LATC2_UNORM
:
2007 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
2012 if (!util_format_s3tc_enabled
) {
2017 case PIPE_FORMAT_DXT1_RGB
:
2018 case PIPE_FORMAT_DXT1_RGBA
:
2019 case PIPE_FORMAT_DXT1_SRGB
:
2020 case PIPE_FORMAT_DXT1_SRGBA
:
2022 is_srgb_valid
= TRUE
;
2024 case PIPE_FORMAT_DXT3_RGBA
:
2025 case PIPE_FORMAT_DXT3_SRGBA
:
2027 is_srgb_valid
= TRUE
;
2029 case PIPE_FORMAT_DXT5_RGBA
:
2030 case PIPE_FORMAT_DXT5_SRGBA
:
2032 is_srgb_valid
= TRUE
;
2039 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
2043 if (rscreen
->b
.chip_class
< EVERGREEN
)
2047 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
2048 case PIPE_FORMAT_BPTC_SRGBA
:
2050 is_srgb_valid
= TRUE
;
2052 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2053 word4
|= sign_bit
[0] | sign_bit
[1] | sign_bit
[2];
2055 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
2063 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2065 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
2066 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
2069 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
2070 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
2078 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
2079 result
= FMT_5_9_9_9_SHAREDEXP
;
2081 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
2082 result
= FMT_10_11_11_FLOAT
;
2087 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2088 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2089 word4
|= sign_bit
[i
];
2093 /* R8G8Bx_SNORM - XXX CxV8U8 */
2095 /* See whether the components are of the same size. */
2096 for (i
= 1; i
< desc
->nr_channels
; i
++) {
2097 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
2100 /* Non-uniform formats. */
2102 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2103 desc
->channel
[0].pure_integer
)
2104 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2105 switch(desc
->nr_channels
) {
2107 if (desc
->channel
[0].size
== 5 &&
2108 desc
->channel
[1].size
== 6 &&
2109 desc
->channel
[2].size
== 5) {
2115 if (desc
->channel
[0].size
== 5 &&
2116 desc
->channel
[1].size
== 5 &&
2117 desc
->channel
[2].size
== 5 &&
2118 desc
->channel
[3].size
== 1) {
2119 result
= FMT_1_5_5_5
;
2122 if (desc
->channel
[0].size
== 10 &&
2123 desc
->channel
[1].size
== 10 &&
2124 desc
->channel
[2].size
== 10 &&
2125 desc
->channel
[3].size
== 2) {
2126 result
= FMT_2_10_10_10
;
2134 /* Find the first non-VOID channel. */
2135 for (i
= 0; i
< 4; i
++) {
2136 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2144 /* uniform formats */
2145 switch (desc
->channel
[i
].type
) {
2146 case UTIL_FORMAT_TYPE_UNSIGNED
:
2147 case UTIL_FORMAT_TYPE_SIGNED
:
2149 if (!desc
->channel
[i
].normalized
&&
2150 desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
) {
2154 if (desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_SRGB
&&
2155 desc
->channel
[i
].pure_integer
)
2156 word4
|= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT
);
2158 switch (desc
->channel
[i
].size
) {
2160 switch (desc
->nr_channels
) {
2165 result
= FMT_4_4_4_4
;
2170 switch (desc
->nr_channels
) {
2178 result
= FMT_8_8_8_8
;
2179 is_srgb_valid
= TRUE
;
2184 switch (desc
->nr_channels
) {
2192 result
= FMT_16_16_16_16
;
2197 switch (desc
->nr_channels
) {
2205 result
= FMT_32_32_32_32
;
2211 case UTIL_FORMAT_TYPE_FLOAT
:
2212 switch (desc
->channel
[i
].size
) {
2214 switch (desc
->nr_channels
) {
2216 result
= FMT_16_FLOAT
;
2219 result
= FMT_16_16_FLOAT
;
2222 result
= FMT_16_16_16_16_FLOAT
;
2227 switch (desc
->nr_channels
) {
2229 result
= FMT_32_FLOAT
;
2232 result
= FMT_32_32_FLOAT
;
2235 result
= FMT_32_32_32_32_FLOAT
;
2244 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
&& !is_srgb_valid
)
2249 *yuv_format_p
= yuv_format
;
2252 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
2256 uint32_t r600_translate_colorformat(enum chip_class chip
, enum pipe_format format
)
2258 const struct util_format_description
*desc
= util_format_description(format
);
2259 int channel
= util_format_get_first_non_void_channel(format
);
2262 #define HAS_SIZE(x,y,z,w) \
2263 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
2264 desc->channel[2].size == (z) && desc->channel[3].size == (w))
2266 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
2267 return V_0280A0_COLOR_10_11_11_FLOAT
;
2269 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
||
2273 is_float
= desc
->channel
[channel
].type
== UTIL_FORMAT_TYPE_FLOAT
;
2275 switch (desc
->nr_channels
) {
2277 switch (desc
->channel
[0].size
) {
2279 return V_0280A0_COLOR_8
;
2282 return V_0280A0_COLOR_16_FLOAT
;
2284 return V_0280A0_COLOR_16
;
2287 return V_0280A0_COLOR_32_FLOAT
;
2289 return V_0280A0_COLOR_32
;
2293 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
2294 switch (desc
->channel
[0].size
) {
2297 return V_0280A0_COLOR_4_4
;
2299 return ~0U; /* removed on Evergreen */
2301 return V_0280A0_COLOR_8_8
;
2304 return V_0280A0_COLOR_16_16_FLOAT
;
2306 return V_0280A0_COLOR_16_16
;
2309 return V_0280A0_COLOR_32_32_FLOAT
;
2311 return V_0280A0_COLOR_32_32
;
2313 } else if (HAS_SIZE(8,24,0,0)) {
2314 return V_0280A0_COLOR_24_8
;
2315 } else if (HAS_SIZE(24,8,0,0)) {
2316 return V_0280A0_COLOR_8_24
;
2320 if (HAS_SIZE(5,6,5,0)) {
2321 return V_0280A0_COLOR_5_6_5
;
2322 } else if (HAS_SIZE(32,8,24,0)) {
2323 return V_0280A0_COLOR_X24_8_32_FLOAT
;
2327 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
2328 desc
->channel
[0].size
== desc
->channel
[2].size
&&
2329 desc
->channel
[0].size
== desc
->channel
[3].size
) {
2330 switch (desc
->channel
[0].size
) {
2332 return V_0280A0_COLOR_4_4_4_4
;
2334 return V_0280A0_COLOR_8_8_8_8
;
2337 return V_0280A0_COLOR_16_16_16_16_FLOAT
;
2339 return V_0280A0_COLOR_16_16_16_16
;
2342 return V_0280A0_COLOR_32_32_32_32_FLOAT
;
2344 return V_0280A0_COLOR_32_32_32_32
;
2346 } else if (HAS_SIZE(5,5,5,1)) {
2347 return V_0280A0_COLOR_1_5_5_5
;
2348 } else if (HAS_SIZE(10,10,10,2)) {
2349 return V_0280A0_COLOR_2_10_10_10
;
2356 uint32_t r600_colorformat_endian_swap(uint32_t colorformat
)
2358 if (R600_BIG_ENDIAN
) {
2359 switch(colorformat
) {
2360 /* 8-bit buffers. */
2361 case V_0280A0_COLOR_4_4
:
2362 case V_0280A0_COLOR_8
:
2365 /* 16-bit buffers. */
2366 case V_0280A0_COLOR_5_6_5
:
2367 case V_0280A0_COLOR_1_5_5_5
:
2368 case V_0280A0_COLOR_4_4_4_4
:
2369 case V_0280A0_COLOR_16
:
2370 case V_0280A0_COLOR_8_8
:
2371 return ENDIAN_8IN16
;
2373 /* 32-bit buffers. */
2374 case V_0280A0_COLOR_8_8_8_8
:
2375 case V_0280A0_COLOR_2_10_10_10
:
2376 case V_0280A0_COLOR_8_24
:
2377 case V_0280A0_COLOR_24_8
:
2378 case V_0280A0_COLOR_32_FLOAT
:
2379 case V_0280A0_COLOR_16_16_FLOAT
:
2380 case V_0280A0_COLOR_16_16
:
2381 return ENDIAN_8IN32
;
2383 /* 64-bit buffers. */
2384 case V_0280A0_COLOR_16_16_16_16
:
2385 case V_0280A0_COLOR_16_16_16_16_FLOAT
:
2386 return ENDIAN_8IN16
;
2388 case V_0280A0_COLOR_32_32_FLOAT
:
2389 case V_0280A0_COLOR_32_32
:
2390 case V_0280A0_COLOR_X24_8_32_FLOAT
:
2391 return ENDIAN_8IN32
;
2393 /* 128-bit buffers. */
2394 case V_0280A0_COLOR_32_32_32_32_FLOAT
:
2395 case V_0280A0_COLOR_32_32_32_32
:
2396 return ENDIAN_8IN32
;
2398 return ENDIAN_NONE
; /* Unsupported. */
2405 static void r600_invalidate_buffer(struct pipe_context
*ctx
, struct pipe_resource
*buf
)
2407 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2408 struct r600_resource
*rbuffer
= r600_resource(buf
);
2409 unsigned i
, shader
, mask
, alignment
= rbuffer
->buf
->alignment
;
2410 struct r600_pipe_sampler_view
*view
;
2412 /* Reallocate the buffer in the same pipe_resource. */
2413 r600_init_resource(&rctx
->screen
->b
, rbuffer
, rbuffer
->b
.b
.width0
,
2416 /* We changed the buffer, now we need to bind it where the old one was bound. */
2417 /* Vertex buffers. */
2418 mask
= rctx
->vertex_buffer_state
.enabled_mask
;
2420 i
= u_bit_scan(&mask
);
2421 if (rctx
->vertex_buffer_state
.vb
[i
].buffer
== &rbuffer
->b
.b
) {
2422 rctx
->vertex_buffer_state
.dirty_mask
|= 1 << i
;
2423 r600_vertex_buffers_dirty(rctx
);
2426 /* Streamout buffers. */
2427 for (i
= 0; i
< rctx
->b
.streamout
.num_targets
; i
++) {
2428 if (rctx
->b
.streamout
.targets
[i
]->b
.buffer
== &rbuffer
->b
.b
) {
2429 if (rctx
->b
.streamout
.begin_emitted
) {
2430 r600_emit_streamout_end(&rctx
->b
);
2432 rctx
->b
.streamout
.append_bitmask
= rctx
->b
.streamout
.enabled_mask
;
2433 r600_streamout_buffers_dirty(&rctx
->b
);
2437 /* Constant buffers. */
2438 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2439 struct r600_constbuf_state
*state
= &rctx
->constbuf_state
[shader
];
2441 uint32_t mask
= state
->enabled_mask
;
2444 unsigned i
= u_bit_scan(&mask
);
2445 if (state
->cb
[i
].buffer
== &rbuffer
->b
.b
) {
2447 state
->dirty_mask
|= 1 << i
;
2451 r600_constant_buffers_dirty(rctx
, state
);
2455 /* Texture buffer objects - update the virtual addresses in descriptors. */
2456 LIST_FOR_EACH_ENTRY(view
, &rctx
->b
.texture_buffers
, list
) {
2457 if (view
->base
.texture
== &rbuffer
->b
.b
) {
2458 unsigned stride
= util_format_get_blocksize(view
->base
.format
);
2459 uint64_t offset
= (uint64_t)view
->base
.u
.buf
.first_element
* stride
;
2460 uint64_t va
= rbuffer
->gpu_address
+ offset
;
2462 view
->tex_resource_words
[0] = va
;
2463 view
->tex_resource_words
[2] &= C_038008_BASE_ADDRESS_HI
;
2464 view
->tex_resource_words
[2] |= S_038008_BASE_ADDRESS_HI(va
>> 32);
2467 /* Texture buffer objects - make bindings dirty if needed. */
2468 for (shader
= 0; shader
< PIPE_SHADER_TYPES
; shader
++) {
2469 struct r600_samplerview_state
*state
= &rctx
->samplers
[shader
].views
;
2471 uint32_t mask
= state
->enabled_mask
;
2474 unsigned i
= u_bit_scan(&mask
);
2475 if (state
->views
[i
]->base
.texture
== &rbuffer
->b
.b
) {
2477 state
->dirty_mask
|= 1 << i
;
2481 r600_sampler_views_dirty(rctx
, state
);
2486 static void r600_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
2488 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2490 if (rctx
->db_misc_state
.occlusion_query_enabled
!= enable
) {
2491 rctx
->db_misc_state
.occlusion_query_enabled
= enable
;
2492 rctx
->db_misc_state
.atom
.dirty
= true;
2496 static void r600_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2497 bool include_draw_vbo
)
2499 r600_need_cs_space((struct r600_context
*)ctx
, num_dw
, include_draw_vbo
);
2502 /* keep this at the end of this file, please */
2503 void r600_init_common_state_functions(struct r600_context
*rctx
)
2505 rctx
->b
.b
.create_fs_state
= r600_create_ps_state
;
2506 rctx
->b
.b
.create_vs_state
= r600_create_vs_state
;
2507 rctx
->b
.b
.create_gs_state
= r600_create_gs_state
;
2508 rctx
->b
.b
.create_vertex_elements_state
= r600_create_vertex_fetch_shader
;
2509 rctx
->b
.b
.bind_blend_state
= r600_bind_blend_state
;
2510 rctx
->b
.b
.bind_depth_stencil_alpha_state
= r600_bind_dsa_state
;
2511 rctx
->b
.b
.bind_sampler_states
= r600_bind_sampler_states
;
2512 rctx
->b
.b
.bind_fs_state
= r600_bind_ps_state
;
2513 rctx
->b
.b
.bind_rasterizer_state
= r600_bind_rs_state
;
2514 rctx
->b
.b
.bind_vertex_elements_state
= r600_bind_vertex_elements
;
2515 rctx
->b
.b
.bind_vs_state
= r600_bind_vs_state
;
2516 rctx
->b
.b
.bind_gs_state
= r600_bind_gs_state
;
2517 rctx
->b
.b
.delete_blend_state
= r600_delete_blend_state
;
2518 rctx
->b
.b
.delete_depth_stencil_alpha_state
= r600_delete_dsa_state
;
2519 rctx
->b
.b
.delete_fs_state
= r600_delete_ps_state
;
2520 rctx
->b
.b
.delete_rasterizer_state
= r600_delete_rs_state
;
2521 rctx
->b
.b
.delete_sampler_state
= r600_delete_sampler_state
;
2522 rctx
->b
.b
.delete_vertex_elements_state
= r600_delete_vertex_elements
;
2523 rctx
->b
.b
.delete_vs_state
= r600_delete_vs_state
;
2524 rctx
->b
.b
.delete_gs_state
= r600_delete_gs_state
;
2525 rctx
->b
.b
.set_blend_color
= r600_set_blend_color
;
2526 rctx
->b
.b
.set_clip_state
= r600_set_clip_state
;
2527 rctx
->b
.b
.set_constant_buffer
= r600_set_constant_buffer
;
2528 rctx
->b
.b
.set_sample_mask
= r600_set_sample_mask
;
2529 rctx
->b
.b
.set_stencil_ref
= r600_set_pipe_stencil_ref
;
2530 rctx
->b
.b
.set_viewport_states
= r600_set_viewport_states
;
2531 rctx
->b
.b
.set_vertex_buffers
= r600_set_vertex_buffers
;
2532 rctx
->b
.b
.set_index_buffer
= r600_set_index_buffer
;
2533 rctx
->b
.b
.set_sampler_views
= r600_set_sampler_views
;
2534 rctx
->b
.b
.sampler_view_destroy
= r600_sampler_view_destroy
;
2535 rctx
->b
.b
.texture_barrier
= r600_texture_barrier
;
2536 rctx
->b
.b
.set_stream_output_targets
= r600_set_streamout_targets
;
2537 rctx
->b
.b
.draw_vbo
= r600_draw_vbo
;
2538 rctx
->b
.invalidate_buffer
= r600_invalidate_buffer
;
2539 rctx
->b
.set_occlusion_query_state
= r600_set_occlusion_query_state
;
2540 rctx
->b
.need_gfx_cs_space
= r600_need_gfx_cs_space
;
2543 void r600_trace_emit(struct r600_context
*rctx
)
2545 struct r600_screen
*rscreen
= rctx
->screen
;
2546 struct radeon_winsys_cs
*cs
= rctx
->b
.rings
.gfx
.cs
;
2550 va
= rscreen
->b
.trace_bo
->gpu_address
;
2551 reloc
= r600_context_bo_reloc(&rctx
->b
, &rctx
->b
.rings
.gfx
, rscreen
->b
.trace_bo
,
2552 RADEON_USAGE_READWRITE
, RADEON_PRIO_MIN
);
2553 radeon_emit(cs
, PKT3(PKT3_MEM_WRITE
, 3, 0));
2554 radeon_emit(cs
, va
& 0xFFFFFFFFUL
);
2555 radeon_emit(cs
, (va
>> 32UL) & 0xFFUL
);
2556 radeon_emit(cs
, cs
->cdw
);
2557 radeon_emit(cs
, rscreen
->b
.cs_count
);
2558 radeon_emit(cs
, PKT3(PKT3_NOP
, 0, 0));
2559 radeon_emit(cs
, reloc
);