src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_format_s3tc.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "state_tracker/drm_driver.h"
  35 #include "pipebuffer/pb_buffer.h"
  36 #include "r600_pipe.h"
  37 #include "r600_resource.h"
  38 #include "r600_state_inlines.h"
  39 #include "r600d.h"
  40 #include "r600_formats.h"
  41
  42 /* Copy from a full GPU texture to a transfer's staging one. */
  43 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  44 {
  45         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  46         struct pipe_resource *texture = transfer->resource;
  47
  48         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  49                                 0, 0, 0, 0, texture, transfer->level,
  50                                 &transfer->box);
  51 }
  52
  53
  54 /* Copy from a transfer's staging texture to a full GPU one. */
  55 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  56 {
  57         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  58         struct pipe_resource *texture = transfer->resource;
  59         struct pipe_box sbox;
  60
  61         sbox.x = sbox.y = sbox.z = 0;
  62         sbox.width = transfer->box.width;
  63         sbox.height = transfer->box.height;
  64         /* XXX that might be wrong */
  65         sbox.depth = 1;
  66         ctx->resource_copy_region(ctx, texture, transfer->level,
  67                                   transfer->box.x, transfer->box.y, transfer->box.z,
  68                                   rtransfer->staging_texture,
  69                                   0, &sbox);
  70
  71         ctx->flush(ctx, 0, NULL);
  72 }
  73
  74 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  75                                         unsigned level, unsigned layer)
  76 {
  77         unsigned offset = rtex->offset[level];
  78
  79         switch (rtex->resource.b.b.b.target) {
  80         case PIPE_TEXTURE_3D:
  81         case PIPE_TEXTURE_CUBE:
  82         default:
  83                 return offset + layer * rtex->layer_size[level];
  84         }
  85 }
  86
  87 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
  88                                          enum pipe_format format,
  89                                          unsigned array_mode)
  90 {
  91         struct r600_screen* rscreen = (struct r600_screen *)screen;
  92         unsigned pixsize = util_format_get_blocksize(format);
  93         int p_align;
  94
  95         switch(array_mode) {
  96         case V_038000_ARRAY_1D_TILED_THIN1:
  97                 p_align = MAX2(8,
  98                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
  99                 break;
 100         case V_038000_ARRAY_2D_TILED_THIN1:
 101                 p_align = MAX2(rscreen->tiling_info->num_banks,
 102                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 103                                 rscreen->tiling_info->num_banks)) * 8;
 104                 break;
 105         case V_038000_ARRAY_LINEAR_ALIGNED:
 106                 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
 107                 break;
 108         case V_038000_ARRAY_LINEAR_GENERAL:
 109         default:
 110                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 111                 break;
 112         }
 113         return p_align;
 114 }
 115
 116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 117                                           unsigned array_mode)
 118 {
 119         struct r600_screen* rscreen = (struct r600_screen *)screen;
 120         int h_align;
 121
 122         switch (array_mode) {
 123         case V_038000_ARRAY_2D_TILED_THIN1:
 124                 h_align = rscreen->tiling_info->num_channels * 8;
 125                 break;
 126         case V_038000_ARRAY_1D_TILED_THIN1:
 127         case V_038000_ARRAY_LINEAR_ALIGNED:
 128                 h_align = 8;
 129                 break;
 130         case V_038000_ARRAY_LINEAR_GENERAL:
 131         default:
 132                 h_align = 1;
 133                 break;
 134         }
 135         return h_align;
 136 }
 137
 138 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 139                                         enum pipe_format format,
 140                                         unsigned array_mode)
 141 {
 142         struct r600_screen* rscreen = (struct r600_screen *)screen;
 143         unsigned pixsize = util_format_get_blocksize(format);
 144         int p_align = r600_get_block_alignment(screen, format, array_mode);
 145         int h_align = r600_get_height_alignment(screen, array_mode);
 146         int b_align;
 147
 148         switch (array_mode) {
 149         case V_038000_ARRAY_2D_TILED_THIN1:
 150                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 151                                p_align * pixsize * h_align);
 152                 break;
 153         case V_038000_ARRAY_1D_TILED_THIN1:
 154         case V_038000_ARRAY_LINEAR_ALIGNED:
 155         case V_038000_ARRAY_LINEAR_GENERAL:
 156         default:
 157                 b_align = rscreen->tiling_info->group_bytes;
 158                 break;
 159         }
 160         return b_align;
 161 }
 162
 163 static unsigned mip_minify(unsigned size, unsigned level)
 164 {
 165         unsigned val;
 166         val = u_minify(size, level);
 167         if (level > 0)
 168                 val = util_next_power_of_two(val);
 169         return val;
 170 }
 171
 172 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
 173                                           struct r600_resource_texture *rtex,
 174                                           unsigned level)
 175 {
 176         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 177         unsigned nblocksx, block_align, width;
 178         unsigned blocksize = util_format_get_blocksize(ptex->format);
 179
 180         if (rtex->pitch_override)
 181                 return rtex->pitch_override / blocksize;
 182
 183         width = mip_minify(ptex->width0, level);
 184         nblocksx = util_format_get_nblocksx(ptex->format, width);
 185
 186         block_align = r600_get_block_alignment(screen, ptex->format,
 187                                               rtex->array_mode[level]);
 188         nblocksx = align(nblocksx, block_align);
 189         return nblocksx;
 190 }
 191
 192 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 193                                           struct r600_resource_texture *rtex,
 194                                           unsigned level)
 195 {
 196         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 197         unsigned height, tile_height;
 198
 199         height = mip_minify(ptex->height0, level);
 200         height = util_format_get_nblocksy(ptex->format, height);
 201         tile_height = r600_get_height_alignment(screen,
 202                                                 rtex->array_mode[level]);
 203         height = align(height, tile_height);
 204         return height;
 205 }
 206
 207 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 208                                         struct r600_resource_texture *rtex,
 209                                         unsigned level, unsigned array_mode)
 210 {
 211         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 212
 213         switch (array_mode) {
 214         case V_0280A0_ARRAY_LINEAR_GENERAL:
 215         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 216         case V_0280A0_ARRAY_1D_TILED_THIN1:
 217         default:
 218                 rtex->array_mode[level] = array_mode;
 219                 break;
 220         case V_0280A0_ARRAY_2D_TILED_THIN1:
 221         {
 222                 unsigned w, h, tile_height, tile_width;
 223
 224                 tile_height = r600_get_height_alignment(screen, array_mode);
 225                 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
 226
 227                 w = mip_minify(ptex->width0, level);
 228                 h = mip_minify(ptex->height0, level);
 229                 if (w < tile_width || h < tile_height)
 230                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 231                 else
 232                         rtex->array_mode[level] = array_mode;
 233         }
 234         break;
 235         }
 236 }
 237
 238 static void r600_setup_miptree(struct pipe_screen *screen,
 239                                struct r600_resource_texture *rtex,
 240                                unsigned array_mode)
 241 {
 242         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 243         struct radeon *radeon = (struct radeon *)screen->winsys;
 244         enum chip_class chipc = r600_get_family_class(radeon);
 245         unsigned size, layer_size, i, offset;
 246         unsigned nblocksx, nblocksy;
 247
 248         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 249                 unsigned blocksize = util_format_get_blocksize(ptex->format);
 250
 251                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 252
 253                 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 254                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 255
 256                 layer_size = nblocksx * nblocksy * blocksize;
 257                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 258                         if (chipc >= R700)
 259                                 size = layer_size * 8;
 260                         else
 261                                 size = layer_size * 6;
 262                 }
 263                 else if (ptex->target == PIPE_TEXTURE_3D)
 264                         size = layer_size * u_minify(ptex->depth0, i);
 265                 else
 266                         size = layer_size * ptex->array_size;
 267
 268                 /* align base image and start of miptree */
 269                 if ((i == 0) || (i == 1))
 270                         offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 271                 rtex->offset[i] = offset;
 272                 rtex->layer_size[i] = layer_size;
 273                 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
 274                 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
 275
 276                 offset += size;
 277         }
 278         rtex->size = offset;
 279 }
 280
 281 /* Figure out whether u_blitter will fallback to a transfer operation.
 282  * If so, don't use a staging resource.
 283  */
 284 static boolean permit_hardware_blit(struct pipe_screen *screen,
 285                                         const struct pipe_resource *res)
 286 {
 287         unsigned bind;
 288
 289         if (util_format_is_depth_or_stencil(res->format))
 290                 bind = PIPE_BIND_DEPTH_STENCIL;
 291         else
 292                 bind = PIPE_BIND_RENDER_TARGET;
 293
 294         /* hackaround for S3TC */
 295         if (util_format_is_s3tc(res->format))
 296                 return TRUE;
 297
 298         if (!screen->is_format_supported(screen,
 299                                 res->format,
 300                                 res->target,
 301                                 res->nr_samples,
 302                                 bind, 0))
 303                 return FALSE;
 304
 305         if (!screen->is_format_supported(screen,
 306                                 res->format,
 307                                 res->target,
 308                                 res->nr_samples,
 309                                 PIPE_BIND_SAMPLER_VIEW, 0))
 310                 return FALSE;
 311
 312         return TRUE;
 313 }
 314
 315 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 316                                         struct pipe_resource *ptex,
 317                                         struct winsys_handle *whandle)
 318 {
 319         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 320         struct r600_resource *resource = &rtex->resource;
 321         struct radeon *radeon = (struct radeon *)screen->winsys;
 322
 323         return r600_bo_get_winsys_handle(radeon, resource->bo,
 324                         rtex->pitch_in_bytes[0], whandle);
 325 }
 326
 327 static void r600_texture_destroy(struct pipe_screen *screen,
 328                                  struct pipe_resource *ptex)
 329 {
 330         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 331         struct r600_resource *resource = &rtex->resource;
 332         struct radeon *radeon = (struct radeon *)screen->winsys;
 333
 334         if (rtex->flushed_depth_texture)
 335                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 336
 337         if (resource->bo) {
 338                 r600_bo_reference(radeon, &resource->bo, NULL);
 339         }
 340         FREE(rtex);
 341 }
 342
 343 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 344                                                 struct pipe_resource *texture,
 345                                                 unsigned level, int layer)
 346 {
 347         /* FIXME */
 348         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 349 }
 350
 351 static const struct u_resource_vtbl r600_texture_vtbl =
 352 {
 353         r600_texture_get_handle,        /* get_handle */
 354         r600_texture_destroy,           /* resource_destroy */
 355         r600_texture_is_referenced,     /* is_resource_referenced */
 356         r600_texture_get_transfer,      /* get_transfer */
 357         r600_texture_transfer_destroy,  /* transfer_destroy */
 358         r600_texture_transfer_map,      /* transfer_map */
 359         u_default_transfer_flush_region,/* transfer_flush_region */
 360         r600_texture_transfer_unmap,    /* transfer_unmap */
 361         u_default_transfer_inline_write /* transfer_inline_write */
 362 };
 363
 364 static struct r600_resource_texture *
 365 r600_texture_create_object(struct pipe_screen *screen,
 366                            const struct pipe_resource *base,
 367                            unsigned array_mode,
 368                            unsigned pitch_in_bytes_override,
 369                            unsigned max_buffer_size,
 370                            struct r600_bo *bo)
 371 {
 372         struct r600_resource_texture *rtex;
 373         struct r600_resource *resource;
 374         struct radeon *radeon = (struct radeon *)screen->winsys;
 375
 376         rtex = CALLOC_STRUCT(r600_resource_texture);
 377         if (rtex == NULL)
 378                 return NULL;
 379
 380         resource = &rtex->resource;
 381         resource->b.b.b = *base;
 382         resource->b.b.vtbl = &r600_texture_vtbl;
 383         pipe_reference_init(&resource->b.b.b.reference, 1);
 384         resource->b.b.b.screen = screen;
 385         resource->bo = bo;
 386         rtex->pitch_override = pitch_in_bytes_override;
 387         /* only mark depth textures the HW can hit as depth textures */
 388         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 389                 rtex->depth = 1;
 390
 391         r600_setup_miptree(screen, rtex, array_mode);
 392
 393         resource->size = rtex->size;
 394
 395         if (!resource->bo) {
 396                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 397                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 398
 399                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 400                 if (!resource->bo) {
 401                         FREE(rtex);
 402                         return NULL;
 403                 }
 404         }
 405         return rtex;
 406 }
 407
 408 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 409                                                 const struct pipe_resource *templ)
 410 {
 411         unsigned array_mode = 0;
 412         static int force_tiling = -1;
 413
 414         /* Would like some magic "get_bool_option_once" routine.
 415          */
 416         if (force_tiling == -1)
 417                 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
 418
 419         if (force_tiling && permit_hardware_blit(screen, templ)) {
 420                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 421                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 422                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 423                 }
 424         }
 425
 426         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 427             util_format_is_s3tc(templ->format))
 428                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 429
 430         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 431                                                                   0, 0, NULL);
 432
 433 }
 434
 435 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 436                                                 struct pipe_resource *texture,
 437                                                 const struct pipe_surface *surf_tmpl)
 438 {
 439         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 440         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 441         unsigned level = surf_tmpl->u.tex.level;
 442
 443         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 444         if (surface == NULL)
 445                 return NULL;
 446         /* XXX no offset */
 447 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 448         pipe_reference_init(&surface->base.reference, 1);
 449         pipe_resource_reference(&surface->base.texture, texture);
 450         surface->base.context = pipe;
 451         surface->base.format = surf_tmpl->format;
 452         surface->base.width = mip_minify(texture->width0, level);
 453         surface->base.height = mip_minify(texture->height0, level);
 454         surface->base.usage = surf_tmpl->usage;
 455         surface->base.texture = texture;
 456         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 457         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 458         surface->base.u.tex.level = level;
 459
 460         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 461                                                             rtex, level);
 462         return &surface->base;
 463 }
 464
 465 static void r600_surface_destroy(struct pipe_context *pipe,
 466                                  struct pipe_surface *surface)
 467 {
 468         pipe_resource_reference(&surface->texture, NULL);
 469         FREE(surface);
 470 }
 471
 472
 473 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 474                                                const struct pipe_resource *templ,
 475                                                struct winsys_handle *whandle)
 476 {
 477         struct radeon *rw = (struct radeon*)screen->winsys;
 478         struct r600_bo *bo = NULL;
 479         unsigned array_mode = 0;
 480
 481         /* Support only 2D textures without mipmaps */
 482         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 483               templ->depth0 != 1 || templ->last_level != 0)
 484                 return NULL;
 485
 486         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 487         if (bo == NULL) {
 488                 return NULL;
 489         }
 490
 491         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 492                                                                   whandle->stride,
 493                                                                   0,
 494                                                                   bo);
 495 }
 496
 497 int r600_texture_depth_flush(struct pipe_context *ctx,
 498                              struct pipe_resource *texture, boolean just_create)
 499 {
 500         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 501         struct pipe_resource resource;
 502
 503         if (rtex->flushed_depth_texture)
 504                 goto out;
 505
 506         resource.target = PIPE_TEXTURE_2D;
 507         resource.format = texture->format;
 508         resource.width0 = texture->width0;
 509         resource.height0 = texture->height0;
 510         resource.depth0 = 1;
 511         resource.array_size = 1;
 512         resource.last_level = texture->last_level;
 513         resource.nr_samples = 0;
 514         resource.usage = PIPE_USAGE_DYNAMIC;
 515         resource.bind = 0;
 516         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 517
 518         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 519
 520         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 521         if (rtex->flushed_depth_texture == NULL) {
 522                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 523                 return -ENOMEM;
 524         }
 525
 526         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 527 out:
 528         if (just_create)
 529                 return 0;
 530
 531         /* XXX: only do this if the depth texture has actually changed:
 532          */
 533         r600_blit_uncompress_depth(ctx, rtex);
 534         return 0;
 535 }
 536
 537 /* Needs adjustment for pixelformat:
 538  */
 539 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 540 {
 541         return box->width * box->depth * box->height;
 542 };
 543
 544 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 545                                                 struct pipe_resource *texture,
 546                                                 unsigned level,
 547                                                 unsigned usage,
 548                                                 const struct pipe_box *box)
 549 {
 550         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 551         struct pipe_resource resource;
 552         struct r600_transfer *trans;
 553         int r;
 554         boolean use_staging_texture = FALSE;
 555
 556         /* We cannot map a tiled texture directly because the data is
 557          * in a different order, therefore we do detiling using a blit.
 558          *
 559          * Also, use a temporary in GTT memory for read transfers, as
 560          * the CPU is much happier reading out of cached system memory
 561          * than uncached VRAM.
 562          */
 563         if (R600_TEX_IS_TILED(rtex, level))
 564                 use_staging_texture = TRUE;
 565
 566         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 567                 use_staging_texture = TRUE;
 568
 569         /* XXX: Use a staging texture for uploads if the underlying BO
 570          * is busy.  No interface for checking that currently? so do
 571          * it eagerly whenever the transfer doesn't require a readback
 572          * and might block.
 573          */
 574         if ((usage & PIPE_TRANSFER_WRITE) &&
 575                         !(usage & (PIPE_TRANSFER_READ |
 576                                         PIPE_TRANSFER_DONTBLOCK |
 577                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 578                 use_staging_texture = TRUE;
 579
 580         if (!permit_hardware_blit(ctx->screen, texture) ||
 581                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 582                 use_staging_texture = FALSE;
 583
 584         trans = CALLOC_STRUCT(r600_transfer);
 585         if (trans == NULL)
 586                 return NULL;
 587         pipe_resource_reference(&trans->transfer.resource, texture);
 588         trans->transfer.level = level;
 589         trans->transfer.usage = usage;
 590         trans->transfer.box = *box;
 591         if (rtex->depth) {
 592                 /* XXX: only readback the rectangle which is being mapped?
 593                 */
 594                 /* XXX: when discard is true, no need to read back from depth texture
 595                 */
 596                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 597                 if (r < 0) {
 598                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 599                         pipe_resource_reference(&trans->transfer.resource, NULL);
 600                         FREE(trans);
 601                         return NULL;
 602                 }
 603                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 604                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 605                 return &trans->transfer;
 606         } else if (use_staging_texture) {
 607                 resource.target = PIPE_TEXTURE_2D;
 608                 resource.format = texture->format;
 609                 resource.width0 = box->width;
 610                 resource.height0 = box->height;
 611                 resource.depth0 = 1;
 612                 resource.array_size = 1;
 613                 resource.last_level = 0;
 614                 resource.nr_samples = 0;
 615                 resource.usage = PIPE_USAGE_STAGING;
 616                 resource.bind = 0;
 617                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 618                 /* For texture reading, the temporary (detiled) texture is used as
 619                  * a render target when blitting from a tiled texture. */
 620                 if (usage & PIPE_TRANSFER_READ) {
 621                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 622                 }
 623                 /* For texture writing, the temporary texture is used as a sampler
 624                  * when blitting into a tiled texture. */
 625                 if (usage & PIPE_TRANSFER_WRITE) {
 626                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 627                 }
 628                 /* Create the temporary texture. */
 629                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 630                 if (trans->staging_texture == NULL) {
 631                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 632                         pipe_resource_reference(&trans->transfer.resource, NULL);
 633                         FREE(trans);
 634                         return NULL;
 635                 }
 636
 637                 trans->transfer.stride =
 638                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 639                 if (usage & PIPE_TRANSFER_READ) {
 640                         r600_copy_to_staging_texture(ctx, trans);
 641                         /* Always referenced in the blit. */
 642                         ctx->flush(ctx, 0, NULL);
 643                 }
 644                 return &trans->transfer;
 645         }
 646         trans->transfer.stride = rtex->pitch_in_bytes[level];
 647         trans->transfer.layer_stride = rtex->layer_size[level];
 648         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 649         return &trans->transfer;
 650 }
 651
 652 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 653                                    struct pipe_transfer *transfer)
 654 {
 655         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 656         struct pipe_resource *texture = transfer->resource;
 657         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 658
 659         if (rtransfer->staging_texture) {
 660                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 661                         r600_copy_from_staging_texture(ctx, rtransfer);
 662                 }
 663                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 664         }
 665
 666         if (rtex->depth && !rtex->is_flushing_texture) {
 667                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 668                         r600_blit_push_depth(ctx, rtex);
 669         }
 670
 671         pipe_resource_reference(&transfer->resource, NULL);
 672         FREE(transfer);
 673 }
 674
 675 void* r600_texture_transfer_map(struct pipe_context *ctx,
 676                                 struct pipe_transfer* transfer)
 677 {
 678         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 679         struct r600_bo *bo;
 680         enum pipe_format format = transfer->resource->format;
 681         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 682         unsigned offset = 0;
 683         unsigned usage = 0;
 684         char *map;
 685
 686         if (rtransfer->staging_texture) {
 687                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 688         } else {
 689                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 690
 691                 if (rtex->flushed_depth_texture)
 692                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 693                 else
 694                         bo = ((struct r600_resource *)transfer->resource)->bo;
 695
 696                 offset = rtransfer->offset +
 697                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 698                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 699         }
 700
 701         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 702                 usage |= PB_USAGE_CPU_WRITE;
 703
 704                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 705                 }
 706
 707                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 708                 }
 709         }
 710
 711         if (transfer->usage & PIPE_TRANSFER_READ) {
 712                 usage |= PB_USAGE_CPU_READ;
 713         }
 714
 715         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 716                 usage |= PB_USAGE_DONTBLOCK;
 717         }
 718
 719         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 720                 usage |= PB_USAGE_UNSYNCHRONIZED;
 721         }
 722
 723         map = r600_bo_map(radeon, bo, usage, ctx);
 724         if (!map) {
 725                 return NULL;
 726         }
 727
 728         return map + offset;
 729 }
 730
 731 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 732                                  struct pipe_transfer* transfer)
 733 {
 734         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 735         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 736         struct r600_bo *bo;
 737
 738         if (rtransfer->staging_texture) {
 739                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 740         } else {
 741                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 742
 743                 if (rtex->flushed_depth_texture) {
 744                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 745                 } else {
 746                         bo = ((struct r600_resource *)transfer->resource)->bo;
 747                 }
 748         }
 749         r600_bo_unmap(radeon, bo);
 750 }
 751
 752 void r600_init_surface_functions(struct r600_pipe_context *r600)
 753 {
 754         r600->context.create_surface = r600_create_surface;
 755         r600->context.surface_destroy = r600_surface_destroy;
 756 }
 757
 758 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 759                 const unsigned char *swizzle_view)
 760 {
 761         unsigned i;
 762         unsigned char swizzle[4];
 763         unsigned result = 0;
 764         const uint32_t swizzle_shift[4] = {
 765                 16, 19, 22, 25,
 766         };
 767         const uint32_t swizzle_bit[4] = {
 768                 0, 1, 2, 3,
 769         };
 770
 771         if (swizzle_view) {
 772                 /* Combine two sets of swizzles. */
 773                 for (i = 0; i < 4; i++) {
 774                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 775                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 776                 }
 777         } else {
 778                 memcpy(swizzle, swizzle_format, 4);
 779         }
 780
 781         /* Get swizzle. */
 782         for (i = 0; i < 4; i++) {
 783                 switch (swizzle[i]) {
 784                 case UTIL_FORMAT_SWIZZLE_Y:
 785                         result |= swizzle_bit[1] << swizzle_shift[i];
 786                         break;
 787                 case UTIL_FORMAT_SWIZZLE_Z:
 788                         result |= swizzle_bit[2] << swizzle_shift[i];
 789                         break;
 790                 case UTIL_FORMAT_SWIZZLE_W:
 791                         result |= swizzle_bit[3] << swizzle_shift[i];
 792                         break;
 793                 case UTIL_FORMAT_SWIZZLE_0:
 794                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 795                         break;
 796                 case UTIL_FORMAT_SWIZZLE_1:
 797                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 798                         break;
 799                 default: /* UTIL_FORMAT_SWIZZLE_X */
 800                         result |= swizzle_bit[0] << swizzle_shift[i];
 801                 }
 802         }
 803         return result;
 804 }
 805
 806 /* texture format translate */
 807 uint32_t r600_translate_texformat(enum pipe_format format,
 808                                   const unsigned char *swizzle_view,
 809                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 810 {
 811         uint32_t result = 0, word4 = 0, yuv_format = 0;
 812         const struct util_format_description *desc;
 813         boolean uniform = TRUE;
 814         static int r600_enable_s3tc = -1;
 815
 816         int i;
 817         const uint32_t sign_bit[4] = {
 818                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 819                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 820                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 821                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 822         };
 823         desc = util_format_description(format);
 824
 825         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 826
 827         /* Colorspace (return non-RGB formats directly). */
 828         switch (desc->colorspace) {
 829                 /* Depth stencil formats */
 830         case UTIL_FORMAT_COLORSPACE_ZS:
 831                 switch (format) {
 832                 case PIPE_FORMAT_Z16_UNORM:
 833                         result = FMT_16;
 834                         goto out_word4;
 835                 case PIPE_FORMAT_X24S8_USCALED:
 836                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 837                 case PIPE_FORMAT_Z24X8_UNORM:
 838                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 839                         result = FMT_8_24;
 840                         goto out_word4;
 841                 case PIPE_FORMAT_S8X24_USCALED:
 842                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 843                 case PIPE_FORMAT_X8Z24_UNORM:
 844                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 845                         result = FMT_24_8;
 846                         goto out_word4;
 847                 case PIPE_FORMAT_S8_USCALED:
 848                         result = FMT_8;
 849                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 850                         goto out_word4;
 851                 default:
 852                         goto out_unknown;
 853                 }
 854
 855         case UTIL_FORMAT_COLORSPACE_YUV:
 856                 yuv_format |= (1 << 30);
 857                 switch (format) {
 858                 case PIPE_FORMAT_UYVY:
 859                 case PIPE_FORMAT_YUYV:
 860                 default:
 861                         break;
 862                 }
 863                 goto out_unknown; /* TODO */
 864
 865         case UTIL_FORMAT_COLORSPACE_SRGB:
 866                 word4 |= S_038010_FORCE_DEGAMMA(1);
 867                 break;
 868
 869         default:
 870                 break;
 871         }
 872
 873         if (r600_enable_s3tc == -1)
 874                 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 875
 876         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 877                 if (!r600_enable_s3tc)
 878                         goto out_unknown;
 879
 880                 switch (format) {
 881                 case PIPE_FORMAT_RGTC1_UNORM:
 882                 case PIPE_FORMAT_RGTC1_SNORM:
 883                         result = FMT_BC4;
 884                         goto out_word4;
 885                 case PIPE_FORMAT_RGTC2_UNORM:
 886                 case PIPE_FORMAT_RGTC2_SNORM:
 887                         result = FMT_BC5;
 888                         goto out_word4;
 889                 default:
 890                         goto out_unknown;
 891                 }
 892         }
 893
 894         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 895
 896                 if (!r600_enable_s3tc)
 897                         goto out_unknown;
 898
 899                 if (!util_format_s3tc_enabled) {
 900                         goto out_unknown;
 901                 }
 902
 903                 switch (format) {
 904                 case PIPE_FORMAT_DXT1_RGB:
 905                 case PIPE_FORMAT_DXT1_RGBA:
 906                 case PIPE_FORMAT_DXT1_SRGB:
 907                 case PIPE_FORMAT_DXT1_SRGBA:
 908                         result = FMT_BC1;
 909                         goto out_word4;
 910                 case PIPE_FORMAT_DXT3_RGBA:
 911                 case PIPE_FORMAT_DXT3_SRGBA:
 912                         result = FMT_BC2;
 913                         goto out_word4;
 914                 case PIPE_FORMAT_DXT5_RGBA:
 915                 case PIPE_FORMAT_DXT5_SRGBA:
 916                         result = FMT_BC3;
 917                         goto out_word4;
 918                 default:
 919                         goto out_unknown;
 920                 }
 921         }
 922
 923
 924         for (i = 0; i < desc->nr_channels; i++) {
 925                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 926                         word4 |= sign_bit[i];
 927                 }
 928         }
 929
 930         /* R8G8Bx_SNORM - TODO CxV8U8 */
 931
 932         /* See whether the components are of the same size. */
 933         for (i = 1; i < desc->nr_channels; i++) {
 934                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 935         }
 936
 937         /* Non-uniform formats. */
 938         if (!uniform) {
 939                 switch(desc->nr_channels) {
 940                 case 3:
 941                         if (desc->channel[0].size == 5 &&
 942                             desc->channel[1].size == 6 &&
 943                             desc->channel[2].size == 5) {
 944                                 result = FMT_5_6_5;
 945                                 goto out_word4;
 946                         }
 947                         goto out_unknown;
 948                 case 4:
 949                         if (desc->channel[0].size == 5 &&
 950                             desc->channel[1].size == 5 &&
 951                             desc->channel[2].size == 5 &&
 952                             desc->channel[3].size == 1) {
 953                                 result = FMT_1_5_5_5;
 954                                 goto out_word4;
 955                         }
 956                         if (desc->channel[0].size == 10 &&
 957                             desc->channel[1].size == 10 &&
 958                             desc->channel[2].size == 10 &&
 959                             desc->channel[3].size == 2) {
 960                                 result = FMT_2_10_10_10;
 961                                 goto out_word4;
 962                         }
 963                         goto out_unknown;
 964                 }
 965                 goto out_unknown;
 966         }
 967
 968         /* Find the first non-VOID channel. */
 969         for (i = 0; i < 4; i++) {
 970                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 971                         break;
 972                 }
 973         }
 974
 975         if (i == 4)
 976                 goto out_unknown;
 977
 978         /* uniform formats */
 979         switch (desc->channel[i].type) {
 980         case UTIL_FORMAT_TYPE_UNSIGNED:
 981         case UTIL_FORMAT_TYPE_SIGNED:
 982                 if (!desc->channel[i].normalized &&
 983                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 984                         goto out_unknown;
 985                 }
 986
 987                 switch (desc->channel[i].size) {
 988                 case 4:
 989                         switch (desc->nr_channels) {
 990                         case 2:
 991                                 result = FMT_4_4;
 992                                 goto out_word4;
 993                         case 4:
 994                                 result = FMT_4_4_4_4;
 995                                 goto out_word4;
 996                         }
 997                         goto out_unknown;
 998                 case 8:
 999                         switch (desc->nr_channels) {
1000                         case 1:
1001                                 result = FMT_8;
1002                                 goto out_word4;
1003                         case 2:
1004                                 result = FMT_8_8;
1005                                 goto out_word4;
1006                         case 4:
1007                                 result = FMT_8_8_8_8;
1008                                 goto out_word4;
1009                         }
1010                         goto out_unknown;
1011                 case 16:
1012                         switch (desc->nr_channels) {
1013                         case 1:
1014                                 result = FMT_16;
1015                                 goto out_word4;
1016                         case 2:
1017                                 result = FMT_16_16;
1018                                 goto out_word4;
1019                         case 4:
1020                                 result = FMT_16_16_16_16;
1021                                 goto out_word4;
1022                         }
1023                         goto out_unknown;
1024                 case 32:
1025                         switch (desc->nr_channels) {
1026                         case 1:
1027                                 result = FMT_32;
1028                                 goto out_word4;
1029                         case 2:
1030                                 result = FMT_32_32;
1031                                 goto out_word4;
1032                         case 4:
1033                                 result = FMT_32_32_32_32;
1034                                 goto out_word4;
1035                         }
1036                 }
1037                 goto out_unknown;
1038
1039         case UTIL_FORMAT_TYPE_FLOAT:
1040                 switch (desc->channel[i].size) {
1041                 case 16:
1042                         switch (desc->nr_channels) {
1043                         case 1:
1044                                 result = FMT_16_FLOAT;
1045                                 goto out_word4;
1046                         case 2:
1047                                 result = FMT_16_16_FLOAT;
1048                                 goto out_word4;
1049                         case 4:
1050                                 result = FMT_16_16_16_16_FLOAT;
1051                                 goto out_word4;
1052                         }
1053                         goto out_unknown;
1054                 case 32:
1055                         switch (desc->nr_channels) {
1056                         case 1:
1057                                 result = FMT_32_FLOAT;
1058                                 goto out_word4;
1059                         case 2:
1060                                 result = FMT_32_32_FLOAT;
1061                                 goto out_word4;
1062                         case 4:
1063                                 result = FMT_32_32_32_32_FLOAT;
1064                                 goto out_word4;
1065                         }
1066                 }
1067
1068         }
1069 out_word4:
1070         if (word4_p)
1071                 *word4_p = word4;
1072         if (yuv_format_p)
1073                 *yuv_format_p = yuv_format;
1074         return result;
1075 out_unknown:
1076 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1077         return ~0;
1078 }