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util: move os_time.[ch] to src/util
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
36 #include <errno.h>
37 #include <inttypes.h>
38
39 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
40 struct r600_texture *rtex);
41 static enum radeon_surf_mode
42 r600_choose_tiling(struct r600_common_screen *rscreen,
43 const struct pipe_resource *templ);
44
45
46 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
47 struct r600_texture *rdst,
48 unsigned dst_level, unsigned dstx,
49 unsigned dsty, unsigned dstz,
50 struct r600_texture *rsrc,
51 unsigned src_level,
52 const struct pipe_box *src_box)
53 {
54 if (!rctx->dma.cs)
55 return false;
56
57 if (rdst->surface.bpe != rsrc->surface.bpe)
58 return false;
59
60 /* MSAA: Blits don't exist in the real world. */
61 if (rsrc->resource.b.b.nr_samples > 1 ||
62 rdst->resource.b.b.nr_samples > 1)
63 return false;
64
65 /* Depth-stencil surfaces:
66 * When dst is linear, the DB->CB copy preserves HTILE.
67 * When dst is tiled, the 3D path must be used to update HTILE.
68 */
69 if (rsrc->is_depth || rdst->is_depth)
70 return false;
71
72 /* CMASK as:
73 * src: Both texture and SDMA paths need decompression. Use SDMA.
74 * dst: If overwriting the whole texture, discard CMASK and use
75 * SDMA. Otherwise, use the 3D path.
76 */
77 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
78 /* The CMASK clear is only enabled for the first level. */
79 assert(dst_level == 0);
80 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
81 dstx, dsty, dstz, src_box->width,
82 src_box->height, src_box->depth))
83 return false;
84
85 r600_texture_discard_cmask(rctx->screen, rdst);
86 }
87
88 /* All requirements are met. Prepare textures for SDMA. */
89 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
90 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
91
92 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
93 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
94
95 return true;
96 }
97
98 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
99 static void r600_copy_region_with_blit(struct pipe_context *pipe,
100 struct pipe_resource *dst,
101 unsigned dst_level,
102 unsigned dstx, unsigned dsty, unsigned dstz,
103 struct pipe_resource *src,
104 unsigned src_level,
105 const struct pipe_box *src_box)
106 {
107 struct pipe_blit_info blit;
108
109 memset(&blit, 0, sizeof(blit));
110 blit.src.resource = src;
111 blit.src.format = src->format;
112 blit.src.level = src_level;
113 blit.src.box = *src_box;
114 blit.dst.resource = dst;
115 blit.dst.format = dst->format;
116 blit.dst.level = dst_level;
117 blit.dst.box.x = dstx;
118 blit.dst.box.y = dsty;
119 blit.dst.box.z = dstz;
120 blit.dst.box.width = src_box->width;
121 blit.dst.box.height = src_box->height;
122 blit.dst.box.depth = src_box->depth;
123 blit.mask = util_format_get_mask(src->format) &
124 util_format_get_mask(dst->format);
125 blit.filter = PIPE_TEX_FILTER_NEAREST;
126
127 if (blit.mask) {
128 pipe->blit(pipe, &blit);
129 }
130 }
131
132 /* Copy from a full GPU texture to a transfer's staging one. */
133 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
134 {
135 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
136 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
137 struct pipe_resource *dst = &rtransfer->staging->b.b;
138 struct pipe_resource *src = transfer->resource;
139
140 if (src->nr_samples > 1) {
141 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
142 src, transfer->level, &transfer->box);
143 return;
144 }
145
146 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
147 &transfer->box);
148 }
149
150 /* Copy from a transfer's staging texture to a full GPU one. */
151 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
152 {
153 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
154 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
155 struct pipe_resource *dst = transfer->resource;
156 struct pipe_resource *src = &rtransfer->staging->b.b;
157 struct pipe_box sbox;
158
159 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
160
161 if (dst->nr_samples > 1) {
162 r600_copy_region_with_blit(ctx, dst, transfer->level,
163 transfer->box.x, transfer->box.y, transfer->box.z,
164 src, 0, &sbox);
165 return;
166 }
167
168 rctx->dma_copy(ctx, dst, transfer->level,
169 transfer->box.x, transfer->box.y, transfer->box.z,
170 src, 0, &sbox);
171 }
172
173 static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
174 struct r600_texture *rtex, unsigned level,
175 const struct pipe_box *box,
176 unsigned *stride,
177 unsigned *layer_stride)
178 {
179 *stride = rtex->surface.u.legacy.level[level].nblk_x *
180 rtex->surface.bpe;
181 *layer_stride = rtex->surface.u.legacy.level[level].slice_size;
182
183 if (!box)
184 return rtex->surface.u.legacy.level[level].offset;
185
186 /* Each texture is an array of mipmap levels. Each level is
187 * an array of slices. */
188 return rtex->surface.u.legacy.level[level].offset +
189 box->z * rtex->surface.u.legacy.level[level].slice_size +
190 (box->y / rtex->surface.blk_h *
191 rtex->surface.u.legacy.level[level].nblk_x +
192 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
193 }
194
195 static int r600_init_surface(struct r600_common_screen *rscreen,
196 struct radeon_surf *surface,
197 const struct pipe_resource *ptex,
198 enum radeon_surf_mode array_mode,
199 unsigned pitch_in_bytes_override,
200 unsigned offset,
201 bool is_imported,
202 bool is_scanout,
203 bool is_flushed_depth)
204 {
205 const struct util_format_description *desc =
206 util_format_description(ptex->format);
207 bool is_depth, is_stencil;
208 int r;
209 unsigned i, bpe, flags = 0;
210
211 is_depth = util_format_has_depth(desc);
212 is_stencil = util_format_has_stencil(desc);
213
214 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
215 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
216 bpe = 4; /* stencil is allocated separately on evergreen */
217 } else {
218 bpe = util_format_get_blocksize(ptex->format);
219 assert(util_is_power_of_two(bpe));
220 }
221
222 if (!is_flushed_depth && is_depth) {
223 flags |= RADEON_SURF_ZBUFFER;
224
225 if (is_stencil)
226 flags |= RADEON_SURF_SBUFFER;
227 }
228
229 if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
230 /* This should catch bugs in gallium users setting incorrect flags. */
231 assert(ptex->nr_samples <= 1 &&
232 ptex->array_size == 1 &&
233 ptex->depth0 == 1 &&
234 ptex->last_level == 0 &&
235 !(flags & RADEON_SURF_Z_OR_SBUFFER));
236
237 flags |= RADEON_SURF_SCANOUT;
238 }
239
240 if (ptex->bind & PIPE_BIND_SHARED)
241 flags |= RADEON_SURF_SHAREABLE;
242 if (is_imported)
243 flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
244 if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
245 flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
246
247 r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
248 array_mode, surface);
249 if (r) {
250 return r;
251 }
252
253 if (pitch_in_bytes_override &&
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
255 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
256 * for those
257 */
258 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
259 surface->u.legacy.level[0].slice_size = pitch_in_bytes_override *
260 surface->u.legacy.level[0].nblk_y;
261 }
262
263 if (offset) {
264 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
265 surface->u.legacy.level[i].offset += offset;
266 }
267
268 return 0;
269 }
270
271 static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
272 struct r600_texture *rtex,
273 struct radeon_bo_metadata *metadata)
274 {
275 struct radeon_surf *surface = &rtex->surface;
276
277 memset(metadata, 0, sizeof(*metadata));
278
279 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
280 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
281 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
282 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
283 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
284 metadata->u.legacy.bankw = surface->u.legacy.bankw;
285 metadata->u.legacy.bankh = surface->u.legacy.bankh;
286 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
287 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
288 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
289 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
290 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
291 }
292
293 static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
294 struct radeon_surf *surf,
295 struct radeon_bo_metadata *metadata,
296 enum radeon_surf_mode *array_mode,
297 bool *is_scanout)
298 {
299 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
300 surf->u.legacy.bankw = metadata->u.legacy.bankw;
301 surf->u.legacy.bankh = metadata->u.legacy.bankh;
302 surf->u.legacy.tile_split = metadata->u.legacy.tile_split;
303 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
304 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
305
306 if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED)
307 *array_mode = RADEON_SURF_MODE_2D;
308 else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
309 *array_mode = RADEON_SURF_MODE_1D;
310 else
311 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
312
313 *is_scanout = metadata->u.legacy.scanout;
314 }
315
316 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
317 struct r600_texture *rtex)
318 {
319 struct r600_common_screen *rscreen = rctx->screen;
320 struct pipe_context *ctx = &rctx->b;
321
322 if (ctx == rscreen->aux_context)
323 mtx_lock(&rscreen->aux_context_lock);
324
325 ctx->flush_resource(ctx, &rtex->resource.b.b);
326 ctx->flush(ctx, NULL, 0);
327
328 if (ctx == rscreen->aux_context)
329 mtx_unlock(&rscreen->aux_context_lock);
330 }
331
332 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
333 struct r600_texture *rtex)
334 {
335 if (!rtex->cmask.size)
336 return;
337
338 assert(rtex->resource.b.b.nr_samples <= 1);
339
340 /* Disable CMASK. */
341 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
342 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
343 rtex->dirty_level_mask = 0;
344
345 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
346
347 if (rtex->cmask_buffer != &rtex->resource)
348 r600_resource_reference(&rtex->cmask_buffer, NULL);
349
350 /* Notify all contexts about the change. */
351 p_atomic_inc(&rscreen->dirty_tex_counter);
352 p_atomic_inc(&rscreen->compressed_colortex_counter);
353 }
354
355 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
356 struct r600_texture *rtex,
357 unsigned new_bind_flag,
358 bool invalidate_storage)
359 {
360 struct pipe_screen *screen = rctx->b.screen;
361 struct r600_texture *new_tex;
362 struct pipe_resource templ = rtex->resource.b.b;
363 unsigned i;
364
365 templ.bind |= new_bind_flag;
366
367 /* r600g doesn't react to dirty_tex_descriptor_counter */
368 if (rctx->chip_class < SI)
369 return;
370
371 if (rtex->resource.b.is_shared)
372 return;
373
374 if (new_bind_flag == PIPE_BIND_LINEAR) {
375 if (rtex->surface.is_linear)
376 return;
377
378 /* This fails with MSAA, depth, and compressed textures. */
379 if (r600_choose_tiling(rctx->screen, &templ) !=
380 RADEON_SURF_MODE_LINEAR_ALIGNED)
381 return;
382 }
383
384 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
385 if (!new_tex)
386 return;
387
388 /* Copy the pixels to the new texture. */
389 if (!invalidate_storage) {
390 for (i = 0; i <= templ.last_level; i++) {
391 struct pipe_box box;
392
393 u_box_3d(0, 0, 0,
394 u_minify(templ.width0, i), u_minify(templ.height0, i),
395 util_max_layer(&templ, i) + 1, &box);
396
397 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
398 &rtex->resource.b.b, i, &box);
399 }
400 }
401
402 if (new_bind_flag == PIPE_BIND_LINEAR) {
403 r600_texture_discard_cmask(rctx->screen, rtex);
404 }
405
406 /* Replace the structure fields of rtex. */
407 rtex->resource.b.b.bind = templ.bind;
408 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
409 rtex->resource.gpu_address = new_tex->resource.gpu_address;
410 rtex->resource.vram_usage = new_tex->resource.vram_usage;
411 rtex->resource.gart_usage = new_tex->resource.gart_usage;
412 rtex->resource.bo_size = new_tex->resource.bo_size;
413 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
414 rtex->resource.domains = new_tex->resource.domains;
415 rtex->resource.flags = new_tex->resource.flags;
416 rtex->size = new_tex->size;
417 rtex->db_render_format = new_tex->db_render_format;
418 rtex->db_compatible = new_tex->db_compatible;
419 rtex->can_sample_z = new_tex->can_sample_z;
420 rtex->can_sample_s = new_tex->can_sample_s;
421 rtex->surface = new_tex->surface;
422 rtex->fmask = new_tex->fmask;
423 rtex->cmask = new_tex->cmask;
424 rtex->cb_color_info = new_tex->cb_color_info;
425 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
426 rtex->htile_offset = new_tex->htile_offset;
427 rtex->depth_cleared = new_tex->depth_cleared;
428 rtex->stencil_cleared = new_tex->stencil_cleared;
429 rtex->non_disp_tiling = new_tex->non_disp_tiling;
430 rtex->framebuffers_bound = new_tex->framebuffers_bound;
431
432 if (new_bind_flag == PIPE_BIND_LINEAR) {
433 assert(!rtex->htile_offset);
434 assert(!rtex->cmask.size);
435 assert(!rtex->fmask.size);
436 assert(!rtex->is_depth);
437 }
438
439 r600_texture_reference(&new_tex, NULL);
440
441 p_atomic_inc(&rctx->screen->dirty_tex_counter);
442 }
443
444 static boolean r600_texture_get_handle(struct pipe_screen* screen,
445 struct pipe_context *ctx,
446 struct pipe_resource *resource,
447 struct winsys_handle *whandle,
448 unsigned usage)
449 {
450 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
451 struct r600_common_context *rctx;
452 struct r600_resource *res = (struct r600_resource*)resource;
453 struct r600_texture *rtex = (struct r600_texture*)resource;
454 struct radeon_bo_metadata metadata;
455 bool update_metadata = false;
456 unsigned stride, offset, slice_size;
457
458 ctx = threaded_context_unwrap_sync(ctx);
459 rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
460
461 if (resource->target != PIPE_BUFFER) {
462 /* This is not supported now, but it might be required for OpenCL
463 * interop in the future.
464 */
465 if (resource->nr_samples > 1 || rtex->is_depth)
466 return false;
467
468 /* Move a suballocated texture into a non-suballocated allocation. */
469 if (rscreen->ws->buffer_is_suballocated(res->buf) ||
470 rtex->surface.tile_swizzle) {
471 assert(!res->b.is_shared);
472 r600_reallocate_texture_inplace(rctx, rtex,
473 PIPE_BIND_SHARED, false);
474 rctx->b.flush(&rctx->b, NULL, 0);
475 assert(res->b.b.bind & PIPE_BIND_SHARED);
476 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
477 assert(rtex->surface.tile_swizzle == 0);
478 }
479
480 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
481 rtex->cmask.size) {
482 /* Eliminate fast clear (CMASK) */
483 r600_eliminate_fast_color_clear(rctx, rtex);
484
485 /* Disable CMASK if flush_resource isn't going
486 * to be called.
487 */
488 if (rtex->cmask.size)
489 r600_texture_discard_cmask(rscreen, rtex);
490 }
491
492 /* Set metadata. */
493 if (!res->b.is_shared || update_metadata) {
494 r600_texture_init_metadata(rscreen, rtex, &metadata);
495 if (rscreen->query_opaque_metadata)
496 rscreen->query_opaque_metadata(rscreen, rtex,
497 &metadata);
498
499 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
500 }
501
502 offset = rtex->surface.u.legacy.level[0].offset;
503 stride = rtex->surface.u.legacy.level[0].nblk_x *
504 rtex->surface.bpe;
505 slice_size = rtex->surface.u.legacy.level[0].slice_size;
506 } else {
507 /* Move a suballocated buffer into a non-suballocated allocation. */
508 if (rscreen->ws->buffer_is_suballocated(res->buf)) {
509 assert(!res->b.is_shared);
510
511 /* Allocate a new buffer with PIPE_BIND_SHARED. */
512 struct pipe_resource templ = res->b.b;
513 templ.bind |= PIPE_BIND_SHARED;
514
515 struct pipe_resource *newb =
516 screen->resource_create(screen, &templ);
517 if (!newb)
518 return false;
519
520 /* Copy the old buffer contents to the new one. */
521 struct pipe_box box;
522 u_box_1d(0, newb->width0, &box);
523 rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
524 &res->b.b, 0, &box);
525 /* Move the new buffer storage to the old pipe_resource. */
526 r600_replace_buffer_storage(&rctx->b, &res->b.b, newb);
527 pipe_resource_reference(&newb, NULL);
528
529 assert(res->b.b.bind & PIPE_BIND_SHARED);
530 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
531 }
532
533 /* Buffers */
534 offset = 0;
535 stride = 0;
536 slice_size = 0;
537 }
538
539 if (res->b.is_shared) {
540 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
541 * doesn't set it.
542 */
543 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
544 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
545 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
546 } else {
547 res->b.is_shared = true;
548 res->external_usage = usage;
549 }
550
551 return rscreen->ws->buffer_get_handle(res->buf, stride, offset,
552 slice_size, whandle);
553 }
554
555 static void r600_texture_destroy(struct pipe_screen *screen,
556 struct pipe_resource *ptex)
557 {
558 struct r600_texture *rtex = (struct r600_texture*)ptex;
559 struct r600_resource *resource = &rtex->resource;
560
561 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
562
563 if (rtex->cmask_buffer != &rtex->resource) {
564 r600_resource_reference(&rtex->cmask_buffer, NULL);
565 }
566 pb_reference(&resource->buf, NULL);
567 FREE(rtex);
568 }
569
570 static const struct u_resource_vtbl r600_texture_vtbl;
571
572 /* The number of samples can be specified independently of the texture. */
573 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
574 struct r600_texture *rtex,
575 unsigned nr_samples,
576 struct r600_fmask_info *out)
577 {
578 /* FMASK is allocated like an ordinary texture. */
579 struct pipe_resource templ = rtex->resource.b.b;
580 struct radeon_surf fmask = {};
581 unsigned flags, bpe;
582
583 memset(out, 0, sizeof(*out));
584
585 templ.nr_samples = 1;
586 flags = rtex->surface.flags | RADEON_SURF_FMASK;
587
588 /* Use the same parameters and tile mode. */
589 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
590 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
591 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
592 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
593
594 if (nr_samples <= 4)
595 fmask.u.legacy.bankh = 4;
596
597 switch (nr_samples) {
598 case 2:
599 case 4:
600 bpe = 1;
601 break;
602 case 8:
603 bpe = 4;
604 break;
605 default:
606 R600_ERR("Invalid sample count for FMASK allocation.\n");
607 return;
608 }
609
610 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
611 * This can be fixed by writing a separate FMASK allocator specifically
612 * for R600-R700 asics. */
613 if (rscreen->chip_class <= R700) {
614 bpe *= 2;
615 }
616
617 if (rscreen->ws->surface_init(rscreen->ws, &templ, flags, bpe,
618 RADEON_SURF_MODE_2D, &fmask)) {
619 R600_ERR("Got error in surface_init while allocating FMASK.\n");
620 return;
621 }
622
623 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
624
625 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
626 if (out->slice_tile_max)
627 out->slice_tile_max -= 1;
628
629 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
630 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
631 out->bank_height = fmask.u.legacy.bankh;
632 out->tile_swizzle = fmask.tile_swizzle;
633 out->alignment = MAX2(256, fmask.surf_alignment);
634 out->size = fmask.surf_size;
635 }
636
637 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
638 struct r600_texture *rtex)
639 {
640 r600_texture_get_fmask_info(rscreen, rtex,
641 rtex->resource.b.b.nr_samples, &rtex->fmask);
642
643 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
644 rtex->size = rtex->fmask.offset + rtex->fmask.size;
645 }
646
647 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
648 struct r600_texture *rtex,
649 struct r600_cmask_info *out)
650 {
651 unsigned cmask_tile_width = 8;
652 unsigned cmask_tile_height = 8;
653 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
654 unsigned element_bits = 4;
655 unsigned cmask_cache_bits = 1024;
656 unsigned num_pipes = rscreen->info.num_tile_pipes;
657 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
658
659 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
660 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
661 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
662 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
663 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
664
665 unsigned pitch_elements = align(rtex->resource.b.b.width0, macro_tile_width);
666 unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
667
668 unsigned base_align = num_pipes * pipe_interleave_bytes;
669 unsigned slice_bytes =
670 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
671
672 assert(macro_tile_width % 128 == 0);
673 assert(macro_tile_height % 128 == 0);
674
675 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
676 out->alignment = MAX2(256, base_align);
677 out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
678 align(slice_bytes, base_align);
679 }
680
681 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
682 struct r600_texture *rtex)
683 {
684 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
685
686 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
687 rtex->size = rtex->cmask.offset + rtex->cmask.size;
688
689 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
690 }
691
692 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
693 struct r600_texture *rtex)
694 {
695 if (rtex->cmask_buffer)
696 return;
697
698 assert(rtex->cmask.size == 0);
699
700 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
701
702 rtex->cmask_buffer = (struct r600_resource *)
703 r600_aligned_buffer_create(&rscreen->b,
704 R600_RESOURCE_FLAG_UNMAPPABLE,
705 PIPE_USAGE_DEFAULT,
706 rtex->cmask.size,
707 rtex->cmask.alignment);
708 if (rtex->cmask_buffer == NULL) {
709 rtex->cmask.size = 0;
710 return;
711 }
712
713 /* update colorbuffer state bits */
714 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
715
716 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
717
718 p_atomic_inc(&rscreen->compressed_colortex_counter);
719 }
720
721 static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
722 struct r600_texture *rtex)
723 {
724 unsigned cl_width, cl_height, width, height;
725 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
726 unsigned num_pipes = rscreen->info.num_tile_pipes;
727
728 rtex->surface.htile_size = 0;
729
730 if (rscreen->chip_class <= EVERGREEN &&
731 rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
732 return;
733
734 /* HW bug on R6xx. */
735 if (rscreen->chip_class == R600 &&
736 (rtex->resource.b.b.width0 > 7680 ||
737 rtex->resource.b.b.height0 > 7680))
738 return;
739
740 switch (num_pipes) {
741 case 1:
742 cl_width = 32;
743 cl_height = 16;
744 break;
745 case 2:
746 cl_width = 32;
747 cl_height = 32;
748 break;
749 case 4:
750 cl_width = 64;
751 cl_height = 32;
752 break;
753 case 8:
754 cl_width = 64;
755 cl_height = 64;
756 break;
757 case 16:
758 cl_width = 128;
759 cl_height = 64;
760 break;
761 default:
762 assert(0);
763 return;
764 }
765
766 width = align(rtex->resource.b.b.width0, cl_width * 8);
767 height = align(rtex->resource.b.b.height0, cl_height * 8);
768
769 slice_elements = (width * height) / (8 * 8);
770 slice_bytes = slice_elements * 4;
771
772 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
773 base_align = num_pipes * pipe_interleave_bytes;
774
775 rtex->surface.htile_alignment = base_align;
776 rtex->surface.htile_size =
777 (util_max_layer(&rtex->resource.b.b, 0) + 1) *
778 align(slice_bytes, base_align);
779 }
780
781 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
782 struct r600_texture *rtex)
783 {
784 r600_texture_get_htile_size(rscreen, rtex);
785
786 if (!rtex->surface.htile_size)
787 return;
788
789 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
790 rtex->size = rtex->htile_offset + rtex->surface.htile_size;
791 }
792
793 void r600_print_texture_info(struct r600_common_screen *rscreen,
794 struct r600_texture *rtex, struct u_log_context *log)
795 {
796 int i;
797
798 /* Common parameters. */
799 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
800 "blk_h=%u, array_size=%u, last_level=%u, "
801 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
802 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
803 rtex->resource.b.b.depth0, rtex->surface.blk_w,
804 rtex->surface.blk_h,
805 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
806 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
807 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
808
809 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
810 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
811 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
812 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
813 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
814 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
815
816 if (rtex->fmask.size)
817 u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
818 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
819 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
820 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
821 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
822
823 if (rtex->cmask.size)
824 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
825 "slice_tile_max=%u\n",
826 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
827 rtex->cmask.slice_tile_max);
828
829 if (rtex->htile_offset)
830 u_log_printf(log, " HTile: offset=%"PRIu64", size=%"PRIu64", "
831 "alignment=%u\n",
832 rtex->htile_offset, rtex->surface.htile_size,
833 rtex->surface.htile_alignment);
834
835 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
836 u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
837 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
838 "mode=%u, tiling_index = %u\n",
839 i, rtex->surface.u.legacy.level[i].offset,
840 rtex->surface.u.legacy.level[i].slice_size,
841 u_minify(rtex->resource.b.b.width0, i),
842 u_minify(rtex->resource.b.b.height0, i),
843 u_minify(rtex->resource.b.b.depth0, i),
844 rtex->surface.u.legacy.level[i].nblk_x,
845 rtex->surface.u.legacy.level[i].nblk_y,
846 rtex->surface.u.legacy.level[i].mode,
847 rtex->surface.u.legacy.tiling_index[i]);
848
849 if (rtex->surface.has_stencil) {
850 u_log_printf(log, " StencilLayout: tilesplit=%u\n",
851 rtex->surface.u.legacy.stencil_tile_split);
852 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
853 u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
854 "slice_size=%"PRIu64", npix_x=%u, "
855 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
856 "mode=%u, tiling_index = %u\n",
857 i, rtex->surface.u.legacy.stencil_level[i].offset,
858 rtex->surface.u.legacy.stencil_level[i].slice_size,
859 u_minify(rtex->resource.b.b.width0, i),
860 u_minify(rtex->resource.b.b.height0, i),
861 u_minify(rtex->resource.b.b.depth0, i),
862 rtex->surface.u.legacy.stencil_level[i].nblk_x,
863 rtex->surface.u.legacy.stencil_level[i].nblk_y,
864 rtex->surface.u.legacy.stencil_level[i].mode,
865 rtex->surface.u.legacy.stencil_tiling_index[i]);
866 }
867 }
868 }
869
870 /* Common processing for r600_texture_create and r600_texture_from_handle */
871 static struct r600_texture *
872 r600_texture_create_object(struct pipe_screen *screen,
873 const struct pipe_resource *base,
874 struct pb_buffer *buf,
875 struct radeon_surf *surface)
876 {
877 struct r600_texture *rtex;
878 struct r600_resource *resource;
879 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
880
881 rtex = CALLOC_STRUCT(r600_texture);
882 if (!rtex)
883 return NULL;
884
885 resource = &rtex->resource;
886 resource->b.b = *base;
887 resource->b.b.next = NULL;
888 resource->b.vtbl = &r600_texture_vtbl;
889 pipe_reference_init(&resource->b.b.reference, 1);
890 resource->b.b.screen = screen;
891
892 /* don't include stencil-only formats which we don't support for rendering */
893 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
894
895 rtex->surface = *surface;
896 rtex->size = rtex->surface.surf_size;
897 rtex->db_render_format = base->format;
898
899 /* Tiled depth textures utilize the non-displayable tile order.
900 * This must be done after r600_setup_surface.
901 * Applies to R600-Cayman. */
902 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
903 /* Applies to GCN. */
904 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
905
906 if (rtex->is_depth) {
907 if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
908 R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
909 rscreen->chip_class >= EVERGREEN) {
910 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
911 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
912 } else {
913 if (rtex->resource.b.b.nr_samples <= 1 &&
914 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
915 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT))
916 rtex->can_sample_z = true;
917 }
918
919 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
920 R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
921 rtex->db_compatible = true;
922
923 if (!(rscreen->debug_flags & DBG_NO_HYPERZ))
924 r600_texture_allocate_htile(rscreen, rtex);
925 }
926 } else {
927 if (base->nr_samples > 1) {
928 if (!buf) {
929 r600_texture_allocate_fmask(rscreen, rtex);
930 r600_texture_allocate_cmask(rscreen, rtex);
931 rtex->cmask_buffer = &rtex->resource;
932 }
933 if (!rtex->fmask.size || !rtex->cmask.size) {
934 FREE(rtex);
935 return NULL;
936 }
937 }
938 }
939
940 /* Now create the backing buffer. */
941 if (!buf) {
942 r600_init_resource_fields(rscreen, resource, rtex->size,
943 rtex->surface.surf_alignment);
944
945 /* Displayable surfaces are not suballocated. */
946 if (resource->b.b.bind & PIPE_BIND_SCANOUT)
947 resource->flags |= RADEON_FLAG_NO_SUBALLOC;
948
949 if (!r600_alloc_resource(rscreen, resource)) {
950 FREE(rtex);
951 return NULL;
952 }
953 } else {
954 resource->buf = buf;
955 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
956 resource->bo_size = buf->size;
957 resource->bo_alignment = buf->alignment;
958 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
959 if (resource->domains & RADEON_DOMAIN_VRAM)
960 resource->vram_usage = buf->size;
961 else if (resource->domains & RADEON_DOMAIN_GTT)
962 resource->gart_usage = buf->size;
963 }
964
965 if (rtex->cmask.size) {
966 /* Initialize the cmask to 0xCC (= compressed state). */
967 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
968 rtex->cmask.offset, rtex->cmask.size,
969 0xCCCCCCCC);
970 }
971 if (rtex->htile_offset) {
972 uint32_t clear_value = 0;
973
974 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
975 rtex->htile_offset,
976 rtex->surface.htile_size,
977 clear_value);
978 }
979
980 /* Initialize the CMASK base register value. */
981 rtex->cmask.base_address_reg =
982 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
983
984 if (rscreen->debug_flags & DBG_VM) {
985 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
986 rtex->resource.gpu_address,
987 rtex->resource.gpu_address + rtex->resource.buf->size,
988 base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
989 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
990 }
991
992 if (rscreen->debug_flags & DBG_TEX) {
993 puts("Texture:");
994 struct u_log_context log;
995 u_log_context_init(&log);
996 r600_print_texture_info(rscreen, rtex, &log);
997 u_log_new_page_print(&log, stdout);
998 fflush(stdout);
999 u_log_context_destroy(&log);
1000 }
1001
1002 return rtex;
1003 }
1004
1005 static enum radeon_surf_mode
1006 r600_choose_tiling(struct r600_common_screen *rscreen,
1007 const struct pipe_resource *templ)
1008 {
1009 const struct util_format_description *desc = util_format_description(templ->format);
1010 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1011 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1012 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1013
1014 /* MSAA resources must be 2D tiled. */
1015 if (templ->nr_samples > 1)
1016 return RADEON_SURF_MODE_2D;
1017
1018 /* Transfer resources should be linear. */
1019 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1020 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1021
1022 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1023 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
1024 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
1025 (templ->target == PIPE_TEXTURE_2D ||
1026 templ->target == PIPE_TEXTURE_3D))
1027 force_tiling = true;
1028
1029 /* Handle common candidates for the linear mode.
1030 * Compressed textures and DB surfaces must always be tiled.
1031 */
1032 if (!force_tiling &&
1033 !is_depth_stencil &&
1034 !util_format_is_compressed(templ->format)) {
1035 if (rscreen->debug_flags & DBG_NO_TILING)
1036 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1037
1038 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1039 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1040 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1041
1042 if (templ->bind & PIPE_BIND_LINEAR)
1043 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1044
1045 /* Textures with a very small height are recommended to be linear. */
1046 if (templ->target == PIPE_TEXTURE_1D ||
1047 templ->target == PIPE_TEXTURE_1D_ARRAY ||
1048 /* Only very thin and long 2D textures should benefit from
1049 * linear_aligned. */
1050 (templ->width0 > 8 && templ->height0 <= 2))
1051 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1052
1053 /* Textures likely to be mapped often. */
1054 if (templ->usage == PIPE_USAGE_STAGING ||
1055 templ->usage == PIPE_USAGE_STREAM)
1056 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1057 }
1058
1059 /* Make small textures 1D tiled. */
1060 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1061 (rscreen->debug_flags & DBG_NO_2D_TILING))
1062 return RADEON_SURF_MODE_1D;
1063
1064 /* The allocator will switch to 1D if needed. */
1065 return RADEON_SURF_MODE_2D;
1066 }
1067
1068 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
1069 const struct pipe_resource *templ)
1070 {
1071 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1072 struct radeon_surf surface = {0};
1073 bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1074 int r;
1075
1076 r = r600_init_surface(rscreen, &surface, templ,
1077 r600_choose_tiling(rscreen, templ), 0, 0,
1078 false, false, is_flushed_depth);
1079 if (r) {
1080 return NULL;
1081 }
1082
1083 return (struct pipe_resource *)
1084 r600_texture_create_object(screen, templ, NULL, &surface);
1085 }
1086
1087 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1088 const struct pipe_resource *templ,
1089 struct winsys_handle *whandle,
1090 unsigned usage)
1091 {
1092 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1093 struct pb_buffer *buf = NULL;
1094 unsigned stride = 0, offset = 0;
1095 enum radeon_surf_mode array_mode;
1096 struct radeon_surf surface = {};
1097 int r;
1098 struct radeon_bo_metadata metadata = {};
1099 struct r600_texture *rtex;
1100 bool is_scanout;
1101
1102 /* Support only 2D textures without mipmaps */
1103 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1104 templ->depth0 != 1 || templ->last_level != 0)
1105 return NULL;
1106
1107 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset);
1108 if (!buf)
1109 return NULL;
1110
1111 rscreen->ws->buffer_get_metadata(buf, &metadata);
1112 r600_surface_import_metadata(rscreen, &surface, &metadata,
1113 &array_mode, &is_scanout);
1114
1115 r = r600_init_surface(rscreen, &surface, templ, array_mode, stride,
1116 offset, true, is_scanout, false);
1117 if (r) {
1118 return NULL;
1119 }
1120
1121 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1122 if (!rtex)
1123 return NULL;
1124
1125 rtex->resource.b.is_shared = true;
1126 rtex->resource.external_usage = usage;
1127
1128 if (rscreen->apply_opaque_metadata)
1129 rscreen->apply_opaque_metadata(rscreen, rtex, &metadata);
1130
1131 assert(rtex->surface.tile_swizzle == 0);
1132 return &rtex->resource.b.b;
1133 }
1134
1135 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1136 struct pipe_resource *texture,
1137 struct r600_texture **staging)
1138 {
1139 struct r600_texture *rtex = (struct r600_texture*)texture;
1140 struct pipe_resource resource;
1141 struct r600_texture **flushed_depth_texture = staging ?
1142 staging : &rtex->flushed_depth_texture;
1143 enum pipe_format pipe_format = texture->format;
1144
1145 if (!staging) {
1146 if (rtex->flushed_depth_texture)
1147 return true; /* it's ready */
1148
1149 if (!rtex->can_sample_z && rtex->can_sample_s) {
1150 switch (pipe_format) {
1151 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1152 /* Save memory by not allocating the S plane. */
1153 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1154 break;
1155 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1156 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1157 /* Save memory bandwidth by not copying the
1158 * stencil part during flush.
1159 *
1160 * This potentially increases memory bandwidth
1161 * if an application uses both Z and S texturing
1162 * simultaneously (a flushed Z24S8 texture
1163 * would be stored compactly), but how often
1164 * does that really happen?
1165 */
1166 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1167 break;
1168 default:;
1169 }
1170 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1171 assert(util_format_has_stencil(util_format_description(pipe_format)));
1172
1173 /* DB->CB copies to an 8bpp surface don't work. */
1174 pipe_format = PIPE_FORMAT_X24S8_UINT;
1175 }
1176 }
1177
1178 memset(&resource, 0, sizeof(resource));
1179 resource.target = texture->target;
1180 resource.format = pipe_format;
1181 resource.width0 = texture->width0;
1182 resource.height0 = texture->height0;
1183 resource.depth0 = texture->depth0;
1184 resource.array_size = texture->array_size;
1185 resource.last_level = texture->last_level;
1186 resource.nr_samples = texture->nr_samples;
1187 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1188 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1189 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1190
1191 if (staging)
1192 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1193
1194 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1195 if (*flushed_depth_texture == NULL) {
1196 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1197 return false;
1198 }
1199
1200 (*flushed_depth_texture)->non_disp_tiling = false;
1201 return true;
1202 }
1203
1204 /**
1205 * Initialize the pipe_resource descriptor to be of the same size as the box,
1206 * which is supposed to hold a subregion of the texture "orig" at the given
1207 * mipmap level.
1208 */
1209 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1210 struct pipe_resource *orig,
1211 const struct pipe_box *box,
1212 unsigned level, unsigned flags)
1213 {
1214 memset(res, 0, sizeof(*res));
1215 res->format = orig->format;
1216 res->width0 = box->width;
1217 res->height0 = box->height;
1218 res->depth0 = 1;
1219 res->array_size = 1;
1220 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1221 res->flags = flags;
1222
1223 /* We must set the correct texture target and dimensions for a 3D box. */
1224 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1225 res->target = PIPE_TEXTURE_2D_ARRAY;
1226 res->array_size = box->depth;
1227 } else {
1228 res->target = PIPE_TEXTURE_2D;
1229 }
1230 }
1231
1232 static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
1233 struct r600_texture *rtex,
1234 unsigned transfer_usage,
1235 const struct pipe_box *box)
1236 {
1237 /* r600g doesn't react to dirty_tex_descriptor_counter */
1238 return rscreen->chip_class >= SI &&
1239 !rtex->resource.b.is_shared &&
1240 !(transfer_usage & PIPE_TRANSFER_READ) &&
1241 rtex->resource.b.b.last_level == 0 &&
1242 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1243 box->x, box->y, box->z,
1244 box->width, box->height,
1245 box->depth);
1246 }
1247
1248 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1249 struct r600_texture *rtex)
1250 {
1251 struct r600_common_screen *rscreen = rctx->screen;
1252
1253 /* There is no point in discarding depth and tiled buffers. */
1254 assert(!rtex->is_depth);
1255 assert(rtex->surface.is_linear);
1256
1257 /* Reallocate the buffer in the same pipe_resource. */
1258 r600_alloc_resource(rscreen, &rtex->resource);
1259
1260 /* Initialize the CMASK base address (needed even without CMASK). */
1261 rtex->cmask.base_address_reg =
1262 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1263
1264 p_atomic_inc(&rscreen->dirty_tex_counter);
1265
1266 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1267 }
1268
1269 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1270 struct pipe_resource *texture,
1271 unsigned level,
1272 unsigned usage,
1273 const struct pipe_box *box,
1274 struct pipe_transfer **ptransfer)
1275 {
1276 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1277 struct r600_texture *rtex = (struct r600_texture*)texture;
1278 struct r600_transfer *trans;
1279 struct r600_resource *buf;
1280 unsigned offset = 0;
1281 char *map;
1282 bool use_staging_texture = false;
1283
1284 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1285 assert(box->width && box->height && box->depth);
1286
1287 /* Depth textures use staging unconditionally. */
1288 if (!rtex->is_depth) {
1289 /* Degrade the tile mode if we get too many transfers on APUs.
1290 * On dGPUs, the staging texture is always faster.
1291 * Only count uploads that are at least 4x4 pixels large.
1292 */
1293 if (!rctx->screen->info.has_dedicated_vram &&
1294 level == 0 &&
1295 box->width >= 4 && box->height >= 4 &&
1296 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1297 bool can_invalidate =
1298 r600_can_invalidate_texture(rctx->screen, rtex,
1299 usage, box);
1300
1301 r600_reallocate_texture_inplace(rctx, rtex,
1302 PIPE_BIND_LINEAR,
1303 can_invalidate);
1304 }
1305
1306 /* Tiled textures need to be converted into a linear texture for CPU
1307 * access. The staging texture is always linear and is placed in GART.
1308 *
1309 * Reading from VRAM or GTT WC is slow, always use the staging
1310 * texture in this case.
1311 *
1312 * Use the staging texture for uploads if the underlying BO
1313 * is busy.
1314 */
1315 if (!rtex->surface.is_linear)
1316 use_staging_texture = true;
1317 else if (usage & PIPE_TRANSFER_READ)
1318 use_staging_texture =
1319 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1320 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1321 /* Write & linear only: */
1322 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1323 RADEON_USAGE_READWRITE) ||
1324 !rctx->ws->buffer_wait(rtex->resource.buf, 0,
1325 RADEON_USAGE_READWRITE)) {
1326 /* It's busy. */
1327 if (r600_can_invalidate_texture(rctx->screen, rtex,
1328 usage, box))
1329 r600_texture_invalidate_storage(rctx, rtex);
1330 else
1331 use_staging_texture = true;
1332 }
1333 }
1334
1335 trans = CALLOC_STRUCT(r600_transfer);
1336 if (!trans)
1337 return NULL;
1338 pipe_resource_reference(&trans->b.b.resource, texture);
1339 trans->b.b.level = level;
1340 trans->b.b.usage = usage;
1341 trans->b.b.box = *box;
1342
1343 if (rtex->is_depth) {
1344 struct r600_texture *staging_depth;
1345
1346 if (rtex->resource.b.b.nr_samples > 1) {
1347 /* MSAA depth buffers need to be converted to single sample buffers.
1348 *
1349 * Mapping MSAA depth buffers can occur if ReadPixels is called
1350 * with a multisample GLX visual.
1351 *
1352 * First downsample the depth buffer to a temporary texture,
1353 * then decompress the temporary one to staging.
1354 *
1355 * Only the region being mapped is transfered.
1356 */
1357 struct pipe_resource resource;
1358
1359 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1360
1361 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1362 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1363 FREE(trans);
1364 return NULL;
1365 }
1366
1367 if (usage & PIPE_TRANSFER_READ) {
1368 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1369 if (!temp) {
1370 R600_ERR("failed to create a temporary depth texture\n");
1371 FREE(trans);
1372 return NULL;
1373 }
1374
1375 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1376 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1377 0, 0, 0, box->depth, 0, 0);
1378 pipe_resource_reference(&temp, NULL);
1379 }
1380
1381 /* Just get the strides. */
1382 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1383 &trans->b.b.stride,
1384 &trans->b.b.layer_stride);
1385 } else {
1386 /* XXX: only readback the rectangle which is being mapped? */
1387 /* XXX: when discard is true, no need to read back from depth texture */
1388 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1389 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1390 FREE(trans);
1391 return NULL;
1392 }
1393
1394 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1395 level, level,
1396 box->z, box->z + box->depth - 1,
1397 0, 0);
1398
1399 offset = r600_texture_get_offset(rctx->screen, staging_depth,
1400 level, box,
1401 &trans->b.b.stride,
1402 &trans->b.b.layer_stride);
1403 }
1404
1405 trans->staging = (struct r600_resource*)staging_depth;
1406 buf = trans->staging;
1407 } else if (use_staging_texture) {
1408 struct pipe_resource resource;
1409 struct r600_texture *staging;
1410
1411 r600_init_temp_resource_from_box(&resource, texture, box, level,
1412 R600_RESOURCE_FLAG_TRANSFER);
1413 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1414 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1415
1416 /* Create the temporary texture. */
1417 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1418 if (!staging) {
1419 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1420 FREE(trans);
1421 return NULL;
1422 }
1423 trans->staging = &staging->resource;
1424
1425 /* Just get the strides. */
1426 r600_texture_get_offset(rctx->screen, staging, 0, NULL,
1427 &trans->b.b.stride,
1428 &trans->b.b.layer_stride);
1429
1430 if (usage & PIPE_TRANSFER_READ)
1431 r600_copy_to_staging_texture(ctx, trans);
1432 else
1433 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1434
1435 buf = trans->staging;
1436 } else {
1437 /* the resource is mapped directly */
1438 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1439 &trans->b.b.stride,
1440 &trans->b.b.layer_stride);
1441 buf = &rtex->resource;
1442 }
1443
1444 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1445 r600_resource_reference(&trans->staging, NULL);
1446 FREE(trans);
1447 return NULL;
1448 }
1449
1450 *ptransfer = &trans->b.b;
1451 return map + offset;
1452 }
1453
1454 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1455 struct pipe_transfer* transfer)
1456 {
1457 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1458 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1459 struct pipe_resource *texture = transfer->resource;
1460 struct r600_texture *rtex = (struct r600_texture*)texture;
1461
1462 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1463 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1464 ctx->resource_copy_region(ctx, texture, transfer->level,
1465 transfer->box.x, transfer->box.y, transfer->box.z,
1466 &rtransfer->staging->b.b, transfer->level,
1467 &transfer->box);
1468 } else {
1469 r600_copy_from_staging_texture(ctx, rtransfer);
1470 }
1471 }
1472
1473 if (rtransfer->staging) {
1474 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1475 r600_resource_reference(&rtransfer->staging, NULL);
1476 }
1477
1478 /* Heuristic for {upload, draw, upload, draw, ..}:
1479 *
1480 * Flush the gfx IB if we've allocated too much texture storage.
1481 *
1482 * The idea is that we don't want to build IBs that use too much
1483 * memory and put pressure on the kernel memory manager and we also
1484 * want to make temporary and invalidated buffers go idle ASAP to
1485 * decrease the total memory usage or make them reusable. The memory
1486 * usage will be slightly higher than given here because of the buffer
1487 * cache in the winsys.
1488 *
1489 * The result is that the kernel memory manager is never a bottleneck.
1490 */
1491 if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
1492 rctx->gfx.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
1493 rctx->num_alloc_tex_transfer_bytes = 0;
1494 }
1495
1496 pipe_resource_reference(&transfer->resource, NULL);
1497 FREE(transfer);
1498 }
1499
1500 static const struct u_resource_vtbl r600_texture_vtbl =
1501 {
1502 NULL, /* get_handle */
1503 r600_texture_destroy, /* resource_destroy */
1504 r600_texture_transfer_map, /* transfer_map */
1505 u_default_transfer_flush_region, /* transfer_flush_region */
1506 r600_texture_transfer_unmap, /* transfer_unmap */
1507 };
1508
1509 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1510 struct pipe_resource *texture,
1511 const struct pipe_surface *templ,
1512 unsigned width0, unsigned height0,
1513 unsigned width, unsigned height)
1514 {
1515 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1516
1517 if (!surface)
1518 return NULL;
1519
1520 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1521 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1522
1523 pipe_reference_init(&surface->base.reference, 1);
1524 pipe_resource_reference(&surface->base.texture, texture);
1525 surface->base.context = pipe;
1526 surface->base.format = templ->format;
1527 surface->base.width = width;
1528 surface->base.height = height;
1529 surface->base.u = templ->u;
1530
1531 surface->width0 = width0;
1532 surface->height0 = height0;
1533
1534 return &surface->base;
1535 }
1536
1537 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1538 struct pipe_resource *tex,
1539 const struct pipe_surface *templ)
1540 {
1541 unsigned level = templ->u.tex.level;
1542 unsigned width = u_minify(tex->width0, level);
1543 unsigned height = u_minify(tex->height0, level);
1544 unsigned width0 = tex->width0;
1545 unsigned height0 = tex->height0;
1546
1547 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1548 const struct util_format_description *tex_desc
1549 = util_format_description(tex->format);
1550 const struct util_format_description *templ_desc
1551 = util_format_description(templ->format);
1552
1553 assert(tex_desc->block.bits == templ_desc->block.bits);
1554
1555 /* Adjust size of surface if and only if the block width or
1556 * height is changed. */
1557 if (tex_desc->block.width != templ_desc->block.width ||
1558 tex_desc->block.height != templ_desc->block.height) {
1559 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1560 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1561
1562 width = nblks_x * templ_desc->block.width;
1563 height = nblks_y * templ_desc->block.height;
1564
1565 width0 = util_format_get_nblocksx(tex->format, width0);
1566 height0 = util_format_get_nblocksy(tex->format, height0);
1567 }
1568 }
1569
1570 return r600_create_surface_custom(pipe, tex, templ,
1571 width0, height0,
1572 width, height);
1573 }
1574
1575 static void r600_surface_destroy(struct pipe_context *pipe,
1576 struct pipe_surface *surface)
1577 {
1578 struct r600_surface *surf = (struct r600_surface*)surface;
1579 r600_resource_reference(&surf->cb_buffer_fmask, NULL);
1580 r600_resource_reference(&surf->cb_buffer_cmask, NULL);
1581 pipe_resource_reference(&surface->texture, NULL);
1582 FREE(surface);
1583 }
1584
1585 static void r600_clear_texture(struct pipe_context *pipe,
1586 struct pipe_resource *tex,
1587 unsigned level,
1588 const struct pipe_box *box,
1589 const void *data)
1590 {
1591 struct pipe_screen *screen = pipe->screen;
1592 struct r600_texture *rtex = (struct r600_texture*)tex;
1593 struct pipe_surface tmpl = {{0}};
1594 struct pipe_surface *sf;
1595 const struct util_format_description *desc =
1596 util_format_description(tex->format);
1597
1598 tmpl.format = tex->format;
1599 tmpl.u.tex.first_layer = box->z;
1600 tmpl.u.tex.last_layer = box->z + box->depth - 1;
1601 tmpl.u.tex.level = level;
1602 sf = pipe->create_surface(pipe, tex, &tmpl);
1603 if (!sf)
1604 return;
1605
1606 if (rtex->is_depth) {
1607 unsigned clear;
1608 float depth;
1609 uint8_t stencil = 0;
1610
1611 /* Depth is always present. */
1612 clear = PIPE_CLEAR_DEPTH;
1613 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
1614
1615 if (rtex->surface.has_stencil) {
1616 clear |= PIPE_CLEAR_STENCIL;
1617 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
1618 }
1619
1620 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
1621 box->x, box->y,
1622 box->width, box->height, false);
1623 } else {
1624 union pipe_color_union color;
1625
1626 /* pipe_color_union requires the full vec4 representation. */
1627 if (util_format_is_pure_uint(tex->format))
1628 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
1629 else if (util_format_is_pure_sint(tex->format))
1630 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
1631 else
1632 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
1633
1634 if (screen->is_format_supported(screen, tex->format,
1635 tex->target, 0,
1636 PIPE_BIND_RENDER_TARGET)) {
1637 pipe->clear_render_target(pipe, sf, &color,
1638 box->x, box->y,
1639 box->width, box->height, false);
1640 } else {
1641 /* Software fallback - just for R9G9B9E5_FLOAT */
1642 util_clear_render_target(pipe, sf, &color,
1643 box->x, box->y,
1644 box->width, box->height);
1645 }
1646 }
1647 pipe_surface_reference(&sf, NULL);
1648 }
1649
1650 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1651 {
1652 const struct util_format_description *desc = util_format_description(format);
1653
1654 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1655
1656 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1657 return V_0280A0_SWAP_STD;
1658
1659 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1660 return ~0U;
1661
1662 switch (desc->nr_channels) {
1663 case 1:
1664 if (HAS_SWIZZLE(0,X))
1665 return V_0280A0_SWAP_STD; /* X___ */
1666 else if (HAS_SWIZZLE(3,X))
1667 return V_0280A0_SWAP_ALT_REV; /* ___X */
1668 break;
1669 case 2:
1670 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1671 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1672 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1673 return V_0280A0_SWAP_STD; /* XY__ */
1674 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1675 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1676 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1677 /* YX__ */
1678 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1679 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1680 return V_0280A0_SWAP_ALT; /* X__Y */
1681 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1682 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1683 break;
1684 case 3:
1685 if (HAS_SWIZZLE(0,X))
1686 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1687 else if (HAS_SWIZZLE(0,Z))
1688 return V_0280A0_SWAP_STD_REV; /* ZYX */
1689 break;
1690 case 4:
1691 /* check the middle channels, the 1st and 4th channel can be NONE */
1692 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1693 return V_0280A0_SWAP_STD; /* XYZW */
1694 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1695 return V_0280A0_SWAP_STD_REV; /* WZYX */
1696 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1697 return V_0280A0_SWAP_ALT; /* ZYXW */
1698 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1699 /* YZWX */
1700 if (desc->is_array)
1701 return V_0280A0_SWAP_ALT_REV;
1702 else
1703 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1704 }
1705 break;
1706 }
1707 return ~0U;
1708 }
1709
1710 /* FAST COLOR CLEAR */
1711
1712 static void evergreen_set_clear_color(struct r600_texture *rtex,
1713 enum pipe_format surface_format,
1714 const union pipe_color_union *color)
1715 {
1716 union util_color uc;
1717
1718 memset(&uc, 0, sizeof(uc));
1719
1720 if (rtex->surface.bpe == 16) {
1721 /* DCC fast clear only:
1722 * CLEAR_WORD0 = R = G = B
1723 * CLEAR_WORD1 = A
1724 */
1725 assert(color->ui[0] == color->ui[1] &&
1726 color->ui[0] == color->ui[2]);
1727 uc.ui[0] = color->ui[0];
1728 uc.ui[1] = color->ui[3];
1729 } else if (util_format_is_pure_uint(surface_format)) {
1730 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1731 } else if (util_format_is_pure_sint(surface_format)) {
1732 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1733 } else {
1734 util_pack_color(color->f, surface_format, &uc);
1735 }
1736
1737 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1738 }
1739
1740 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1741 struct pipe_framebuffer_state *fb,
1742 struct r600_atom *fb_state,
1743 unsigned *buffers, ubyte *dirty_cbufs,
1744 const union pipe_color_union *color)
1745 {
1746 int i;
1747
1748 /* This function is broken in BE, so just disable this path for now */
1749 #ifdef PIPE_ARCH_BIG_ENDIAN
1750 return;
1751 #endif
1752
1753 if (rctx->render_cond)
1754 return;
1755
1756 for (i = 0; i < fb->nr_cbufs; i++) {
1757 struct r600_texture *tex;
1758 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1759
1760 if (!fb->cbufs[i])
1761 continue;
1762
1763 /* if this colorbuffer is not being cleared */
1764 if (!(*buffers & clear_bit))
1765 continue;
1766
1767 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1768
1769 /* the clear is allowed if all layers are bound */
1770 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1771 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1772 continue;
1773 }
1774
1775 /* cannot clear mipmapped textures */
1776 if (fb->cbufs[i]->texture->last_level != 0) {
1777 continue;
1778 }
1779
1780 /* only supported on tiled surfaces */
1781 if (tex->surface.is_linear) {
1782 continue;
1783 }
1784
1785 /* shared textures can't use fast clear without an explicit flush,
1786 * because there is no way to communicate the clear color among
1787 * all clients
1788 */
1789 if (tex->resource.b.is_shared &&
1790 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1791 continue;
1792
1793 {
1794 /* 128-bit formats are unusupported */
1795 if (tex->surface.bpe > 8) {
1796 continue;
1797 }
1798
1799 /* ensure CMASK is enabled */
1800 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1801 if (tex->cmask.size == 0) {
1802 continue;
1803 }
1804
1805 /* Do the fast clear. */
1806 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1807 tex->cmask.offset, tex->cmask.size, 0,
1808 R600_COHERENCY_CB_META);
1809
1810 bool need_compressed_update = !tex->dirty_level_mask;
1811
1812 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1813
1814 if (need_compressed_update)
1815 p_atomic_inc(&rctx->screen->compressed_colortex_counter);
1816 }
1817
1818 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1819
1820 if (dirty_cbufs)
1821 *dirty_cbufs |= 1 << i;
1822 rctx->set_atom_dirty(rctx, fb_state, true);
1823 *buffers &= ~clear_bit;
1824 }
1825 }
1826
1827 static struct pipe_memory_object *
1828 r600_memobj_from_handle(struct pipe_screen *screen,
1829 struct winsys_handle *whandle,
1830 bool dedicated)
1831 {
1832 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1833 struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
1834 struct pb_buffer *buf = NULL;
1835 uint32_t stride, offset;
1836
1837 if (!memobj)
1838 return NULL;
1839
1840 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1841 &stride, &offset);
1842 if (!buf) {
1843 free(memobj);
1844 return NULL;
1845 }
1846
1847 memobj->b.dedicated = dedicated;
1848 memobj->buf = buf;
1849 memobj->stride = stride;
1850 memobj->offset = offset;
1851
1852 return (struct pipe_memory_object *)memobj;
1853
1854 }
1855
1856 static void
1857 r600_memobj_destroy(struct pipe_screen *screen,
1858 struct pipe_memory_object *_memobj)
1859 {
1860 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1861
1862 pb_reference(&memobj->buf, NULL);
1863 free(memobj);
1864 }
1865
1866 static struct pipe_resource *
1867 r600_texture_from_memobj(struct pipe_screen *screen,
1868 const struct pipe_resource *templ,
1869 struct pipe_memory_object *_memobj,
1870 uint64_t offset)
1871 {
1872 int r;
1873 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1874 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1875 struct r600_texture *rtex;
1876 struct radeon_surf surface = {};
1877 struct radeon_bo_metadata metadata = {};
1878 enum radeon_surf_mode array_mode;
1879 bool is_scanout;
1880 struct pb_buffer *buf = NULL;
1881
1882 if (memobj->b.dedicated) {
1883 rscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
1884 r600_surface_import_metadata(rscreen, &surface, &metadata,
1885 &array_mode, &is_scanout);
1886 } else {
1887 /**
1888 * The bo metadata is unset for un-dedicated images. So we fall
1889 * back to linear. See answer to question 5 of the
1890 * VK_KHX_external_memory spec for some details.
1891 *
1892 * It is possible that this case isn't going to work if the
1893 * surface pitch isn't correctly aligned by default.
1894 *
1895 * In order to support it correctly we require multi-image
1896 * metadata to be syncrhonized between radv and radeonsi. The
1897 * semantics of associating multiple image metadata to a memory
1898 * object on the vulkan export side are not concretely defined
1899 * either.
1900 *
1901 * All the use cases we are aware of at the moment for memory
1902 * objects use dedicated allocations. So lets keep the initial
1903 * implementation simple.
1904 *
1905 * A possible alternative is to attempt to reconstruct the
1906 * tiling information when the TexParameter TEXTURE_TILING_EXT
1907 * is set.
1908 */
1909 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1910 is_scanout = false;
1911
1912 }
1913
1914 r = r600_init_surface(rscreen, &surface, templ,
1915 array_mode, memobj->stride,
1916 offset, true, is_scanout,
1917 false);
1918 if (r)
1919 return NULL;
1920
1921 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
1922 if (!rtex)
1923 return NULL;
1924
1925 /* r600_texture_create_object doesn't increment refcount of
1926 * memobj->buf, so increment it here.
1927 */
1928 pb_reference(&buf, memobj->buf);
1929
1930 rtex->resource.b.is_shared = true;
1931 rtex->resource.external_usage = PIPE_HANDLE_USAGE_READ_WRITE;
1932
1933 if (rscreen->apply_opaque_metadata)
1934 rscreen->apply_opaque_metadata(rscreen, rtex, &metadata);
1935
1936 return &rtex->resource.b.b;
1937 }
1938
1939 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1940 {
1941 rscreen->b.resource_from_handle = r600_texture_from_handle;
1942 rscreen->b.resource_get_handle = r600_texture_get_handle;
1943 rscreen->b.resource_from_memobj = r600_texture_from_memobj;
1944 rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
1945 rscreen->b.memobj_destroy = r600_memobj_destroy;
1946 }
1947
1948 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1949 {
1950 rctx->b.create_surface = r600_create_surface;
1951 rctx->b.surface_destroy = r600_surface_destroy;
1952 rctx->b.clear_texture = r600_clear_texture;
1953 }