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[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
36 #include "state_tracker/winsys_handle.h"
37 #include <errno.h>
38 #include <inttypes.h>
39
40 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
41 struct r600_texture *rtex);
42 static enum radeon_surf_mode
43 r600_choose_tiling(struct r600_common_screen *rscreen,
44 const struct pipe_resource *templ);
45
46
47 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
48 struct r600_texture *rdst,
49 unsigned dst_level, unsigned dstx,
50 unsigned dsty, unsigned dstz,
51 struct r600_texture *rsrc,
52 unsigned src_level,
53 const struct pipe_box *src_box)
54 {
55 if (!rctx->dma.cs)
56 return false;
57
58 if (rdst->surface.bpe != rsrc->surface.bpe)
59 return false;
60
61 /* MSAA: Blits don't exist in the real world. */
62 if (rsrc->resource.b.b.nr_samples > 1 ||
63 rdst->resource.b.b.nr_samples > 1)
64 return false;
65
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
69 */
70 if (rsrc->is_depth || rdst->is_depth)
71 return false;
72
73 /* CMASK as:
74 * src: Both texture and SDMA paths need decompression. Use SDMA.
75 * dst: If overwriting the whole texture, discard CMASK and use
76 * SDMA. Otherwise, use the 3D path.
77 */
78 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
79 /* The CMASK clear is only enabled for the first level. */
80 assert(dst_level == 0);
81 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
82 dstx, dsty, dstz, src_box->width,
83 src_box->height, src_box->depth))
84 return false;
85
86 r600_texture_discard_cmask(rctx->screen, rdst);
87 }
88
89 /* All requirements are met. Prepare textures for SDMA. */
90 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
91 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
92
93 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
94 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
95
96 return true;
97 }
98
99 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
100 static void r600_copy_region_with_blit(struct pipe_context *pipe,
101 struct pipe_resource *dst,
102 unsigned dst_level,
103 unsigned dstx, unsigned dsty, unsigned dstz,
104 struct pipe_resource *src,
105 unsigned src_level,
106 const struct pipe_box *src_box)
107 {
108 struct pipe_blit_info blit;
109
110 memset(&blit, 0, sizeof(blit));
111 blit.src.resource = src;
112 blit.src.format = src->format;
113 blit.src.level = src_level;
114 blit.src.box = *src_box;
115 blit.dst.resource = dst;
116 blit.dst.format = dst->format;
117 blit.dst.level = dst_level;
118 blit.dst.box.x = dstx;
119 blit.dst.box.y = dsty;
120 blit.dst.box.z = dstz;
121 blit.dst.box.width = src_box->width;
122 blit.dst.box.height = src_box->height;
123 blit.dst.box.depth = src_box->depth;
124 blit.mask = util_format_get_mask(src->format) &
125 util_format_get_mask(dst->format);
126 blit.filter = PIPE_TEX_FILTER_NEAREST;
127
128 if (blit.mask) {
129 pipe->blit(pipe, &blit);
130 }
131 }
132
133 /* Copy from a full GPU texture to a transfer's staging one. */
134 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
135 {
136 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
137 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
138 struct pipe_resource *dst = &rtransfer->staging->b.b;
139 struct pipe_resource *src = transfer->resource;
140
141 if (src->nr_samples > 1) {
142 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
143 src, transfer->level, &transfer->box);
144 return;
145 }
146
147 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
148 &transfer->box);
149 }
150
151 /* Copy from a transfer's staging texture to a full GPU one. */
152 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
153 {
154 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
155 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
156 struct pipe_resource *dst = transfer->resource;
157 struct pipe_resource *src = &rtransfer->staging->b.b;
158 struct pipe_box sbox;
159
160 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
161
162 if (dst->nr_samples > 1) {
163 r600_copy_region_with_blit(ctx, dst, transfer->level,
164 transfer->box.x, transfer->box.y, transfer->box.z,
165 src, 0, &sbox);
166 return;
167 }
168
169 rctx->dma_copy(ctx, dst, transfer->level,
170 transfer->box.x, transfer->box.y, transfer->box.z,
171 src, 0, &sbox);
172 }
173
174 static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
175 struct r600_texture *rtex, unsigned level,
176 const struct pipe_box *box,
177 unsigned *stride,
178 unsigned *layer_stride)
179 {
180 *stride = rtex->surface.u.legacy.level[level].nblk_x *
181 rtex->surface.bpe;
182 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
183 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
184
185 if (!box)
186 return rtex->surface.u.legacy.level[level].offset;
187
188 /* Each texture is an array of mipmap levels. Each level is
189 * an array of slices. */
190 return rtex->surface.u.legacy.level[level].offset +
191 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
192 (box->y / rtex->surface.blk_h *
193 rtex->surface.u.legacy.level[level].nblk_x +
194 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
195 }
196
197 static int r600_init_surface(struct r600_common_screen *rscreen,
198 struct radeon_surf *surface,
199 const struct pipe_resource *ptex,
200 enum radeon_surf_mode array_mode,
201 unsigned pitch_in_bytes_override,
202 unsigned offset,
203 bool is_imported,
204 bool is_scanout,
205 bool is_flushed_depth)
206 {
207 const struct util_format_description *desc =
208 util_format_description(ptex->format);
209 bool is_depth, is_stencil;
210 int r;
211 unsigned i, bpe, flags = 0;
212
213 is_depth = util_format_has_depth(desc);
214 is_stencil = util_format_has_stencil(desc);
215
216 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
217 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
218 bpe = 4; /* stencil is allocated separately on evergreen */
219 } else {
220 bpe = util_format_get_blocksize(ptex->format);
221 assert(util_is_power_of_two_or_zero(bpe));
222 }
223
224 if (!is_flushed_depth && is_depth) {
225 flags |= RADEON_SURF_ZBUFFER;
226
227 if (is_stencil)
228 flags |= RADEON_SURF_SBUFFER;
229 }
230
231 if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
232 /* This should catch bugs in gallium users setting incorrect flags. */
233 assert(ptex->nr_samples <= 1 &&
234 ptex->array_size == 1 &&
235 ptex->depth0 == 1 &&
236 ptex->last_level == 0 &&
237 !(flags & RADEON_SURF_Z_OR_SBUFFER));
238
239 flags |= RADEON_SURF_SCANOUT;
240 }
241
242 if (ptex->bind & PIPE_BIND_SHARED)
243 flags |= RADEON_SURF_SHAREABLE;
244 if (is_imported)
245 flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
246 if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
247 flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
248
249 r = rscreen->ws->surface_init(rscreen->ws, ptex,
250 flags, bpe, array_mode, surface);
251 if (r) {
252 return r;
253 }
254
255 if (pitch_in_bytes_override &&
256 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
257 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
258 * for those
259 */
260 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
261 surface->u.legacy.level[0].slice_size_dw =
262 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4;
263 }
264
265 if (offset) {
266 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
267 surface->u.legacy.level[i].offset += offset;
268 }
269
270 return 0;
271 }
272
273 static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
274 struct r600_texture *rtex,
275 struct radeon_bo_metadata *metadata)
276 {
277 struct radeon_surf *surface = &rtex->surface;
278
279 memset(metadata, 0, sizeof(*metadata));
280
281 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
282 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
283 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
284 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
285 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
286 metadata->u.legacy.bankw = surface->u.legacy.bankw;
287 metadata->u.legacy.bankh = surface->u.legacy.bankh;
288 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
289 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
290 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
291 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
292 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
293 }
294
295 static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
296 struct radeon_surf *surf,
297 struct radeon_bo_metadata *metadata,
298 enum radeon_surf_mode *array_mode,
299 bool *is_scanout)
300 {
301 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
302 surf->u.legacy.bankw = metadata->u.legacy.bankw;
303 surf->u.legacy.bankh = metadata->u.legacy.bankh;
304 surf->u.legacy.tile_split = metadata->u.legacy.tile_split;
305 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
306 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
307
308 if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED)
309 *array_mode = RADEON_SURF_MODE_2D;
310 else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
311 *array_mode = RADEON_SURF_MODE_1D;
312 else
313 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
314
315 *is_scanout = metadata->u.legacy.scanout;
316 }
317
318 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
319 struct r600_texture *rtex)
320 {
321 struct r600_common_screen *rscreen = rctx->screen;
322 struct pipe_context *ctx = &rctx->b;
323
324 if (ctx == rscreen->aux_context)
325 mtx_lock(&rscreen->aux_context_lock);
326
327 ctx->flush_resource(ctx, &rtex->resource.b.b);
328 ctx->flush(ctx, NULL, 0);
329
330 if (ctx == rscreen->aux_context)
331 mtx_unlock(&rscreen->aux_context_lock);
332 }
333
334 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
335 struct r600_texture *rtex)
336 {
337 if (!rtex->cmask.size)
338 return;
339
340 assert(rtex->resource.b.b.nr_samples <= 1);
341
342 /* Disable CMASK. */
343 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
344 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
345 rtex->dirty_level_mask = 0;
346
347 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
348
349 if (rtex->cmask_buffer != &rtex->resource)
350 r600_resource_reference(&rtex->cmask_buffer, NULL);
351
352 /* Notify all contexts about the change. */
353 p_atomic_inc(&rscreen->dirty_tex_counter);
354 p_atomic_inc(&rscreen->compressed_colortex_counter);
355 }
356
357 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
358 struct r600_texture *rtex,
359 unsigned new_bind_flag,
360 bool invalidate_storage)
361 {
362 struct pipe_screen *screen = rctx->b.screen;
363 struct r600_texture *new_tex;
364 struct pipe_resource templ = rtex->resource.b.b;
365 unsigned i;
366
367 templ.bind |= new_bind_flag;
368
369 /* r600g doesn't react to dirty_tex_descriptor_counter */
370 if (rctx->chip_class < GFX6)
371 return;
372
373 if (rtex->resource.b.is_shared)
374 return;
375
376 if (new_bind_flag == PIPE_BIND_LINEAR) {
377 if (rtex->surface.is_linear)
378 return;
379
380 /* This fails with MSAA, depth, and compressed textures. */
381 if (r600_choose_tiling(rctx->screen, &templ) !=
382 RADEON_SURF_MODE_LINEAR_ALIGNED)
383 return;
384 }
385
386 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
387 if (!new_tex)
388 return;
389
390 /* Copy the pixels to the new texture. */
391 if (!invalidate_storage) {
392 for (i = 0; i <= templ.last_level; i++) {
393 struct pipe_box box;
394
395 u_box_3d(0, 0, 0,
396 u_minify(templ.width0, i), u_minify(templ.height0, i),
397 util_num_layers(&templ, i), &box);
398
399 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
400 &rtex->resource.b.b, i, &box);
401 }
402 }
403
404 if (new_bind_flag == PIPE_BIND_LINEAR) {
405 r600_texture_discard_cmask(rctx->screen, rtex);
406 }
407
408 /* Replace the structure fields of rtex. */
409 rtex->resource.b.b.bind = templ.bind;
410 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
411 rtex->resource.gpu_address = new_tex->resource.gpu_address;
412 rtex->resource.vram_usage = new_tex->resource.vram_usage;
413 rtex->resource.gart_usage = new_tex->resource.gart_usage;
414 rtex->resource.bo_size = new_tex->resource.bo_size;
415 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
416 rtex->resource.domains = new_tex->resource.domains;
417 rtex->resource.flags = new_tex->resource.flags;
418 rtex->size = new_tex->size;
419 rtex->db_render_format = new_tex->db_render_format;
420 rtex->db_compatible = new_tex->db_compatible;
421 rtex->can_sample_z = new_tex->can_sample_z;
422 rtex->can_sample_s = new_tex->can_sample_s;
423 rtex->surface = new_tex->surface;
424 rtex->fmask = new_tex->fmask;
425 rtex->cmask = new_tex->cmask;
426 rtex->cb_color_info = new_tex->cb_color_info;
427 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
428 rtex->htile_offset = new_tex->htile_offset;
429 rtex->depth_cleared = new_tex->depth_cleared;
430 rtex->stencil_cleared = new_tex->stencil_cleared;
431 rtex->non_disp_tiling = new_tex->non_disp_tiling;
432 rtex->framebuffers_bound = new_tex->framebuffers_bound;
433
434 if (new_bind_flag == PIPE_BIND_LINEAR) {
435 assert(!rtex->htile_offset);
436 assert(!rtex->cmask.size);
437 assert(!rtex->fmask.size);
438 assert(!rtex->is_depth);
439 }
440
441 r600_texture_reference(&new_tex, NULL);
442
443 p_atomic_inc(&rctx->screen->dirty_tex_counter);
444 }
445
446 static void r600_texture_get_info(struct pipe_screen* screen,
447 struct pipe_resource *resource,
448 unsigned *pstride,
449 unsigned *poffset)
450 {
451 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
452 struct r600_texture *rtex = (struct r600_texture*)resource;
453 unsigned stride = 0;
454 unsigned offset = 0;
455
456 if (!rscreen || !rtex)
457 return;
458
459 if (resource->target != PIPE_BUFFER) {
460 offset = rtex->surface.u.legacy.level[0].offset;
461 stride = rtex->surface.u.legacy.level[0].nblk_x *
462 rtex->surface.bpe;
463 }
464
465 if (pstride)
466 *pstride = stride;
467
468 if (poffset)
469 *poffset = offset;
470 }
471
472 static bool r600_texture_get_handle(struct pipe_screen* screen,
473 struct pipe_context *ctx,
474 struct pipe_resource *resource,
475 struct winsys_handle *whandle,
476 unsigned usage)
477 {
478 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
479 struct r600_common_context *rctx;
480 struct r600_resource *res = (struct r600_resource*)resource;
481 struct r600_texture *rtex = (struct r600_texture*)resource;
482 struct radeon_bo_metadata metadata;
483 bool update_metadata = false;
484 unsigned stride, offset, slice_size;
485
486 ctx = threaded_context_unwrap_sync(ctx);
487 rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
488
489 if (resource->target != PIPE_BUFFER) {
490 /* This is not supported now, but it might be required for OpenCL
491 * interop in the future.
492 */
493 if (resource->nr_samples > 1 || rtex->is_depth)
494 return false;
495
496 /* Move a suballocated texture into a non-suballocated allocation. */
497 if (rscreen->ws->buffer_is_suballocated(res->buf) ||
498 rtex->surface.tile_swizzle) {
499 assert(!res->b.is_shared);
500 r600_reallocate_texture_inplace(rctx, rtex,
501 PIPE_BIND_SHARED, false);
502 rctx->b.flush(&rctx->b, NULL, 0);
503 assert(res->b.b.bind & PIPE_BIND_SHARED);
504 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
505 assert(rtex->surface.tile_swizzle == 0);
506 }
507
508 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
509 rtex->cmask.size) {
510 /* Eliminate fast clear (CMASK) */
511 r600_eliminate_fast_color_clear(rctx, rtex);
512
513 /* Disable CMASK if flush_resource isn't going
514 * to be called.
515 */
516 if (rtex->cmask.size)
517 r600_texture_discard_cmask(rscreen, rtex);
518 }
519
520 /* Set metadata. */
521 if (!res->b.is_shared || update_metadata) {
522 r600_texture_init_metadata(rscreen, rtex, &metadata);
523
524 rscreen->ws->buffer_set_metadata(res->buf, &metadata);
525 }
526
527 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
528 } else {
529 /* Move a suballocated buffer into a non-suballocated allocation. */
530 if (rscreen->ws->buffer_is_suballocated(res->buf)) {
531 assert(!res->b.is_shared);
532
533 /* Allocate a new buffer with PIPE_BIND_SHARED. */
534 struct pipe_resource templ = res->b.b;
535 templ.bind |= PIPE_BIND_SHARED;
536
537 struct pipe_resource *newb =
538 screen->resource_create(screen, &templ);
539 if (!newb)
540 return false;
541
542 /* Copy the old buffer contents to the new one. */
543 struct pipe_box box;
544 u_box_1d(0, newb->width0, &box);
545 rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
546 &res->b.b, 0, &box);
547 /* Move the new buffer storage to the old pipe_resource. */
548 r600_replace_buffer_storage(&rctx->b, &res->b.b, newb);
549 pipe_resource_reference(&newb, NULL);
550
551 assert(res->b.b.bind & PIPE_BIND_SHARED);
552 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
553 }
554
555 /* Buffers */
556 slice_size = 0;
557 }
558
559 r600_texture_get_info(screen, resource, &stride, &offset);
560
561 if (res->b.is_shared) {
562 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
563 * doesn't set it.
564 */
565 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
566 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
567 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
568 } else {
569 res->b.is_shared = true;
570 res->external_usage = usage;
571 }
572
573 whandle->stride = stride;
574 whandle->offset = offset + slice_size * whandle->layer;
575
576 return rscreen->ws->buffer_get_handle(rscreen->ws, res->buf, whandle);
577 }
578
579 static void r600_texture_destroy(struct pipe_screen *screen,
580 struct pipe_resource *ptex)
581 {
582 struct r600_texture *rtex = (struct r600_texture*)ptex;
583 struct r600_resource *resource = &rtex->resource;
584
585 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
586 pipe_resource_reference((struct pipe_resource**)&resource->immed_buffer, NULL);
587
588 if (rtex->cmask_buffer != &rtex->resource) {
589 r600_resource_reference(&rtex->cmask_buffer, NULL);
590 }
591 pb_reference(&resource->buf, NULL);
592 FREE(rtex);
593 }
594
595 static const struct u_resource_vtbl r600_texture_vtbl;
596
597 /* The number of samples can be specified independently of the texture. */
598 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
599 struct r600_texture *rtex,
600 unsigned nr_samples,
601 struct r600_fmask_info *out)
602 {
603 /* FMASK is allocated like an ordinary texture. */
604 struct pipe_resource templ = rtex->resource.b.b;
605 struct radeon_surf fmask = {};
606 unsigned flags, bpe;
607
608 memset(out, 0, sizeof(*out));
609
610 templ.nr_samples = 1;
611 flags = rtex->surface.flags | RADEON_SURF_FMASK;
612
613 /* Use the same parameters and tile mode. */
614 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
615 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
616 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
617 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
618
619 if (nr_samples <= 4)
620 fmask.u.legacy.bankh = 4;
621
622 switch (nr_samples) {
623 case 2:
624 case 4:
625 bpe = 1;
626 break;
627 case 8:
628 bpe = 4;
629 break;
630 default:
631 R600_ERR("Invalid sample count for FMASK allocation.\n");
632 return;
633 }
634
635 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
636 * This can be fixed by writing a separate FMASK allocator specifically
637 * for R600-R700 asics. */
638 if (rscreen->chip_class <= R700) {
639 bpe *= 2;
640 }
641
642 if (rscreen->ws->surface_init(rscreen->ws, &templ,
643 flags, bpe, RADEON_SURF_MODE_2D, &fmask)) {
644 R600_ERR("Got error in surface_init while allocating FMASK.\n");
645 return;
646 }
647
648 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
649
650 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
651 if (out->slice_tile_max)
652 out->slice_tile_max -= 1;
653
654 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
655 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
656 out->bank_height = fmask.u.legacy.bankh;
657 out->tile_swizzle = fmask.tile_swizzle;
658 out->alignment = MAX2(256, fmask.surf_alignment);
659 out->size = fmask.surf_size;
660 }
661
662 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
663 struct r600_texture *rtex)
664 {
665 r600_texture_get_fmask_info(rscreen, rtex,
666 rtex->resource.b.b.nr_samples, &rtex->fmask);
667
668 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
669 rtex->size = rtex->fmask.offset + rtex->fmask.size;
670 }
671
672 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
673 struct r600_texture *rtex,
674 struct r600_cmask_info *out)
675 {
676 unsigned cmask_tile_width = 8;
677 unsigned cmask_tile_height = 8;
678 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
679 unsigned element_bits = 4;
680 unsigned cmask_cache_bits = 1024;
681 unsigned num_pipes = rscreen->info.num_tile_pipes;
682 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
683
684 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
685 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
686 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
687 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
688 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
689
690 unsigned pitch_elements = align(rtex->resource.b.b.width0, macro_tile_width);
691 unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
692
693 unsigned base_align = num_pipes * pipe_interleave_bytes;
694 unsigned slice_bytes =
695 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
696
697 assert(macro_tile_width % 128 == 0);
698 assert(macro_tile_height % 128 == 0);
699
700 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
701 out->alignment = MAX2(256, base_align);
702 out->size = util_num_layers(&rtex->resource.b.b, 0) *
703 align(slice_bytes, base_align);
704 }
705
706 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
707 struct r600_texture *rtex)
708 {
709 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
710
711 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
712 rtex->size = rtex->cmask.offset + rtex->cmask.size;
713
714 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
715 }
716
717 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
718 struct r600_texture *rtex)
719 {
720 if (rtex->cmask_buffer)
721 return;
722
723 assert(rtex->cmask.size == 0);
724
725 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
726
727 rtex->cmask_buffer = (struct r600_resource *)
728 r600_aligned_buffer_create(&rscreen->b,
729 R600_RESOURCE_FLAG_UNMAPPABLE,
730 PIPE_USAGE_DEFAULT,
731 rtex->cmask.size,
732 rtex->cmask.alignment);
733 if (rtex->cmask_buffer == NULL) {
734 rtex->cmask.size = 0;
735 return;
736 }
737
738 /* update colorbuffer state bits */
739 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
740
741 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
742
743 p_atomic_inc(&rscreen->compressed_colortex_counter);
744 }
745
746 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
747 struct r600_resource *res,
748 unsigned immed_size)
749 {
750 res->immed_buffer = (struct r600_resource *)
751 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
752 PIPE_USAGE_DEFAULT, immed_size);
753 }
754
755 static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
756 struct r600_texture *rtex)
757 {
758 unsigned cl_width, cl_height, width, height;
759 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
760 unsigned num_pipes = rscreen->info.num_tile_pipes;
761
762 rtex->surface.htile_size = 0;
763
764 if (rscreen->chip_class <= EVERGREEN &&
765 rscreen->info.drm_minor < 26)
766 return;
767
768 /* HW bug on R6xx. */
769 if (rscreen->chip_class == R600 &&
770 (rtex->resource.b.b.width0 > 7680 ||
771 rtex->resource.b.b.height0 > 7680))
772 return;
773
774 switch (num_pipes) {
775 case 1:
776 cl_width = 32;
777 cl_height = 16;
778 break;
779 case 2:
780 cl_width = 32;
781 cl_height = 32;
782 break;
783 case 4:
784 cl_width = 64;
785 cl_height = 32;
786 break;
787 case 8:
788 cl_width = 64;
789 cl_height = 64;
790 break;
791 case 16:
792 cl_width = 128;
793 cl_height = 64;
794 break;
795 default:
796 assert(0);
797 return;
798 }
799
800 width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
801 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
802
803 slice_elements = (width * height) / (8 * 8);
804 slice_bytes = slice_elements * 4;
805
806 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
807 base_align = num_pipes * pipe_interleave_bytes;
808
809 rtex->surface.htile_alignment = base_align;
810 rtex->surface.htile_size =
811 util_num_layers(&rtex->resource.b.b, 0) *
812 align(slice_bytes, base_align);
813 }
814
815 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
816 struct r600_texture *rtex)
817 {
818 r600_texture_get_htile_size(rscreen, rtex);
819
820 if (!rtex->surface.htile_size)
821 return;
822
823 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
824 rtex->size = rtex->htile_offset + rtex->surface.htile_size;
825 }
826
827 void r600_print_texture_info(struct r600_common_screen *rscreen,
828 struct r600_texture *rtex, struct u_log_context *log)
829 {
830 int i;
831
832 /* Common parameters. */
833 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
834 "blk_h=%u, array_size=%u, last_level=%u, "
835 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
836 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
837 rtex->resource.b.b.depth0, rtex->surface.blk_w,
838 rtex->surface.blk_h,
839 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
840 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
841 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
842
843 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
844 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
845 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
846 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
847 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
848 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
849
850 if (rtex->fmask.size)
851 u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
852 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
853 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
854 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
855 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
856
857 if (rtex->cmask.size)
858 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
859 "slice_tile_max=%u\n",
860 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
861 rtex->cmask.slice_tile_max);
862
863 if (rtex->htile_offset)
864 u_log_printf(log, " HTile: offset=%"PRIu64", size=%u "
865 "alignment=%u\n",
866 rtex->htile_offset, rtex->surface.htile_size,
867 rtex->surface.htile_alignment);
868
869 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
870 u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
871 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
872 "mode=%u, tiling_index = %u\n",
873 i, rtex->surface.u.legacy.level[i].offset,
874 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
875 u_minify(rtex->resource.b.b.width0, i),
876 u_minify(rtex->resource.b.b.height0, i),
877 u_minify(rtex->resource.b.b.depth0, i),
878 rtex->surface.u.legacy.level[i].nblk_x,
879 rtex->surface.u.legacy.level[i].nblk_y,
880 rtex->surface.u.legacy.level[i].mode,
881 rtex->surface.u.legacy.tiling_index[i]);
882
883 if (rtex->surface.has_stencil) {
884 u_log_printf(log, " StencilLayout: tilesplit=%u\n",
885 rtex->surface.u.legacy.stencil_tile_split);
886 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
887 u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
888 "slice_size=%"PRIu64", npix_x=%u, "
889 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
890 "mode=%u, tiling_index = %u\n",
891 i, rtex->surface.u.legacy.stencil_level[i].offset,
892 (uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4,
893 u_minify(rtex->resource.b.b.width0, i),
894 u_minify(rtex->resource.b.b.height0, i),
895 u_minify(rtex->resource.b.b.depth0, i),
896 rtex->surface.u.legacy.stencil_level[i].nblk_x,
897 rtex->surface.u.legacy.stencil_level[i].nblk_y,
898 rtex->surface.u.legacy.stencil_level[i].mode,
899 rtex->surface.u.legacy.stencil_tiling_index[i]);
900 }
901 }
902 }
903
904 /* Common processing for r600_texture_create and r600_texture_from_handle */
905 static struct r600_texture *
906 r600_texture_create_object(struct pipe_screen *screen,
907 const struct pipe_resource *base,
908 struct pb_buffer *buf,
909 struct radeon_surf *surface)
910 {
911 struct r600_texture *rtex;
912 struct r600_resource *resource;
913 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
914
915 rtex = CALLOC_STRUCT(r600_texture);
916 if (!rtex)
917 return NULL;
918
919 resource = &rtex->resource;
920 resource->b.b = *base;
921 resource->b.b.next = NULL;
922 resource->b.vtbl = &r600_texture_vtbl;
923 pipe_reference_init(&resource->b.b.reference, 1);
924 resource->b.b.screen = screen;
925
926 /* don't include stencil-only formats which we don't support for rendering */
927 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
928
929 rtex->surface = *surface;
930 rtex->size = rtex->surface.surf_size;
931 rtex->db_render_format = base->format;
932
933 /* Tiled depth textures utilize the non-displayable tile order.
934 * This must be done after r600_setup_surface.
935 * Applies to R600-Cayman. */
936 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
937 /* Applies to GCN. */
938 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
939
940 if (rtex->is_depth) {
941 if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
942 R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
943 rscreen->chip_class >= EVERGREEN) {
944 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
945 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
946 } else {
947 if (rtex->resource.b.b.nr_samples <= 1 &&
948 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
949 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT))
950 rtex->can_sample_z = true;
951 }
952
953 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
954 R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
955 rtex->db_compatible = true;
956
957 if (!(rscreen->debug_flags & DBG_NO_HYPERZ))
958 r600_texture_allocate_htile(rscreen, rtex);
959 }
960 } else {
961 if (base->nr_samples > 1) {
962 if (!buf) {
963 r600_texture_allocate_fmask(rscreen, rtex);
964 r600_texture_allocate_cmask(rscreen, rtex);
965 rtex->cmask_buffer = &rtex->resource;
966 }
967 if (!rtex->fmask.size || !rtex->cmask.size) {
968 FREE(rtex);
969 return NULL;
970 }
971 }
972 }
973
974 /* Now create the backing buffer. */
975 if (!buf) {
976 r600_init_resource_fields(rscreen, resource, rtex->size,
977 rtex->surface.surf_alignment);
978
979 if (!r600_alloc_resource(rscreen, resource)) {
980 FREE(rtex);
981 return NULL;
982 }
983 } else {
984 resource->buf = buf;
985 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
986 resource->bo_size = buf->size;
987 resource->bo_alignment = buf->alignment;
988 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
989 if (resource->domains & RADEON_DOMAIN_VRAM)
990 resource->vram_usage = buf->size;
991 else if (resource->domains & RADEON_DOMAIN_GTT)
992 resource->gart_usage = buf->size;
993 }
994
995 if (rtex->cmask.size) {
996 /* Initialize the cmask to 0xCC (= compressed state). */
997 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
998 rtex->cmask.offset, rtex->cmask.size,
999 0xCCCCCCCC);
1000 }
1001 if (rtex->htile_offset) {
1002 uint32_t clear_value = 0;
1003
1004 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
1005 rtex->htile_offset,
1006 rtex->surface.htile_size,
1007 clear_value);
1008 }
1009
1010 /* Initialize the CMASK base register value. */
1011 rtex->cmask.base_address_reg =
1012 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1013
1014 if (rscreen->debug_flags & DBG_VM) {
1015 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1016 rtex->resource.gpu_address,
1017 rtex->resource.gpu_address + rtex->resource.buf->size,
1018 base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
1019 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
1020 }
1021
1022 if (rscreen->debug_flags & DBG_TEX) {
1023 puts("Texture:");
1024 struct u_log_context log;
1025 u_log_context_init(&log);
1026 r600_print_texture_info(rscreen, rtex, &log);
1027 u_log_new_page_print(&log, stdout);
1028 fflush(stdout);
1029 u_log_context_destroy(&log);
1030 }
1031
1032 return rtex;
1033 }
1034
1035 static enum radeon_surf_mode
1036 r600_choose_tiling(struct r600_common_screen *rscreen,
1037 const struct pipe_resource *templ)
1038 {
1039 const struct util_format_description *desc = util_format_description(templ->format);
1040 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1041 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1042 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1043
1044 /* MSAA resources must be 2D tiled. */
1045 if (templ->nr_samples > 1)
1046 return RADEON_SURF_MODE_2D;
1047
1048 /* Transfer resources should be linear. */
1049 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1050 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1051
1052 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1053 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
1054 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
1055 (templ->target == PIPE_TEXTURE_2D ||
1056 templ->target == PIPE_TEXTURE_3D))
1057 force_tiling = true;
1058
1059 /* Handle common candidates for the linear mode.
1060 * Compressed textures and DB surfaces must always be tiled.
1061 */
1062 if (!force_tiling &&
1063 !is_depth_stencil &&
1064 !util_format_is_compressed(templ->format)) {
1065 if (rscreen->debug_flags & DBG_NO_TILING)
1066 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1067
1068 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1069 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1070 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1071
1072 if (templ->bind & PIPE_BIND_LINEAR)
1073 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1074
1075 /* 1D textures should be linear - fixes image operations on 1d */
1076 if (templ->target == PIPE_TEXTURE_1D ||
1077 templ->target == PIPE_TEXTURE_1D_ARRAY)
1078 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1079
1080 /* Textures likely to be mapped often. */
1081 if (templ->usage == PIPE_USAGE_STAGING ||
1082 templ->usage == PIPE_USAGE_STREAM)
1083 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1084 }
1085
1086 /* Make small textures 1D tiled. */
1087 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1088 (rscreen->debug_flags & DBG_NO_2D_TILING))
1089 return RADEON_SURF_MODE_1D;
1090
1091 /* The allocator will switch to 1D if needed. */
1092 return RADEON_SURF_MODE_2D;
1093 }
1094
1095 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
1096 const struct pipe_resource *templ)
1097 {
1098 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1099 struct radeon_surf surface = {0};
1100 bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1101 int r;
1102
1103 r = r600_init_surface(rscreen, &surface, templ,
1104 r600_choose_tiling(rscreen, templ), 0, 0,
1105 false, false, is_flushed_depth);
1106 if (r) {
1107 return NULL;
1108 }
1109
1110 return (struct pipe_resource *)
1111 r600_texture_create_object(screen, templ, NULL, &surface);
1112 }
1113
1114 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1115 const struct pipe_resource *templ,
1116 struct winsys_handle *whandle,
1117 unsigned usage)
1118 {
1119 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1120 struct pb_buffer *buf = NULL;
1121 enum radeon_surf_mode array_mode;
1122 struct radeon_surf surface = {};
1123 int r;
1124 struct radeon_bo_metadata metadata = {};
1125 struct r600_texture *rtex;
1126 bool is_scanout;
1127
1128 /* Support only 2D textures without mipmaps */
1129 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1130 templ->depth0 != 1 || templ->last_level != 0)
1131 return NULL;
1132
1133 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1134 rscreen->info.max_alignment);
1135 if (!buf)
1136 return NULL;
1137
1138 rscreen->ws->buffer_get_metadata(buf, &metadata);
1139 r600_surface_import_metadata(rscreen, &surface, &metadata,
1140 &array_mode, &is_scanout);
1141
1142 r = r600_init_surface(rscreen, &surface, templ, array_mode,
1143 whandle->stride, whandle->offset,
1144 true, is_scanout, false);
1145 if (r) {
1146 return NULL;
1147 }
1148
1149 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1150 if (!rtex)
1151 return NULL;
1152
1153 rtex->resource.b.is_shared = true;
1154 rtex->resource.external_usage = usage;
1155
1156 assert(rtex->surface.tile_swizzle == 0);
1157 return &rtex->resource.b.b;
1158 }
1159
1160 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1161 struct pipe_resource *texture,
1162 struct r600_texture **staging)
1163 {
1164 struct r600_texture *rtex = (struct r600_texture*)texture;
1165 struct pipe_resource resource;
1166 struct r600_texture **flushed_depth_texture = staging ?
1167 staging : &rtex->flushed_depth_texture;
1168 enum pipe_format pipe_format = texture->format;
1169
1170 if (!staging) {
1171 if (rtex->flushed_depth_texture)
1172 return true; /* it's ready */
1173
1174 if (!rtex->can_sample_z && rtex->can_sample_s) {
1175 switch (pipe_format) {
1176 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1177 /* Save memory by not allocating the S plane. */
1178 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1179 break;
1180 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1181 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1182 /* Save memory bandwidth by not copying the
1183 * stencil part during flush.
1184 *
1185 * This potentially increases memory bandwidth
1186 * if an application uses both Z and S texturing
1187 * simultaneously (a flushed Z24S8 texture
1188 * would be stored compactly), but how often
1189 * does that really happen?
1190 */
1191 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1192 break;
1193 default:;
1194 }
1195 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1196 assert(util_format_has_stencil(util_format_description(pipe_format)));
1197
1198 /* DB->CB copies to an 8bpp surface don't work. */
1199 pipe_format = PIPE_FORMAT_X24S8_UINT;
1200 }
1201 }
1202
1203 memset(&resource, 0, sizeof(resource));
1204 resource.target = texture->target;
1205 resource.format = pipe_format;
1206 resource.width0 = texture->width0;
1207 resource.height0 = texture->height0;
1208 resource.depth0 = texture->depth0;
1209 resource.array_size = texture->array_size;
1210 resource.last_level = texture->last_level;
1211 resource.nr_samples = texture->nr_samples;
1212 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1213 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1214 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1215
1216 if (staging)
1217 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1218
1219 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1220 if (*flushed_depth_texture == NULL) {
1221 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1222 return false;
1223 }
1224
1225 (*flushed_depth_texture)->non_disp_tiling = false;
1226 return true;
1227 }
1228
1229 /**
1230 * Initialize the pipe_resource descriptor to be of the same size as the box,
1231 * which is supposed to hold a subregion of the texture "orig" at the given
1232 * mipmap level.
1233 */
1234 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1235 struct pipe_resource *orig,
1236 const struct pipe_box *box,
1237 unsigned level, unsigned flags)
1238 {
1239 memset(res, 0, sizeof(*res));
1240 res->format = orig->format;
1241 res->width0 = box->width;
1242 res->height0 = box->height;
1243 res->depth0 = 1;
1244 res->array_size = 1;
1245 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1246 res->flags = flags;
1247
1248 /* We must set the correct texture target and dimensions for a 3D box. */
1249 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1250 res->target = PIPE_TEXTURE_2D_ARRAY;
1251 res->array_size = box->depth;
1252 } else {
1253 res->target = PIPE_TEXTURE_2D;
1254 }
1255 }
1256
1257 static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
1258 struct r600_texture *rtex,
1259 unsigned transfer_usage,
1260 const struct pipe_box *box)
1261 {
1262 /* r600g doesn't react to dirty_tex_descriptor_counter */
1263 return rscreen->chip_class >= GFX6 &&
1264 !rtex->resource.b.is_shared &&
1265 !(transfer_usage & PIPE_TRANSFER_READ) &&
1266 rtex->resource.b.b.last_level == 0 &&
1267 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1268 box->x, box->y, box->z,
1269 box->width, box->height,
1270 box->depth);
1271 }
1272
1273 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1274 struct r600_texture *rtex)
1275 {
1276 struct r600_common_screen *rscreen = rctx->screen;
1277
1278 /* There is no point in discarding depth and tiled buffers. */
1279 assert(!rtex->is_depth);
1280 assert(rtex->surface.is_linear);
1281
1282 /* Reallocate the buffer in the same pipe_resource. */
1283 r600_alloc_resource(rscreen, &rtex->resource);
1284
1285 /* Initialize the CMASK base address (needed even without CMASK). */
1286 rtex->cmask.base_address_reg =
1287 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1288
1289 p_atomic_inc(&rscreen->dirty_tex_counter);
1290
1291 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1292 }
1293
1294 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1295 struct pipe_resource *texture,
1296 unsigned level,
1297 unsigned usage,
1298 const struct pipe_box *box,
1299 struct pipe_transfer **ptransfer)
1300 {
1301 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1302 struct r600_texture *rtex = (struct r600_texture*)texture;
1303 struct r600_transfer *trans;
1304 struct r600_resource *buf;
1305 unsigned offset = 0;
1306 char *map;
1307 bool use_staging_texture = false;
1308
1309 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1310 assert(box->width && box->height && box->depth);
1311
1312 /* Depth textures use staging unconditionally. */
1313 if (!rtex->is_depth) {
1314 /* Degrade the tile mode if we get too many transfers on APUs.
1315 * On dGPUs, the staging texture is always faster.
1316 * Only count uploads that are at least 4x4 pixels large.
1317 */
1318 if (!rctx->screen->info.has_dedicated_vram &&
1319 level == 0 &&
1320 box->width >= 4 && box->height >= 4 &&
1321 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1322 bool can_invalidate =
1323 r600_can_invalidate_texture(rctx->screen, rtex,
1324 usage, box);
1325
1326 r600_reallocate_texture_inplace(rctx, rtex,
1327 PIPE_BIND_LINEAR,
1328 can_invalidate);
1329 }
1330
1331 /* Tiled textures need to be converted into a linear texture for CPU
1332 * access. The staging texture is always linear and is placed in GART.
1333 *
1334 * Reading from VRAM or GTT WC is slow, always use the staging
1335 * texture in this case.
1336 *
1337 * Use the staging texture for uploads if the underlying BO
1338 * is busy.
1339 */
1340 if (!rtex->surface.is_linear)
1341 use_staging_texture = true;
1342 else if (usage & PIPE_TRANSFER_READ)
1343 use_staging_texture =
1344 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1345 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1346 /* Write & linear only: */
1347 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1348 RADEON_USAGE_READWRITE) ||
1349 !rctx->ws->buffer_wait(rtex->resource.buf, 0,
1350 RADEON_USAGE_READWRITE)) {
1351 /* It's busy. */
1352 if (r600_can_invalidate_texture(rctx->screen, rtex,
1353 usage, box))
1354 r600_texture_invalidate_storage(rctx, rtex);
1355 else
1356 use_staging_texture = true;
1357 }
1358 }
1359
1360 trans = CALLOC_STRUCT(r600_transfer);
1361 if (!trans)
1362 return NULL;
1363 pipe_resource_reference(&trans->b.b.resource, texture);
1364 trans->b.b.level = level;
1365 trans->b.b.usage = usage;
1366 trans->b.b.box = *box;
1367
1368 if (rtex->is_depth) {
1369 struct r600_texture *staging_depth;
1370
1371 if (rtex->resource.b.b.nr_samples > 1) {
1372 /* MSAA depth buffers need to be converted to single sample buffers.
1373 *
1374 * Mapping MSAA depth buffers can occur if ReadPixels is called
1375 * with a multisample GLX visual.
1376 *
1377 * First downsample the depth buffer to a temporary texture,
1378 * then decompress the temporary one to staging.
1379 *
1380 * Only the region being mapped is transfered.
1381 */
1382 struct pipe_resource resource;
1383
1384 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1385
1386 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1387 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1388 FREE(trans);
1389 return NULL;
1390 }
1391
1392 if (usage & PIPE_TRANSFER_READ) {
1393 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1394 if (!temp) {
1395 R600_ERR("failed to create a temporary depth texture\n");
1396 FREE(trans);
1397 return NULL;
1398 }
1399
1400 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1401 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1402 0, 0, 0, box->depth, 0, 0);
1403 pipe_resource_reference(&temp, NULL);
1404 }
1405
1406 /* Just get the strides. */
1407 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1408 &trans->b.b.stride,
1409 &trans->b.b.layer_stride);
1410 } else {
1411 /* XXX: only readback the rectangle which is being mapped? */
1412 /* XXX: when discard is true, no need to read back from depth texture */
1413 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1414 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1415 FREE(trans);
1416 return NULL;
1417 }
1418
1419 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1420 level, level,
1421 box->z, box->z + box->depth - 1,
1422 0, 0);
1423
1424 offset = r600_texture_get_offset(rctx->screen, staging_depth,
1425 level, box,
1426 &trans->b.b.stride,
1427 &trans->b.b.layer_stride);
1428 }
1429
1430 trans->staging = (struct r600_resource*)staging_depth;
1431 buf = trans->staging;
1432 } else if (use_staging_texture) {
1433 struct pipe_resource resource;
1434 struct r600_texture *staging;
1435
1436 r600_init_temp_resource_from_box(&resource, texture, box, level,
1437 R600_RESOURCE_FLAG_TRANSFER);
1438 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1439 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1440
1441 /* Create the temporary texture. */
1442 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1443 if (!staging) {
1444 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1445 FREE(trans);
1446 return NULL;
1447 }
1448 trans->staging = &staging->resource;
1449
1450 /* Just get the strides. */
1451 r600_texture_get_offset(rctx->screen, staging, 0, NULL,
1452 &trans->b.b.stride,
1453 &trans->b.b.layer_stride);
1454
1455 if (usage & PIPE_TRANSFER_READ)
1456 r600_copy_to_staging_texture(ctx, trans);
1457 else
1458 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1459
1460 buf = trans->staging;
1461 } else {
1462 /* the resource is mapped directly */
1463 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1464 &trans->b.b.stride,
1465 &trans->b.b.layer_stride);
1466 buf = &rtex->resource;
1467 }
1468
1469 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1470 r600_resource_reference(&trans->staging, NULL);
1471 FREE(trans);
1472 return NULL;
1473 }
1474
1475 *ptransfer = &trans->b.b;
1476 return map + offset;
1477 }
1478
1479 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1480 struct pipe_transfer* transfer)
1481 {
1482 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1483 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1484 struct pipe_resource *texture = transfer->resource;
1485 struct r600_texture *rtex = (struct r600_texture*)texture;
1486
1487 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1488 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1489 ctx->resource_copy_region(ctx, texture, transfer->level,
1490 transfer->box.x, transfer->box.y, transfer->box.z,
1491 &rtransfer->staging->b.b, transfer->level,
1492 &transfer->box);
1493 } else {
1494 r600_copy_from_staging_texture(ctx, rtransfer);
1495 }
1496 }
1497
1498 if (rtransfer->staging) {
1499 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1500 r600_resource_reference(&rtransfer->staging, NULL);
1501 }
1502
1503 /* Heuristic for {upload, draw, upload, draw, ..}:
1504 *
1505 * Flush the gfx IB if we've allocated too much texture storage.
1506 *
1507 * The idea is that we don't want to build IBs that use too much
1508 * memory and put pressure on the kernel memory manager and we also
1509 * want to make temporary and invalidated buffers go idle ASAP to
1510 * decrease the total memory usage or make them reusable. The memory
1511 * usage will be slightly higher than given here because of the buffer
1512 * cache in the winsys.
1513 *
1514 * The result is that the kernel memory manager is never a bottleneck.
1515 */
1516 if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
1517 rctx->gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1518 rctx->num_alloc_tex_transfer_bytes = 0;
1519 }
1520
1521 pipe_resource_reference(&transfer->resource, NULL);
1522 FREE(transfer);
1523 }
1524
1525 static const struct u_resource_vtbl r600_texture_vtbl =
1526 {
1527 NULL, /* get_handle */
1528 r600_texture_destroy, /* resource_destroy */
1529 r600_texture_transfer_map, /* transfer_map */
1530 u_default_transfer_flush_region, /* transfer_flush_region */
1531 r600_texture_transfer_unmap, /* transfer_unmap */
1532 };
1533
1534 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1535 struct pipe_resource *texture,
1536 const struct pipe_surface *templ,
1537 unsigned width0, unsigned height0,
1538 unsigned width, unsigned height)
1539 {
1540 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1541
1542 if (!surface)
1543 return NULL;
1544
1545 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1546 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1547
1548 pipe_reference_init(&surface->base.reference, 1);
1549 pipe_resource_reference(&surface->base.texture, texture);
1550 surface->base.context = pipe;
1551 surface->base.format = templ->format;
1552 surface->base.width = width;
1553 surface->base.height = height;
1554 surface->base.u = templ->u;
1555
1556 surface->width0 = width0;
1557 surface->height0 = height0;
1558
1559 return &surface->base;
1560 }
1561
1562 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1563 struct pipe_resource *tex,
1564 const struct pipe_surface *templ)
1565 {
1566 unsigned level = templ->u.tex.level;
1567 unsigned width = u_minify(tex->width0, level);
1568 unsigned height = u_minify(tex->height0, level);
1569 unsigned width0 = tex->width0;
1570 unsigned height0 = tex->height0;
1571
1572 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1573 const struct util_format_description *tex_desc
1574 = util_format_description(tex->format);
1575 const struct util_format_description *templ_desc
1576 = util_format_description(templ->format);
1577
1578 assert(tex_desc->block.bits == templ_desc->block.bits);
1579
1580 /* Adjust size of surface if and only if the block width or
1581 * height is changed. */
1582 if (tex_desc->block.width != templ_desc->block.width ||
1583 tex_desc->block.height != templ_desc->block.height) {
1584 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1585 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1586
1587 width = nblks_x * templ_desc->block.width;
1588 height = nblks_y * templ_desc->block.height;
1589
1590 width0 = util_format_get_nblocksx(tex->format, width0);
1591 height0 = util_format_get_nblocksy(tex->format, height0);
1592 }
1593 }
1594
1595 return r600_create_surface_custom(pipe, tex, templ,
1596 width0, height0,
1597 width, height);
1598 }
1599
1600 static void r600_surface_destroy(struct pipe_context *pipe,
1601 struct pipe_surface *surface)
1602 {
1603 struct r600_surface *surf = (struct r600_surface*)surface;
1604 r600_resource_reference(&surf->cb_buffer_fmask, NULL);
1605 r600_resource_reference(&surf->cb_buffer_cmask, NULL);
1606 pipe_resource_reference(&surface->texture, NULL);
1607 FREE(surface);
1608 }
1609
1610 static void r600_clear_texture(struct pipe_context *pipe,
1611 struct pipe_resource *tex,
1612 unsigned level,
1613 const struct pipe_box *box,
1614 const void *data)
1615 {
1616 struct pipe_screen *screen = pipe->screen;
1617 struct r600_texture *rtex = (struct r600_texture*)tex;
1618 struct pipe_surface tmpl = {{0}};
1619 struct pipe_surface *sf;
1620 const struct util_format_description *desc =
1621 util_format_description(tex->format);
1622
1623 tmpl.format = tex->format;
1624 tmpl.u.tex.first_layer = box->z;
1625 tmpl.u.tex.last_layer = box->z + box->depth - 1;
1626 tmpl.u.tex.level = level;
1627 sf = pipe->create_surface(pipe, tex, &tmpl);
1628 if (!sf)
1629 return;
1630
1631 if (rtex->is_depth) {
1632 unsigned clear;
1633 float depth;
1634 uint8_t stencil = 0;
1635
1636 /* Depth is always present. */
1637 clear = PIPE_CLEAR_DEPTH;
1638 desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
1639
1640 if (rtex->surface.has_stencil) {
1641 clear |= PIPE_CLEAR_STENCIL;
1642 desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
1643 }
1644
1645 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
1646 box->x, box->y,
1647 box->width, box->height, false);
1648 } else {
1649 union pipe_color_union color;
1650
1651 /* pipe_color_union requires the full vec4 representation. */
1652 if (util_format_is_pure_uint(tex->format))
1653 desc->unpack_rgba_uint(color.ui, 0, data, 0, 1, 1);
1654 else if (util_format_is_pure_sint(tex->format))
1655 desc->unpack_rgba_sint(color.i, 0, data, 0, 1, 1);
1656 else
1657 desc->unpack_rgba_float(color.f, 0, data, 0, 1, 1);
1658
1659 if (screen->is_format_supported(screen, tex->format,
1660 tex->target, 0, 0,
1661 PIPE_BIND_RENDER_TARGET)) {
1662 pipe->clear_render_target(pipe, sf, &color,
1663 box->x, box->y,
1664 box->width, box->height, false);
1665 } else {
1666 /* Software fallback - just for R9G9B9E5_FLOAT */
1667 util_clear_render_target(pipe, sf, &color,
1668 box->x, box->y,
1669 box->width, box->height);
1670 }
1671 }
1672 pipe_surface_reference(&sf, NULL);
1673 }
1674
1675 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1676 {
1677 const struct util_format_description *desc = util_format_description(format);
1678
1679 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1680
1681 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1682 return V_0280A0_SWAP_STD;
1683
1684 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1685 return ~0U;
1686
1687 switch (desc->nr_channels) {
1688 case 1:
1689 if (HAS_SWIZZLE(0,X))
1690 return V_0280A0_SWAP_STD; /* X___ */
1691 else if (HAS_SWIZZLE(3,X))
1692 return V_0280A0_SWAP_ALT_REV; /* ___X */
1693 break;
1694 case 2:
1695 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1696 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1697 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1698 return V_0280A0_SWAP_STD; /* XY__ */
1699 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1700 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1701 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1702 /* YX__ */
1703 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1704 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1705 return V_0280A0_SWAP_ALT; /* X__Y */
1706 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1707 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1708 break;
1709 case 3:
1710 if (HAS_SWIZZLE(0,X))
1711 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1712 else if (HAS_SWIZZLE(0,Z))
1713 return V_0280A0_SWAP_STD_REV; /* ZYX */
1714 break;
1715 case 4:
1716 /* check the middle channels, the 1st and 4th channel can be NONE */
1717 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1718 return V_0280A0_SWAP_STD; /* XYZW */
1719 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1720 return V_0280A0_SWAP_STD_REV; /* WZYX */
1721 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1722 return V_0280A0_SWAP_ALT; /* ZYXW */
1723 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1724 /* YZWX */
1725 if (desc->is_array)
1726 return V_0280A0_SWAP_ALT_REV;
1727 else
1728 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1729 }
1730 break;
1731 }
1732 return ~0U;
1733 }
1734
1735 /* FAST COLOR CLEAR */
1736
1737 static void evergreen_set_clear_color(struct r600_texture *rtex,
1738 enum pipe_format surface_format,
1739 const union pipe_color_union *color)
1740 {
1741 union util_color uc;
1742
1743 memset(&uc, 0, sizeof(uc));
1744
1745 if (rtex->surface.bpe == 16) {
1746 /* DCC fast clear only:
1747 * CLEAR_WORD0 = R = G = B
1748 * CLEAR_WORD1 = A
1749 */
1750 assert(color->ui[0] == color->ui[1] &&
1751 color->ui[0] == color->ui[2]);
1752 uc.ui[0] = color->ui[0];
1753 uc.ui[1] = color->ui[3];
1754 } else if (util_format_is_pure_uint(surface_format)) {
1755 util_format_write_4ui(surface_format, color->ui, 0, &uc, 0, 0, 0, 1, 1);
1756 } else if (util_format_is_pure_sint(surface_format)) {
1757 util_format_write_4i(surface_format, color->i, 0, &uc, 0, 0, 0, 1, 1);
1758 } else {
1759 util_pack_color(color->f, surface_format, &uc);
1760 }
1761
1762 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1763 }
1764
1765 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1766 struct pipe_framebuffer_state *fb,
1767 struct r600_atom *fb_state,
1768 unsigned *buffers, ubyte *dirty_cbufs,
1769 const union pipe_color_union *color)
1770 {
1771 int i;
1772
1773 /* This function is broken in BE, so just disable this path for now */
1774 #if PIPE_ARCH_BIG_ENDIAN
1775 return;
1776 #endif
1777
1778 if (rctx->render_cond)
1779 return;
1780
1781 for (i = 0; i < fb->nr_cbufs; i++) {
1782 struct r600_texture *tex;
1783 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1784
1785 if (!fb->cbufs[i])
1786 continue;
1787
1788 /* if this colorbuffer is not being cleared */
1789 if (!(*buffers & clear_bit))
1790 continue;
1791
1792 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1793
1794 /* the clear is allowed if all layers are bound */
1795 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1796 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1797 continue;
1798 }
1799
1800 /* cannot clear mipmapped textures */
1801 if (fb->cbufs[i]->texture->last_level != 0) {
1802 continue;
1803 }
1804
1805 /* only supported on tiled surfaces */
1806 if (tex->surface.is_linear) {
1807 continue;
1808 }
1809
1810 /* shared textures can't use fast clear without an explicit flush,
1811 * because there is no way to communicate the clear color among
1812 * all clients
1813 */
1814 if (tex->resource.b.is_shared &&
1815 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1816 continue;
1817
1818 /* Use a slow clear for small surfaces where the cost of
1819 * the eliminate pass can be higher than the benefit of fast
1820 * clear. AMDGPU-pro does this, but the numbers may differ.
1821 *
1822 * This helps on both dGPUs and APUs, even small ones.
1823 */
1824 if (tex->resource.b.b.nr_samples <= 1 &&
1825 tex->resource.b.b.width0 * tex->resource.b.b.height0 <= 300 * 300)
1826 continue;
1827
1828 {
1829 /* 128-bit formats are unusupported */
1830 if (tex->surface.bpe > 8) {
1831 continue;
1832 }
1833
1834 /* ensure CMASK is enabled */
1835 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1836 if (tex->cmask.size == 0) {
1837 continue;
1838 }
1839
1840 /* Do the fast clear. */
1841 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1842 tex->cmask.offset, tex->cmask.size, 0,
1843 R600_COHERENCY_CB_META);
1844
1845 bool need_compressed_update = !tex->dirty_level_mask;
1846
1847 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1848
1849 if (need_compressed_update)
1850 p_atomic_inc(&rctx->screen->compressed_colortex_counter);
1851 }
1852
1853 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1854
1855 if (dirty_cbufs)
1856 *dirty_cbufs |= 1 << i;
1857 rctx->set_atom_dirty(rctx, fb_state, true);
1858 *buffers &= ~clear_bit;
1859 }
1860 }
1861
1862 static struct pipe_memory_object *
1863 r600_memobj_from_handle(struct pipe_screen *screen,
1864 struct winsys_handle *whandle,
1865 bool dedicated)
1866 {
1867 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1868 struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
1869 struct pb_buffer *buf = NULL;
1870
1871 if (!memobj)
1872 return NULL;
1873
1874 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1875 rscreen->info.max_alignment);
1876 if (!buf) {
1877 free(memobj);
1878 return NULL;
1879 }
1880
1881 memobj->b.dedicated = dedicated;
1882 memobj->buf = buf;
1883 memobj->stride = whandle->stride;
1884 memobj->offset = whandle->offset;
1885
1886 return (struct pipe_memory_object *)memobj;
1887
1888 }
1889
1890 static void
1891 r600_memobj_destroy(struct pipe_screen *screen,
1892 struct pipe_memory_object *_memobj)
1893 {
1894 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1895
1896 pb_reference(&memobj->buf, NULL);
1897 free(memobj);
1898 }
1899
1900 static struct pipe_resource *
1901 r600_texture_from_memobj(struct pipe_screen *screen,
1902 const struct pipe_resource *templ,
1903 struct pipe_memory_object *_memobj,
1904 uint64_t offset)
1905 {
1906 int r;
1907 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1908 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1909 struct r600_texture *rtex;
1910 struct radeon_surf surface = {};
1911 struct radeon_bo_metadata metadata = {};
1912 enum radeon_surf_mode array_mode;
1913 bool is_scanout;
1914 struct pb_buffer *buf = NULL;
1915
1916 if (memobj->b.dedicated) {
1917 rscreen->ws->buffer_get_metadata(memobj->buf, &metadata);
1918 r600_surface_import_metadata(rscreen, &surface, &metadata,
1919 &array_mode, &is_scanout);
1920 } else {
1921 /**
1922 * The bo metadata is unset for un-dedicated images. So we fall
1923 * back to linear. See answer to question 5 of the
1924 * VK_KHX_external_memory spec for some details.
1925 *
1926 * It is possible that this case isn't going to work if the
1927 * surface pitch isn't correctly aligned by default.
1928 *
1929 * In order to support it correctly we require multi-image
1930 * metadata to be syncrhonized between radv and radeonsi. The
1931 * semantics of associating multiple image metadata to a memory
1932 * object on the vulkan export side are not concretely defined
1933 * either.
1934 *
1935 * All the use cases we are aware of at the moment for memory
1936 * objects use dedicated allocations. So lets keep the initial
1937 * implementation simple.
1938 *
1939 * A possible alternative is to attempt to reconstruct the
1940 * tiling information when the TexParameter TEXTURE_TILING_EXT
1941 * is set.
1942 */
1943 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1944 is_scanout = false;
1945
1946 }
1947
1948 r = r600_init_surface(rscreen, &surface, templ,
1949 array_mode, memobj->stride,
1950 offset, true, is_scanout,
1951 false);
1952 if (r)
1953 return NULL;
1954
1955 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
1956 if (!rtex)
1957 return NULL;
1958
1959 /* r600_texture_create_object doesn't increment refcount of
1960 * memobj->buf, so increment it here.
1961 */
1962 pb_reference(&buf, memobj->buf);
1963
1964 rtex->resource.b.is_shared = true;
1965 rtex->resource.external_usage = PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE;
1966
1967 return &rtex->resource.b.b;
1968 }
1969
1970 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1971 {
1972 rscreen->b.resource_from_handle = r600_texture_from_handle;
1973 rscreen->b.resource_get_handle = r600_texture_get_handle;
1974 rscreen->b.resource_get_info = r600_texture_get_info;
1975 rscreen->b.resource_from_memobj = r600_texture_from_memobj;
1976 rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
1977 rscreen->b.memobj_destroy = r600_memobj_destroy;
1978 }
1979
1980 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1981 {
1982 rctx->b.create_surface = r600_create_surface;
1983 rctx->b.surface_destroy = r600_surface_destroy;
1984 rctx->b.clear_texture = r600_clear_texture;
1985 }