2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "r600_pipe_common.h"
29 #include "r600_query.h"
30 #include "util/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
36 #include "state_tracker/winsys_handle.h"
40 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
41 struct r600_texture
*rtex
);
42 static enum radeon_surf_mode
43 r600_choose_tiling(struct r600_common_screen
*rscreen
,
44 const struct pipe_resource
*templ
);
47 bool r600_prepare_for_dma_blit(struct r600_common_context
*rctx
,
48 struct r600_texture
*rdst
,
49 unsigned dst_level
, unsigned dstx
,
50 unsigned dsty
, unsigned dstz
,
51 struct r600_texture
*rsrc
,
53 const struct pipe_box
*src_box
)
58 if (rdst
->surface
.bpe
!= rsrc
->surface
.bpe
)
61 /* MSAA: Blits don't exist in the real world. */
62 if (rsrc
->resource
.b
.b
.nr_samples
> 1 ||
63 rdst
->resource
.b
.b
.nr_samples
> 1)
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
70 if (rsrc
->is_depth
|| rdst
->is_depth
)
74 * src: Both texture and SDMA paths need decompression. Use SDMA.
75 * dst: If overwriting the whole texture, discard CMASK and use
76 * SDMA. Otherwise, use the 3D path.
78 if (rdst
->cmask
.size
&& rdst
->dirty_level_mask
& (1 << dst_level
)) {
79 /* The CMASK clear is only enabled for the first level. */
80 assert(dst_level
== 0);
81 if (!util_texrange_covers_whole_level(&rdst
->resource
.b
.b
, dst_level
,
82 dstx
, dsty
, dstz
, src_box
->width
,
83 src_box
->height
, src_box
->depth
))
86 r600_texture_discard_cmask(rctx
->screen
, rdst
);
89 /* All requirements are met. Prepare textures for SDMA. */
90 if (rsrc
->cmask
.size
&& rsrc
->dirty_level_mask
& (1 << src_level
))
91 rctx
->b
.flush_resource(&rctx
->b
, &rsrc
->resource
.b
.b
);
93 assert(!(rsrc
->dirty_level_mask
& (1 << src_level
)));
94 assert(!(rdst
->dirty_level_mask
& (1 << dst_level
)));
99 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
100 static void r600_copy_region_with_blit(struct pipe_context
*pipe
,
101 struct pipe_resource
*dst
,
103 unsigned dstx
, unsigned dsty
, unsigned dstz
,
104 struct pipe_resource
*src
,
106 const struct pipe_box
*src_box
)
108 struct pipe_blit_info blit
;
110 memset(&blit
, 0, sizeof(blit
));
111 blit
.src
.resource
= src
;
112 blit
.src
.format
= src
->format
;
113 blit
.src
.level
= src_level
;
114 blit
.src
.box
= *src_box
;
115 blit
.dst
.resource
= dst
;
116 blit
.dst
.format
= dst
->format
;
117 blit
.dst
.level
= dst_level
;
118 blit
.dst
.box
.x
= dstx
;
119 blit
.dst
.box
.y
= dsty
;
120 blit
.dst
.box
.z
= dstz
;
121 blit
.dst
.box
.width
= src_box
->width
;
122 blit
.dst
.box
.height
= src_box
->height
;
123 blit
.dst
.box
.depth
= src_box
->depth
;
124 blit
.mask
= util_format_get_mask(src
->format
) &
125 util_format_get_mask(dst
->format
);
126 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
129 pipe
->blit(pipe
, &blit
);
133 /* Copy from a full GPU texture to a transfer's staging one. */
134 static void r600_copy_to_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
136 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
137 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
138 struct pipe_resource
*dst
= &rtransfer
->staging
->b
.b
;
139 struct pipe_resource
*src
= transfer
->resource
;
141 if (src
->nr_samples
> 1) {
142 r600_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0,
143 src
, transfer
->level
, &transfer
->box
);
147 rctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
,
151 /* Copy from a transfer's staging texture to a full GPU one. */
152 static void r600_copy_from_staging_texture(struct pipe_context
*ctx
, struct r600_transfer
*rtransfer
)
154 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
155 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)rtransfer
;
156 struct pipe_resource
*dst
= transfer
->resource
;
157 struct pipe_resource
*src
= &rtransfer
->staging
->b
.b
;
158 struct pipe_box sbox
;
160 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
162 if (dst
->nr_samples
> 1) {
163 r600_copy_region_with_blit(ctx
, dst
, transfer
->level
,
164 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
169 rctx
->dma_copy(ctx
, dst
, transfer
->level
,
170 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
174 static unsigned r600_texture_get_offset(struct r600_common_screen
*rscreen
,
175 struct r600_texture
*rtex
, unsigned level
,
176 const struct pipe_box
*box
,
178 unsigned *layer_stride
)
180 *stride
= rtex
->surface
.u
.legacy
.level
[level
].nblk_x
*
182 assert((uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
183 *layer_stride
= (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
186 return rtex
->surface
.u
.legacy
.level
[level
].offset
;
188 /* Each texture is an array of mipmap levels. Each level is
189 * an array of slices. */
190 return rtex
->surface
.u
.legacy
.level
[level
].offset
+
191 box
->z
* (uint64_t)rtex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
192 (box
->y
/ rtex
->surface
.blk_h
*
193 rtex
->surface
.u
.legacy
.level
[level
].nblk_x
+
194 box
->x
/ rtex
->surface
.blk_w
) * rtex
->surface
.bpe
;
197 static int r600_init_surface(struct r600_common_screen
*rscreen
,
198 struct radeon_surf
*surface
,
199 const struct pipe_resource
*ptex
,
200 enum radeon_surf_mode array_mode
,
201 unsigned pitch_in_bytes_override
,
205 bool is_flushed_depth
)
207 const struct util_format_description
*desc
=
208 util_format_description(ptex
->format
);
209 bool is_depth
, is_stencil
;
211 unsigned i
, bpe
, flags
= 0;
213 is_depth
= util_format_has_depth(desc
);
214 is_stencil
= util_format_has_stencil(desc
);
216 if (rscreen
->chip_class
>= EVERGREEN
&& !is_flushed_depth
&&
217 ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
218 bpe
= 4; /* stencil is allocated separately on evergreen */
220 bpe
= util_format_get_blocksize(ptex
->format
);
221 assert(util_is_power_of_two_or_zero(bpe
));
224 if (!is_flushed_depth
&& is_depth
) {
225 flags
|= RADEON_SURF_ZBUFFER
;
228 flags
|= RADEON_SURF_SBUFFER
;
231 if (ptex
->bind
& PIPE_BIND_SCANOUT
|| is_scanout
) {
232 /* This should catch bugs in gallium users setting incorrect flags. */
233 assert(ptex
->nr_samples
<= 1 &&
234 ptex
->array_size
== 1 &&
236 ptex
->last_level
== 0 &&
237 !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
239 flags
|= RADEON_SURF_SCANOUT
;
242 if (ptex
->bind
& PIPE_BIND_SHARED
)
243 flags
|= RADEON_SURF_SHAREABLE
;
245 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
246 if (!(ptex
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
))
247 flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
249 r
= rscreen
->ws
->surface_init(rscreen
->ws
, ptex
,
250 flags
, bpe
, array_mode
, surface
);
255 if (pitch_in_bytes_override
&&
256 pitch_in_bytes_override
!= surface
->u
.legacy
.level
[0].nblk_x
* bpe
) {
257 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
260 surface
->u
.legacy
.level
[0].nblk_x
= pitch_in_bytes_override
/ bpe
;
261 surface
->u
.legacy
.level
[0].slice_size_dw
=
262 ((uint64_t)pitch_in_bytes_override
* surface
->u
.legacy
.level
[0].nblk_y
) / 4;
266 for (i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
267 surface
->u
.legacy
.level
[i
].offset
+= offset
;
273 static void r600_texture_init_metadata(struct r600_common_screen
*rscreen
,
274 struct r600_texture
*rtex
,
275 struct radeon_bo_metadata
*metadata
)
277 struct radeon_surf
*surface
= &rtex
->surface
;
279 memset(metadata
, 0, sizeof(*metadata
));
281 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
282 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
283 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
284 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
285 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
286 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
287 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
288 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
289 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
290 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
291 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
292 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
295 static void r600_surface_import_metadata(struct r600_common_screen
*rscreen
,
296 struct radeon_surf
*surf
,
297 struct radeon_bo_metadata
*metadata
,
298 enum radeon_surf_mode
*array_mode
,
301 surf
->u
.legacy
.pipe_config
= metadata
->u
.legacy
.pipe_config
;
302 surf
->u
.legacy
.bankw
= metadata
->u
.legacy
.bankw
;
303 surf
->u
.legacy
.bankh
= metadata
->u
.legacy
.bankh
;
304 surf
->u
.legacy
.tile_split
= metadata
->u
.legacy
.tile_split
;
305 surf
->u
.legacy
.mtilea
= metadata
->u
.legacy
.mtilea
;
306 surf
->u
.legacy
.num_banks
= metadata
->u
.legacy
.num_banks
;
308 if (metadata
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
309 *array_mode
= RADEON_SURF_MODE_2D
;
310 else if (metadata
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
311 *array_mode
= RADEON_SURF_MODE_1D
;
313 *array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
315 *is_scanout
= metadata
->u
.legacy
.scanout
;
318 static void r600_eliminate_fast_color_clear(struct r600_common_context
*rctx
,
319 struct r600_texture
*rtex
)
321 struct r600_common_screen
*rscreen
= rctx
->screen
;
322 struct pipe_context
*ctx
= &rctx
->b
;
324 if (ctx
== rscreen
->aux_context
)
325 mtx_lock(&rscreen
->aux_context_lock
);
327 ctx
->flush_resource(ctx
, &rtex
->resource
.b
.b
);
328 ctx
->flush(ctx
, NULL
, 0);
330 if (ctx
== rscreen
->aux_context
)
331 mtx_unlock(&rscreen
->aux_context_lock
);
334 static void r600_texture_discard_cmask(struct r600_common_screen
*rscreen
,
335 struct r600_texture
*rtex
)
337 if (!rtex
->cmask
.size
)
340 assert(rtex
->resource
.b
.b
.nr_samples
<= 1);
343 memset(&rtex
->cmask
, 0, sizeof(rtex
->cmask
));
344 rtex
->cmask
.base_address_reg
= rtex
->resource
.gpu_address
>> 8;
345 rtex
->dirty_level_mask
= 0;
347 rtex
->cb_color_info
&= ~EG_S_028C70_FAST_CLEAR(1);
349 if (rtex
->cmask_buffer
!= &rtex
->resource
)
350 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
352 /* Notify all contexts about the change. */
353 p_atomic_inc(&rscreen
->dirty_tex_counter
);
354 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
357 static void r600_reallocate_texture_inplace(struct r600_common_context
*rctx
,
358 struct r600_texture
*rtex
,
359 unsigned new_bind_flag
,
360 bool invalidate_storage
)
362 struct pipe_screen
*screen
= rctx
->b
.screen
;
363 struct r600_texture
*new_tex
;
364 struct pipe_resource templ
= rtex
->resource
.b
.b
;
367 templ
.bind
|= new_bind_flag
;
369 /* r600g doesn't react to dirty_tex_descriptor_counter */
370 if (rctx
->chip_class
< GFX6
)
373 if (rtex
->resource
.b
.is_shared
)
376 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
377 if (rtex
->surface
.is_linear
)
380 /* This fails with MSAA, depth, and compressed textures. */
381 if (r600_choose_tiling(rctx
->screen
, &templ
) !=
382 RADEON_SURF_MODE_LINEAR_ALIGNED
)
386 new_tex
= (struct r600_texture
*)screen
->resource_create(screen
, &templ
);
390 /* Copy the pixels to the new texture. */
391 if (!invalidate_storage
) {
392 for (i
= 0; i
<= templ
.last_level
; i
++) {
396 u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
397 util_num_layers(&templ
, i
), &box
);
399 rctx
->dma_copy(&rctx
->b
, &new_tex
->resource
.b
.b
, i
, 0, 0, 0,
400 &rtex
->resource
.b
.b
, i
, &box
);
404 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
405 r600_texture_discard_cmask(rctx
->screen
, rtex
);
408 /* Replace the structure fields of rtex. */
409 rtex
->resource
.b
.b
.bind
= templ
.bind
;
410 pb_reference(&rtex
->resource
.buf
, new_tex
->resource
.buf
);
411 rtex
->resource
.gpu_address
= new_tex
->resource
.gpu_address
;
412 rtex
->resource
.vram_usage
= new_tex
->resource
.vram_usage
;
413 rtex
->resource
.gart_usage
= new_tex
->resource
.gart_usage
;
414 rtex
->resource
.bo_size
= new_tex
->resource
.bo_size
;
415 rtex
->resource
.bo_alignment
= new_tex
->resource
.bo_alignment
;
416 rtex
->resource
.domains
= new_tex
->resource
.domains
;
417 rtex
->resource
.flags
= new_tex
->resource
.flags
;
418 rtex
->size
= new_tex
->size
;
419 rtex
->db_render_format
= new_tex
->db_render_format
;
420 rtex
->db_compatible
= new_tex
->db_compatible
;
421 rtex
->can_sample_z
= new_tex
->can_sample_z
;
422 rtex
->can_sample_s
= new_tex
->can_sample_s
;
423 rtex
->surface
= new_tex
->surface
;
424 rtex
->fmask
= new_tex
->fmask
;
425 rtex
->cmask
= new_tex
->cmask
;
426 rtex
->cb_color_info
= new_tex
->cb_color_info
;
427 rtex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
428 rtex
->htile_offset
= new_tex
->htile_offset
;
429 rtex
->depth_cleared
= new_tex
->depth_cleared
;
430 rtex
->stencil_cleared
= new_tex
->stencil_cleared
;
431 rtex
->non_disp_tiling
= new_tex
->non_disp_tiling
;
432 rtex
->framebuffers_bound
= new_tex
->framebuffers_bound
;
434 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
435 assert(!rtex
->htile_offset
);
436 assert(!rtex
->cmask
.size
);
437 assert(!rtex
->fmask
.size
);
438 assert(!rtex
->is_depth
);
441 r600_texture_reference(&new_tex
, NULL
);
443 p_atomic_inc(&rctx
->screen
->dirty_tex_counter
);
446 static void r600_texture_get_info(struct pipe_screen
* screen
,
447 struct pipe_resource
*resource
,
451 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
452 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
456 if (!rscreen
|| !rtex
)
459 if (resource
->target
!= PIPE_BUFFER
) {
460 offset
= rtex
->surface
.u
.legacy
.level
[0].offset
;
461 stride
= rtex
->surface
.u
.legacy
.level
[0].nblk_x
*
472 static bool r600_texture_get_handle(struct pipe_screen
* screen
,
473 struct pipe_context
*ctx
,
474 struct pipe_resource
*resource
,
475 struct winsys_handle
*whandle
,
478 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
479 struct r600_common_context
*rctx
;
480 struct r600_resource
*res
= (struct r600_resource
*)resource
;
481 struct r600_texture
*rtex
= (struct r600_texture
*)resource
;
482 struct radeon_bo_metadata metadata
;
483 bool update_metadata
= false;
484 unsigned stride
, offset
, slice_size
;
486 ctx
= threaded_context_unwrap_sync(ctx
);
487 rctx
= (struct r600_common_context
*)(ctx
? ctx
: rscreen
->aux_context
);
489 if (resource
->target
!= PIPE_BUFFER
) {
490 /* This is not supported now, but it might be required for OpenCL
491 * interop in the future.
493 if (resource
->nr_samples
> 1 || rtex
->is_depth
)
496 /* Move a suballocated texture into a non-suballocated allocation. */
497 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
498 rtex
->surface
.tile_swizzle
) {
499 assert(!res
->b
.is_shared
);
500 r600_reallocate_texture_inplace(rctx
, rtex
,
501 PIPE_BIND_SHARED
, false);
502 rctx
->b
.flush(&rctx
->b
, NULL
, 0);
503 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
504 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
505 assert(rtex
->surface
.tile_swizzle
== 0);
508 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
510 /* Eliminate fast clear (CMASK) */
511 r600_eliminate_fast_color_clear(rctx
, rtex
);
513 /* Disable CMASK if flush_resource isn't going
516 if (rtex
->cmask
.size
)
517 r600_texture_discard_cmask(rscreen
, rtex
);
521 if (!res
->b
.is_shared
|| update_metadata
) {
522 r600_texture_init_metadata(rscreen
, rtex
, &metadata
);
524 rscreen
->ws
->buffer_set_metadata(res
->buf
, &metadata
);
527 slice_size
= (uint64_t)rtex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
529 /* Move a suballocated buffer into a non-suballocated allocation. */
530 if (rscreen
->ws
->buffer_is_suballocated(res
->buf
)) {
531 assert(!res
->b
.is_shared
);
533 /* Allocate a new buffer with PIPE_BIND_SHARED. */
534 struct pipe_resource templ
= res
->b
.b
;
535 templ
.bind
|= PIPE_BIND_SHARED
;
537 struct pipe_resource
*newb
=
538 screen
->resource_create(screen
, &templ
);
542 /* Copy the old buffer contents to the new one. */
544 u_box_1d(0, newb
->width0
, &box
);
545 rctx
->b
.resource_copy_region(&rctx
->b
, newb
, 0, 0, 0, 0,
547 /* Move the new buffer storage to the old pipe_resource. */
548 r600_replace_buffer_storage(&rctx
->b
, &res
->b
.b
, newb
);
549 pipe_resource_reference(&newb
, NULL
);
551 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
552 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
559 r600_texture_get_info(screen
, resource
, &stride
, &offset
);
561 if (res
->b
.is_shared
) {
562 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
565 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
566 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
567 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
569 res
->b
.is_shared
= true;
570 res
->external_usage
= usage
;
573 whandle
->stride
= stride
;
574 whandle
->offset
= offset
+ slice_size
* whandle
->layer
;
576 return rscreen
->ws
->buffer_get_handle(rscreen
->ws
, res
->buf
, whandle
);
579 static void r600_texture_destroy(struct pipe_screen
*screen
,
580 struct pipe_resource
*ptex
)
582 struct r600_texture
*rtex
= (struct r600_texture
*)ptex
;
583 struct r600_resource
*resource
= &rtex
->resource
;
585 r600_texture_reference(&rtex
->flushed_depth_texture
, NULL
);
586 pipe_resource_reference((struct pipe_resource
**)&resource
->immed_buffer
, NULL
);
588 if (rtex
->cmask_buffer
!= &rtex
->resource
) {
589 r600_resource_reference(&rtex
->cmask_buffer
, NULL
);
591 pb_reference(&resource
->buf
, NULL
);
595 static const struct u_resource_vtbl r600_texture_vtbl
;
597 /* The number of samples can be specified independently of the texture. */
598 void r600_texture_get_fmask_info(struct r600_common_screen
*rscreen
,
599 struct r600_texture
*rtex
,
601 struct r600_fmask_info
*out
)
603 /* FMASK is allocated like an ordinary texture. */
604 struct pipe_resource templ
= rtex
->resource
.b
.b
;
605 struct radeon_surf fmask
= {};
608 memset(out
, 0, sizeof(*out
));
610 templ
.nr_samples
= 1;
611 flags
= rtex
->surface
.flags
| RADEON_SURF_FMASK
;
613 /* Use the same parameters and tile mode. */
614 fmask
.u
.legacy
.bankw
= rtex
->surface
.u
.legacy
.bankw
;
615 fmask
.u
.legacy
.bankh
= rtex
->surface
.u
.legacy
.bankh
;
616 fmask
.u
.legacy
.mtilea
= rtex
->surface
.u
.legacy
.mtilea
;
617 fmask
.u
.legacy
.tile_split
= rtex
->surface
.u
.legacy
.tile_split
;
620 fmask
.u
.legacy
.bankh
= 4;
622 switch (nr_samples
) {
631 R600_ERR("Invalid sample count for FMASK allocation.\n");
635 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
636 * This can be fixed by writing a separate FMASK allocator specifically
637 * for R600-R700 asics. */
638 if (rscreen
->chip_class
<= R700
) {
642 if (rscreen
->ws
->surface_init(rscreen
->ws
, &templ
,
643 flags
, bpe
, RADEON_SURF_MODE_2D
, &fmask
)) {
644 R600_ERR("Got error in surface_init while allocating FMASK.\n");
648 assert(fmask
.u
.legacy
.level
[0].mode
== RADEON_SURF_MODE_2D
);
650 out
->slice_tile_max
= (fmask
.u
.legacy
.level
[0].nblk_x
* fmask
.u
.legacy
.level
[0].nblk_y
) / 64;
651 if (out
->slice_tile_max
)
652 out
->slice_tile_max
-= 1;
654 out
->tile_mode_index
= fmask
.u
.legacy
.tiling_index
[0];
655 out
->pitch_in_pixels
= fmask
.u
.legacy
.level
[0].nblk_x
;
656 out
->bank_height
= fmask
.u
.legacy
.bankh
;
657 out
->tile_swizzle
= fmask
.tile_swizzle
;
658 out
->alignment
= MAX2(256, fmask
.surf_alignment
);
659 out
->size
= fmask
.surf_size
;
662 static void r600_texture_allocate_fmask(struct r600_common_screen
*rscreen
,
663 struct r600_texture
*rtex
)
665 r600_texture_get_fmask_info(rscreen
, rtex
,
666 rtex
->resource
.b
.b
.nr_samples
, &rtex
->fmask
);
668 rtex
->fmask
.offset
= align64(rtex
->size
, rtex
->fmask
.alignment
);
669 rtex
->size
= rtex
->fmask
.offset
+ rtex
->fmask
.size
;
672 void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen
,
673 struct r600_texture
*rtex
,
674 struct r600_cmask_info
*out
)
676 unsigned cmask_tile_width
= 8;
677 unsigned cmask_tile_height
= 8;
678 unsigned cmask_tile_elements
= cmask_tile_width
* cmask_tile_height
;
679 unsigned element_bits
= 4;
680 unsigned cmask_cache_bits
= 1024;
681 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
682 unsigned pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
684 unsigned elements_per_macro_tile
= (cmask_cache_bits
/ element_bits
) * num_pipes
;
685 unsigned pixels_per_macro_tile
= elements_per_macro_tile
* cmask_tile_elements
;
686 unsigned sqrt_pixels_per_macro_tile
= sqrt(pixels_per_macro_tile
);
687 unsigned macro_tile_width
= util_next_power_of_two(sqrt_pixels_per_macro_tile
);
688 unsigned macro_tile_height
= pixels_per_macro_tile
/ macro_tile_width
;
690 unsigned pitch_elements
= align(rtex
->resource
.b
.b
.width0
, macro_tile_width
);
691 unsigned height
= align(rtex
->resource
.b
.b
.height0
, macro_tile_height
);
693 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
694 unsigned slice_bytes
=
695 ((pitch_elements
* height
* element_bits
+ 7) / 8) / cmask_tile_elements
;
697 assert(macro_tile_width
% 128 == 0);
698 assert(macro_tile_height
% 128 == 0);
700 out
->slice_tile_max
= ((pitch_elements
* height
) / (128*128)) - 1;
701 out
->alignment
= MAX2(256, base_align
);
702 out
->size
= util_num_layers(&rtex
->resource
.b
.b
, 0) *
703 align(slice_bytes
, base_align
);
706 static void r600_texture_allocate_cmask(struct r600_common_screen
*rscreen
,
707 struct r600_texture
*rtex
)
709 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
711 rtex
->cmask
.offset
= align64(rtex
->size
, rtex
->cmask
.alignment
);
712 rtex
->size
= rtex
->cmask
.offset
+ rtex
->cmask
.size
;
714 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
717 static void r600_texture_alloc_cmask_separate(struct r600_common_screen
*rscreen
,
718 struct r600_texture
*rtex
)
720 if (rtex
->cmask_buffer
)
723 assert(rtex
->cmask
.size
== 0);
725 r600_texture_get_cmask_info(rscreen
, rtex
, &rtex
->cmask
);
727 rtex
->cmask_buffer
= (struct r600_resource
*)
728 r600_aligned_buffer_create(&rscreen
->b
,
729 R600_RESOURCE_FLAG_UNMAPPABLE
,
732 rtex
->cmask
.alignment
);
733 if (rtex
->cmask_buffer
== NULL
) {
734 rtex
->cmask
.size
= 0;
738 /* update colorbuffer state bits */
739 rtex
->cmask
.base_address_reg
= rtex
->cmask_buffer
->gpu_address
>> 8;
741 rtex
->cb_color_info
|= EG_S_028C70_FAST_CLEAR(1);
743 p_atomic_inc(&rscreen
->compressed_colortex_counter
);
746 void eg_resource_alloc_immed(struct r600_common_screen
*rscreen
,
747 struct r600_resource
*res
,
750 res
->immed_buffer
= (struct r600_resource
*)
751 pipe_buffer_create(&rscreen
->b
, PIPE_BIND_CUSTOM
,
752 PIPE_USAGE_DEFAULT
, immed_size
);
755 static void r600_texture_get_htile_size(struct r600_common_screen
*rscreen
,
756 struct r600_texture
*rtex
)
758 unsigned cl_width
, cl_height
, width
, height
;
759 unsigned slice_elements
, slice_bytes
, pipe_interleave_bytes
, base_align
;
760 unsigned num_pipes
= rscreen
->info
.num_tile_pipes
;
762 rtex
->surface
.htile_size
= 0;
764 if (rscreen
->chip_class
<= EVERGREEN
&&
765 rscreen
->info
.drm_minor
< 26)
768 /* HW bug on R6xx. */
769 if (rscreen
->chip_class
== R600
&&
770 (rtex
->resource
.b
.b
.width0
> 7680 ||
771 rtex
->resource
.b
.b
.height0
> 7680))
800 width
= align(rtex
->surface
.u
.legacy
.level
[0].nblk_x
, cl_width
* 8);
801 height
= align(rtex
->surface
.u
.legacy
.level
[0].nblk_y
, cl_height
* 8);
803 slice_elements
= (width
* height
) / (8 * 8);
804 slice_bytes
= slice_elements
* 4;
806 pipe_interleave_bytes
= rscreen
->info
.pipe_interleave_bytes
;
807 base_align
= num_pipes
* pipe_interleave_bytes
;
809 rtex
->surface
.htile_alignment
= base_align
;
810 rtex
->surface
.htile_size
=
811 util_num_layers(&rtex
->resource
.b
.b
, 0) *
812 align(slice_bytes
, base_align
);
815 static void r600_texture_allocate_htile(struct r600_common_screen
*rscreen
,
816 struct r600_texture
*rtex
)
818 r600_texture_get_htile_size(rscreen
, rtex
);
820 if (!rtex
->surface
.htile_size
)
823 rtex
->htile_offset
= align(rtex
->size
, rtex
->surface
.htile_alignment
);
824 rtex
->size
= rtex
->htile_offset
+ rtex
->surface
.htile_size
;
827 void r600_print_texture_info(struct r600_common_screen
*rscreen
,
828 struct r600_texture
*rtex
, struct u_log_context
*log
)
832 /* Common parameters. */
833 u_log_printf(log
, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
834 "blk_h=%u, array_size=%u, last_level=%u, "
835 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
836 rtex
->resource
.b
.b
.width0
, rtex
->resource
.b
.b
.height0
,
837 rtex
->resource
.b
.b
.depth0
, rtex
->surface
.blk_w
,
839 rtex
->resource
.b
.b
.array_size
, rtex
->resource
.b
.b
.last_level
,
840 rtex
->surface
.bpe
, rtex
->resource
.b
.b
.nr_samples
,
841 rtex
->surface
.flags
, util_format_short_name(rtex
->resource
.b
.b
.format
));
843 u_log_printf(log
, " Layout: size=%"PRIu64
", alignment=%u, bankw=%u, "
844 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
845 rtex
->surface
.surf_size
, rtex
->surface
.surf_alignment
, rtex
->surface
.u
.legacy
.bankw
,
846 rtex
->surface
.u
.legacy
.bankh
, rtex
->surface
.u
.legacy
.num_banks
, rtex
->surface
.u
.legacy
.mtilea
,
847 rtex
->surface
.u
.legacy
.tile_split
, rtex
->surface
.u
.legacy
.pipe_config
,
848 (rtex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
850 if (rtex
->fmask
.size
)
851 u_log_printf(log
, " FMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, pitch_in_pixels=%u, "
852 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
853 rtex
->fmask
.offset
, rtex
->fmask
.size
, rtex
->fmask
.alignment
,
854 rtex
->fmask
.pitch_in_pixels
, rtex
->fmask
.bank_height
,
855 rtex
->fmask
.slice_tile_max
, rtex
->fmask
.tile_mode_index
);
857 if (rtex
->cmask
.size
)
858 u_log_printf(log
, " CMask: offset=%"PRIu64
", size=%"PRIu64
", alignment=%u, "
859 "slice_tile_max=%u\n",
860 rtex
->cmask
.offset
, rtex
->cmask
.size
, rtex
->cmask
.alignment
,
861 rtex
->cmask
.slice_tile_max
);
863 if (rtex
->htile_offset
)
864 u_log_printf(log
, " HTile: offset=%"PRIu64
", size=%u "
866 rtex
->htile_offset
, rtex
->surface
.htile_size
,
867 rtex
->surface
.htile_alignment
);
869 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++)
870 u_log_printf(log
, " Level[%i]: offset=%"PRIu64
", slice_size=%"PRIu64
", "
871 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
872 "mode=%u, tiling_index = %u\n",
873 i
, rtex
->surface
.u
.legacy
.level
[i
].offset
,
874 (uint64_t)rtex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
875 u_minify(rtex
->resource
.b
.b
.width0
, i
),
876 u_minify(rtex
->resource
.b
.b
.height0
, i
),
877 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
878 rtex
->surface
.u
.legacy
.level
[i
].nblk_x
,
879 rtex
->surface
.u
.legacy
.level
[i
].nblk_y
,
880 rtex
->surface
.u
.legacy
.level
[i
].mode
,
881 rtex
->surface
.u
.legacy
.tiling_index
[i
]);
883 if (rtex
->surface
.has_stencil
) {
884 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
885 rtex
->surface
.u
.legacy
.stencil_tile_split
);
886 for (i
= 0; i
<= rtex
->resource
.b
.b
.last_level
; i
++) {
887 u_log_printf(log
, " StencilLevel[%i]: offset=%"PRIu64
", "
888 "slice_size=%"PRIu64
", npix_x=%u, "
889 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
890 "mode=%u, tiling_index = %u\n",
891 i
, rtex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
892 (uint64_t)rtex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
893 u_minify(rtex
->resource
.b
.b
.width0
, i
),
894 u_minify(rtex
->resource
.b
.b
.height0
, i
),
895 u_minify(rtex
->resource
.b
.b
.depth0
, i
),
896 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
897 rtex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
898 rtex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
899 rtex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
904 /* Common processing for r600_texture_create and r600_texture_from_handle */
905 static struct r600_texture
*
906 r600_texture_create_object(struct pipe_screen
*screen
,
907 const struct pipe_resource
*base
,
908 struct pb_buffer
*buf
,
909 struct radeon_surf
*surface
)
911 struct r600_texture
*rtex
;
912 struct r600_resource
*resource
;
913 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
915 rtex
= CALLOC_STRUCT(r600_texture
);
919 resource
= &rtex
->resource
;
920 resource
->b
.b
= *base
;
921 resource
->b
.b
.next
= NULL
;
922 resource
->b
.vtbl
= &r600_texture_vtbl
;
923 pipe_reference_init(&resource
->b
.b
.reference
, 1);
924 resource
->b
.b
.screen
= screen
;
926 /* don't include stencil-only formats which we don't support for rendering */
927 rtex
->is_depth
= util_format_has_depth(util_format_description(rtex
->resource
.b
.b
.format
));
929 rtex
->surface
= *surface
;
930 rtex
->size
= rtex
->surface
.surf_size
;
931 rtex
->db_render_format
= base
->format
;
933 /* Tiled depth textures utilize the non-displayable tile order.
934 * This must be done after r600_setup_surface.
935 * Applies to R600-Cayman. */
936 rtex
->non_disp_tiling
= rtex
->is_depth
&& rtex
->surface
.u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
;
937 /* Applies to GCN. */
938 rtex
->last_msaa_resolve_target_micro_mode
= rtex
->surface
.micro_tile_mode
;
940 if (rtex
->is_depth
) {
941 if (base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
942 R600_RESOURCE_FLAG_FLUSHED_DEPTH
) ||
943 rscreen
->chip_class
>= EVERGREEN
) {
944 rtex
->can_sample_z
= !rtex
->surface
.u
.legacy
.depth_adjusted
;
945 rtex
->can_sample_s
= !rtex
->surface
.u
.legacy
.stencil_adjusted
;
947 if (rtex
->resource
.b
.b
.nr_samples
<= 1 &&
948 (rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z16_UNORM
||
949 rtex
->resource
.b
.b
.format
== PIPE_FORMAT_Z32_FLOAT
))
950 rtex
->can_sample_z
= true;
953 if (!(base
->flags
& (R600_RESOURCE_FLAG_TRANSFER
|
954 R600_RESOURCE_FLAG_FLUSHED_DEPTH
))) {
955 rtex
->db_compatible
= true;
957 if (!(rscreen
->debug_flags
& DBG_NO_HYPERZ
))
958 r600_texture_allocate_htile(rscreen
, rtex
);
961 if (base
->nr_samples
> 1) {
963 r600_texture_allocate_fmask(rscreen
, rtex
);
964 r600_texture_allocate_cmask(rscreen
, rtex
);
965 rtex
->cmask_buffer
= &rtex
->resource
;
967 if (!rtex
->fmask
.size
|| !rtex
->cmask
.size
) {
974 /* Now create the backing buffer. */
976 r600_init_resource_fields(rscreen
, resource
, rtex
->size
,
977 rtex
->surface
.surf_alignment
);
979 if (!r600_alloc_resource(rscreen
, resource
)) {
985 resource
->gpu_address
= rscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
986 resource
->bo_size
= buf
->size
;
987 resource
->bo_alignment
= buf
->alignment
;
988 resource
->domains
= rscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
989 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
990 resource
->vram_usage
= buf
->size
;
991 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
992 resource
->gart_usage
= buf
->size
;
995 if (rtex
->cmask
.size
) {
996 /* Initialize the cmask to 0xCC (= compressed state). */
997 r600_screen_clear_buffer(rscreen
, &rtex
->cmask_buffer
->b
.b
,
998 rtex
->cmask
.offset
, rtex
->cmask
.size
,
1001 if (rtex
->htile_offset
) {
1002 uint32_t clear_value
= 0;
1004 r600_screen_clear_buffer(rscreen
, &rtex
->resource
.b
.b
,
1006 rtex
->surface
.htile_size
,
1010 /* Initialize the CMASK base register value. */
1011 rtex
->cmask
.base_address_reg
=
1012 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1014 if (rscreen
->debug_flags
& DBG_VM
) {
1015 fprintf(stderr
, "VM start=0x%"PRIX64
" end=0x%"PRIX64
" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1016 rtex
->resource
.gpu_address
,
1017 rtex
->resource
.gpu_address
+ rtex
->resource
.buf
->size
,
1018 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+1,
1019 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1022 if (rscreen
->debug_flags
& DBG_TEX
) {
1024 struct u_log_context log
;
1025 u_log_context_init(&log
);
1026 r600_print_texture_info(rscreen
, rtex
, &log
);
1027 u_log_new_page_print(&log
, stdout
);
1029 u_log_context_destroy(&log
);
1035 static enum radeon_surf_mode
1036 r600_choose_tiling(struct r600_common_screen
*rscreen
,
1037 const struct pipe_resource
*templ
)
1039 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1040 bool force_tiling
= templ
->flags
& R600_RESOURCE_FLAG_FORCE_TILING
;
1041 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1042 !(templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
);
1044 /* MSAA resources must be 2D tiled. */
1045 if (templ
->nr_samples
> 1)
1046 return RADEON_SURF_MODE_2D
;
1048 /* Transfer resources should be linear. */
1049 if (templ
->flags
& R600_RESOURCE_FLAG_TRANSFER
)
1050 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1052 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1053 if (rscreen
->chip_class
>= R600
&& rscreen
->chip_class
<= CAYMAN
&&
1054 (templ
->bind
& PIPE_BIND_COMPUTE_RESOURCE
) &&
1055 (templ
->target
== PIPE_TEXTURE_2D
||
1056 templ
->target
== PIPE_TEXTURE_3D
))
1057 force_tiling
= true;
1059 /* Handle common candidates for the linear mode.
1060 * Compressed textures and DB surfaces must always be tiled.
1062 if (!force_tiling
&&
1063 !is_depth_stencil
&&
1064 !util_format_is_compressed(templ
->format
)) {
1065 if (rscreen
->debug_flags
& DBG_NO_TILING
)
1066 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1068 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1069 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1070 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1072 if (templ
->bind
& PIPE_BIND_LINEAR
)
1073 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1075 /* 1D textures should be linear - fixes image operations on 1d */
1076 if (templ
->target
== PIPE_TEXTURE_1D
||
1077 templ
->target
== PIPE_TEXTURE_1D_ARRAY
)
1078 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1080 /* Textures likely to be mapped often. */
1081 if (templ
->usage
== PIPE_USAGE_STAGING
||
1082 templ
->usage
== PIPE_USAGE_STREAM
)
1083 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1086 /* Make small textures 1D tiled. */
1087 if (templ
->width0
<= 16 || templ
->height0
<= 16 ||
1088 (rscreen
->debug_flags
& DBG_NO_2D_TILING
))
1089 return RADEON_SURF_MODE_1D
;
1091 /* The allocator will switch to 1D if needed. */
1092 return RADEON_SURF_MODE_2D
;
1095 struct pipe_resource
*r600_texture_create(struct pipe_screen
*screen
,
1096 const struct pipe_resource
*templ
)
1098 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1099 struct radeon_surf surface
= {0};
1100 bool is_flushed_depth
= templ
->flags
& R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1103 r
= r600_init_surface(rscreen
, &surface
, templ
,
1104 r600_choose_tiling(rscreen
, templ
), 0, 0,
1105 false, false, is_flushed_depth
);
1110 return (struct pipe_resource
*)
1111 r600_texture_create_object(screen
, templ
, NULL
, &surface
);
1114 static struct pipe_resource
*r600_texture_from_handle(struct pipe_screen
*screen
,
1115 const struct pipe_resource
*templ
,
1116 struct winsys_handle
*whandle
,
1119 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1120 struct pb_buffer
*buf
= NULL
;
1121 enum radeon_surf_mode array_mode
;
1122 struct radeon_surf surface
= {};
1124 struct radeon_bo_metadata metadata
= {};
1125 struct r600_texture
*rtex
;
1128 /* Support only 2D textures without mipmaps */
1129 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
) ||
1130 templ
->depth0
!= 1 || templ
->last_level
!= 0)
1133 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
,
1134 rscreen
->info
.max_alignment
);
1138 rscreen
->ws
->buffer_get_metadata(buf
, &metadata
);
1139 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
1140 &array_mode
, &is_scanout
);
1142 r
= r600_init_surface(rscreen
, &surface
, templ
, array_mode
,
1143 whandle
->stride
, whandle
->offset
,
1144 true, is_scanout
, false);
1149 rtex
= r600_texture_create_object(screen
, templ
, buf
, &surface
);
1153 rtex
->resource
.b
.is_shared
= true;
1154 rtex
->resource
.external_usage
= usage
;
1156 assert(rtex
->surface
.tile_swizzle
== 0);
1157 return &rtex
->resource
.b
.b
;
1160 bool r600_init_flushed_depth_texture(struct pipe_context
*ctx
,
1161 struct pipe_resource
*texture
,
1162 struct r600_texture
**staging
)
1164 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1165 struct pipe_resource resource
;
1166 struct r600_texture
**flushed_depth_texture
= staging
?
1167 staging
: &rtex
->flushed_depth_texture
;
1168 enum pipe_format pipe_format
= texture
->format
;
1171 if (rtex
->flushed_depth_texture
)
1172 return true; /* it's ready */
1174 if (!rtex
->can_sample_z
&& rtex
->can_sample_s
) {
1175 switch (pipe_format
) {
1176 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1177 /* Save memory by not allocating the S plane. */
1178 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1180 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1181 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1182 /* Save memory bandwidth by not copying the
1183 * stencil part during flush.
1185 * This potentially increases memory bandwidth
1186 * if an application uses both Z and S texturing
1187 * simultaneously (a flushed Z24S8 texture
1188 * would be stored compactly), but how often
1189 * does that really happen?
1191 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1195 } else if (!rtex
->can_sample_s
&& rtex
->can_sample_z
) {
1196 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1198 /* DB->CB copies to an 8bpp surface don't work. */
1199 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1203 memset(&resource
, 0, sizeof(resource
));
1204 resource
.target
= texture
->target
;
1205 resource
.format
= pipe_format
;
1206 resource
.width0
= texture
->width0
;
1207 resource
.height0
= texture
->height0
;
1208 resource
.depth0
= texture
->depth0
;
1209 resource
.array_size
= texture
->array_size
;
1210 resource
.last_level
= texture
->last_level
;
1211 resource
.nr_samples
= texture
->nr_samples
;
1212 resource
.usage
= staging
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1213 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1214 resource
.flags
= texture
->flags
| R600_RESOURCE_FLAG_FLUSHED_DEPTH
;
1217 resource
.flags
|= R600_RESOURCE_FLAG_TRANSFER
;
1219 *flushed_depth_texture
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1220 if (*flushed_depth_texture
== NULL
) {
1221 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1225 (*flushed_depth_texture
)->non_disp_tiling
= false;
1230 * Initialize the pipe_resource descriptor to be of the same size as the box,
1231 * which is supposed to hold a subregion of the texture "orig" at the given
1234 static void r600_init_temp_resource_from_box(struct pipe_resource
*res
,
1235 struct pipe_resource
*orig
,
1236 const struct pipe_box
*box
,
1237 unsigned level
, unsigned flags
)
1239 memset(res
, 0, sizeof(*res
));
1240 res
->format
= orig
->format
;
1241 res
->width0
= box
->width
;
1242 res
->height0
= box
->height
;
1244 res
->array_size
= 1;
1245 res
->usage
= flags
& R600_RESOURCE_FLAG_TRANSFER
? PIPE_USAGE_STAGING
: PIPE_USAGE_DEFAULT
;
1248 /* We must set the correct texture target and dimensions for a 3D box. */
1249 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1250 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1251 res
->array_size
= box
->depth
;
1253 res
->target
= PIPE_TEXTURE_2D
;
1257 static bool r600_can_invalidate_texture(struct r600_common_screen
*rscreen
,
1258 struct r600_texture
*rtex
,
1259 unsigned transfer_usage
,
1260 const struct pipe_box
*box
)
1262 /* r600g doesn't react to dirty_tex_descriptor_counter */
1263 return rscreen
->chip_class
>= GFX6
&&
1264 !rtex
->resource
.b
.is_shared
&&
1265 !(transfer_usage
& PIPE_TRANSFER_READ
) &&
1266 rtex
->resource
.b
.b
.last_level
== 0 &&
1267 util_texrange_covers_whole_level(&rtex
->resource
.b
.b
, 0,
1268 box
->x
, box
->y
, box
->z
,
1269 box
->width
, box
->height
,
1273 static void r600_texture_invalidate_storage(struct r600_common_context
*rctx
,
1274 struct r600_texture
*rtex
)
1276 struct r600_common_screen
*rscreen
= rctx
->screen
;
1278 /* There is no point in discarding depth and tiled buffers. */
1279 assert(!rtex
->is_depth
);
1280 assert(rtex
->surface
.is_linear
);
1282 /* Reallocate the buffer in the same pipe_resource. */
1283 r600_alloc_resource(rscreen
, &rtex
->resource
);
1285 /* Initialize the CMASK base address (needed even without CMASK). */
1286 rtex
->cmask
.base_address_reg
=
1287 (rtex
->resource
.gpu_address
+ rtex
->cmask
.offset
) >> 8;
1289 p_atomic_inc(&rscreen
->dirty_tex_counter
);
1291 rctx
->num_alloc_tex_transfer_bytes
+= rtex
->size
;
1294 static void *r600_texture_transfer_map(struct pipe_context
*ctx
,
1295 struct pipe_resource
*texture
,
1298 const struct pipe_box
*box
,
1299 struct pipe_transfer
**ptransfer
)
1301 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1302 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1303 struct r600_transfer
*trans
;
1304 struct r600_resource
*buf
;
1305 unsigned offset
= 0;
1307 bool use_staging_texture
= false;
1309 assert(!(texture
->flags
& R600_RESOURCE_FLAG_TRANSFER
));
1310 assert(box
->width
&& box
->height
&& box
->depth
);
1312 /* Depth textures use staging unconditionally. */
1313 if (!rtex
->is_depth
) {
1314 /* Degrade the tile mode if we get too many transfers on APUs.
1315 * On dGPUs, the staging texture is always faster.
1316 * Only count uploads that are at least 4x4 pixels large.
1318 if (!rctx
->screen
->info
.has_dedicated_vram
&&
1320 box
->width
>= 4 && box
->height
>= 4 &&
1321 p_atomic_inc_return(&rtex
->num_level0_transfers
) == 10) {
1322 bool can_invalidate
=
1323 r600_can_invalidate_texture(rctx
->screen
, rtex
,
1326 r600_reallocate_texture_inplace(rctx
, rtex
,
1331 /* Tiled textures need to be converted into a linear texture for CPU
1332 * access. The staging texture is always linear and is placed in GART.
1334 * Reading from VRAM or GTT WC is slow, always use the staging
1335 * texture in this case.
1337 * Use the staging texture for uploads if the underlying BO
1340 if (!rtex
->surface
.is_linear
)
1341 use_staging_texture
= true;
1342 else if (usage
& PIPE_TRANSFER_READ
)
1343 use_staging_texture
=
1344 rtex
->resource
.domains
& RADEON_DOMAIN_VRAM
||
1345 rtex
->resource
.flags
& RADEON_FLAG_GTT_WC
;
1346 /* Write & linear only: */
1347 else if (r600_rings_is_buffer_referenced(rctx
, rtex
->resource
.buf
,
1348 RADEON_USAGE_READWRITE
) ||
1349 !rctx
->ws
->buffer_wait(rtex
->resource
.buf
, 0,
1350 RADEON_USAGE_READWRITE
)) {
1352 if (r600_can_invalidate_texture(rctx
->screen
, rtex
,
1354 r600_texture_invalidate_storage(rctx
, rtex
);
1356 use_staging_texture
= true;
1360 trans
= CALLOC_STRUCT(r600_transfer
);
1363 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1364 trans
->b
.b
.level
= level
;
1365 trans
->b
.b
.usage
= usage
;
1366 trans
->b
.b
.box
= *box
;
1368 if (rtex
->is_depth
) {
1369 struct r600_texture
*staging_depth
;
1371 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1372 /* MSAA depth buffers need to be converted to single sample buffers.
1374 * Mapping MSAA depth buffers can occur if ReadPixels is called
1375 * with a multisample GLX visual.
1377 * First downsample the depth buffer to a temporary texture,
1378 * then decompress the temporary one to staging.
1380 * Only the region being mapped is transfered.
1382 struct pipe_resource resource
;
1384 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
, 0);
1386 if (!r600_init_flushed_depth_texture(ctx
, &resource
, &staging_depth
)) {
1387 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1392 if (usage
& PIPE_TRANSFER_READ
) {
1393 struct pipe_resource
*temp
= ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1395 R600_ERR("failed to create a temporary depth texture\n");
1400 r600_copy_region_with_blit(ctx
, temp
, 0, 0, 0, 0, texture
, level
, box
);
1401 rctx
->blit_decompress_depth(ctx
, (struct r600_texture
*)temp
, staging_depth
,
1402 0, 0, 0, box
->depth
, 0, 0);
1403 pipe_resource_reference(&temp
, NULL
);
1406 /* Just get the strides. */
1407 r600_texture_get_offset(rctx
->screen
, staging_depth
, level
, NULL
,
1409 &trans
->b
.b
.layer_stride
);
1411 /* XXX: only readback the rectangle which is being mapped? */
1412 /* XXX: when discard is true, no need to read back from depth texture */
1413 if (!r600_init_flushed_depth_texture(ctx
, texture
, &staging_depth
)) {
1414 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1419 rctx
->blit_decompress_depth(ctx
, rtex
, staging_depth
,
1421 box
->z
, box
->z
+ box
->depth
- 1,
1424 offset
= r600_texture_get_offset(rctx
->screen
, staging_depth
,
1427 &trans
->b
.b
.layer_stride
);
1430 trans
->staging
= (struct r600_resource
*)staging_depth
;
1431 buf
= trans
->staging
;
1432 } else if (use_staging_texture
) {
1433 struct pipe_resource resource
;
1434 struct r600_texture
*staging
;
1436 r600_init_temp_resource_from_box(&resource
, texture
, box
, level
,
1437 R600_RESOURCE_FLAG_TRANSFER
);
1438 resource
.usage
= (usage
& PIPE_TRANSFER_READ
) ?
1439 PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1441 /* Create the temporary texture. */
1442 staging
= (struct r600_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1444 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1448 trans
->staging
= &staging
->resource
;
1450 /* Just get the strides. */
1451 r600_texture_get_offset(rctx
->screen
, staging
, 0, NULL
,
1453 &trans
->b
.b
.layer_stride
);
1455 if (usage
& PIPE_TRANSFER_READ
)
1456 r600_copy_to_staging_texture(ctx
, trans
);
1458 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1460 buf
= trans
->staging
;
1462 /* the resource is mapped directly */
1463 offset
= r600_texture_get_offset(rctx
->screen
, rtex
, level
, box
,
1465 &trans
->b
.b
.layer_stride
);
1466 buf
= &rtex
->resource
;
1469 if (!(map
= r600_buffer_map_sync_with_rings(rctx
, buf
, usage
))) {
1470 r600_resource_reference(&trans
->staging
, NULL
);
1475 *ptransfer
= &trans
->b
.b
;
1476 return map
+ offset
;
1479 static void r600_texture_transfer_unmap(struct pipe_context
*ctx
,
1480 struct pipe_transfer
* transfer
)
1482 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
1483 struct r600_transfer
*rtransfer
= (struct r600_transfer
*)transfer
;
1484 struct pipe_resource
*texture
= transfer
->resource
;
1485 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
1487 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && rtransfer
->staging
) {
1488 if (rtex
->is_depth
&& rtex
->resource
.b
.b
.nr_samples
<= 1) {
1489 ctx
->resource_copy_region(ctx
, texture
, transfer
->level
,
1490 transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
,
1491 &rtransfer
->staging
->b
.b
, transfer
->level
,
1494 r600_copy_from_staging_texture(ctx
, rtransfer
);
1498 if (rtransfer
->staging
) {
1499 rctx
->num_alloc_tex_transfer_bytes
+= rtransfer
->staging
->buf
->size
;
1500 r600_resource_reference(&rtransfer
->staging
, NULL
);
1503 /* Heuristic for {upload, draw, upload, draw, ..}:
1505 * Flush the gfx IB if we've allocated too much texture storage.
1507 * The idea is that we don't want to build IBs that use too much
1508 * memory and put pressure on the kernel memory manager and we also
1509 * want to make temporary and invalidated buffers go idle ASAP to
1510 * decrease the total memory usage or make them reusable. The memory
1511 * usage will be slightly higher than given here because of the buffer
1512 * cache in the winsys.
1514 * The result is that the kernel memory manager is never a bottleneck.
1516 if (rctx
->num_alloc_tex_transfer_bytes
> rctx
->screen
->info
.gart_size
/ 4) {
1517 rctx
->gfx
.flush(rctx
, PIPE_FLUSH_ASYNC
, NULL
);
1518 rctx
->num_alloc_tex_transfer_bytes
= 0;
1521 pipe_resource_reference(&transfer
->resource
, NULL
);
1525 static const struct u_resource_vtbl r600_texture_vtbl
=
1527 NULL
, /* get_handle */
1528 r600_texture_destroy
, /* resource_destroy */
1529 r600_texture_transfer_map
, /* transfer_map */
1530 u_default_transfer_flush_region
, /* transfer_flush_region */
1531 r600_texture_transfer_unmap
, /* transfer_unmap */
1534 struct pipe_surface
*r600_create_surface_custom(struct pipe_context
*pipe
,
1535 struct pipe_resource
*texture
,
1536 const struct pipe_surface
*templ
,
1537 unsigned width0
, unsigned height0
,
1538 unsigned width
, unsigned height
)
1540 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
1545 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1546 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1548 pipe_reference_init(&surface
->base
.reference
, 1);
1549 pipe_resource_reference(&surface
->base
.texture
, texture
);
1550 surface
->base
.context
= pipe
;
1551 surface
->base
.format
= templ
->format
;
1552 surface
->base
.width
= width
;
1553 surface
->base
.height
= height
;
1554 surface
->base
.u
= templ
->u
;
1556 surface
->width0
= width0
;
1557 surface
->height0
= height0
;
1559 return &surface
->base
;
1562 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
1563 struct pipe_resource
*tex
,
1564 const struct pipe_surface
*templ
)
1566 unsigned level
= templ
->u
.tex
.level
;
1567 unsigned width
= u_minify(tex
->width0
, level
);
1568 unsigned height
= u_minify(tex
->height0
, level
);
1569 unsigned width0
= tex
->width0
;
1570 unsigned height0
= tex
->height0
;
1572 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1573 const struct util_format_description
*tex_desc
1574 = util_format_description(tex
->format
);
1575 const struct util_format_description
*templ_desc
1576 = util_format_description(templ
->format
);
1578 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1580 /* Adjust size of surface if and only if the block width or
1581 * height is changed. */
1582 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1583 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1584 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1585 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1587 width
= nblks_x
* templ_desc
->block
.width
;
1588 height
= nblks_y
* templ_desc
->block
.height
;
1590 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1591 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1595 return r600_create_surface_custom(pipe
, tex
, templ
,
1600 static void r600_surface_destroy(struct pipe_context
*pipe
,
1601 struct pipe_surface
*surface
)
1603 struct r600_surface
*surf
= (struct r600_surface
*)surface
;
1604 r600_resource_reference(&surf
->cb_buffer_fmask
, NULL
);
1605 r600_resource_reference(&surf
->cb_buffer_cmask
, NULL
);
1606 pipe_resource_reference(&surface
->texture
, NULL
);
1610 static void r600_clear_texture(struct pipe_context
*pipe
,
1611 struct pipe_resource
*tex
,
1613 const struct pipe_box
*box
,
1616 struct pipe_screen
*screen
= pipe
->screen
;
1617 struct r600_texture
*rtex
= (struct r600_texture
*)tex
;
1618 struct pipe_surface tmpl
= {{0}};
1619 struct pipe_surface
*sf
;
1620 const struct util_format_description
*desc
=
1621 util_format_description(tex
->format
);
1623 tmpl
.format
= tex
->format
;
1624 tmpl
.u
.tex
.first_layer
= box
->z
;
1625 tmpl
.u
.tex
.last_layer
= box
->z
+ box
->depth
- 1;
1626 tmpl
.u
.tex
.level
= level
;
1627 sf
= pipe
->create_surface(pipe
, tex
, &tmpl
);
1631 if (rtex
->is_depth
) {
1634 uint8_t stencil
= 0;
1636 /* Depth is always present. */
1637 clear
= PIPE_CLEAR_DEPTH
;
1638 desc
->unpack_z_float(&depth
, 0, data
, 0, 1, 1);
1640 if (rtex
->surface
.has_stencil
) {
1641 clear
|= PIPE_CLEAR_STENCIL
;
1642 desc
->unpack_s_8uint(&stencil
, 0, data
, 0, 1, 1);
1645 pipe
->clear_depth_stencil(pipe
, sf
, clear
, depth
, stencil
,
1647 box
->width
, box
->height
, false);
1649 union pipe_color_union color
;
1651 /* pipe_color_union requires the full vec4 representation. */
1652 if (util_format_is_pure_uint(tex
->format
))
1653 desc
->unpack_rgba_uint(color
.ui
, 0, data
, 0, 1, 1);
1654 else if (util_format_is_pure_sint(tex
->format
))
1655 desc
->unpack_rgba_sint(color
.i
, 0, data
, 0, 1, 1);
1657 desc
->unpack_rgba_float(color
.f
, 0, data
, 0, 1, 1);
1659 if (screen
->is_format_supported(screen
, tex
->format
,
1661 PIPE_BIND_RENDER_TARGET
)) {
1662 pipe
->clear_render_target(pipe
, sf
, &color
,
1664 box
->width
, box
->height
, false);
1666 /* Software fallback - just for R9G9B9E5_FLOAT */
1667 util_clear_render_target(pipe
, sf
, &color
,
1669 box
->width
, box
->height
);
1672 pipe_surface_reference(&sf
, NULL
);
1675 unsigned r600_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1677 const struct util_format_description
*desc
= util_format_description(format
);
1679 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1681 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1682 return V_0280A0_SWAP_STD
;
1684 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1687 switch (desc
->nr_channels
) {
1689 if (HAS_SWIZZLE(0,X
))
1690 return V_0280A0_SWAP_STD
; /* X___ */
1691 else if (HAS_SWIZZLE(3,X
))
1692 return V_0280A0_SWAP_ALT_REV
; /* ___X */
1695 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
1696 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
1697 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
1698 return V_0280A0_SWAP_STD
; /* XY__ */
1699 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
1700 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
1701 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
1703 return (do_endian_swap
? V_0280A0_SWAP_STD
: V_0280A0_SWAP_STD_REV
);
1704 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
1705 return V_0280A0_SWAP_ALT
; /* X__Y */
1706 else if (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(3,X
))
1707 return V_0280A0_SWAP_ALT_REV
; /* Y__X */
1710 if (HAS_SWIZZLE(0,X
))
1711 return (do_endian_swap
? V_0280A0_SWAP_STD_REV
: V_0280A0_SWAP_STD
);
1712 else if (HAS_SWIZZLE(0,Z
))
1713 return V_0280A0_SWAP_STD_REV
; /* ZYX */
1716 /* check the middle channels, the 1st and 4th channel can be NONE */
1717 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
)) {
1718 return V_0280A0_SWAP_STD
; /* XYZW */
1719 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
)) {
1720 return V_0280A0_SWAP_STD_REV
; /* WZYX */
1721 } else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
)) {
1722 return V_0280A0_SWAP_ALT
; /* ZYXW */
1723 } else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,W
)) {
1726 return V_0280A0_SWAP_ALT_REV
;
1728 return (do_endian_swap
? V_0280A0_SWAP_ALT
: V_0280A0_SWAP_ALT_REV
);
1735 /* FAST COLOR CLEAR */
1737 static void evergreen_set_clear_color(struct r600_texture
*rtex
,
1738 enum pipe_format surface_format
,
1739 const union pipe_color_union
*color
)
1741 union util_color uc
;
1743 memset(&uc
, 0, sizeof(uc
));
1745 if (rtex
->surface
.bpe
== 16) {
1746 /* DCC fast clear only:
1747 * CLEAR_WORD0 = R = G = B
1750 assert(color
->ui
[0] == color
->ui
[1] &&
1751 color
->ui
[0] == color
->ui
[2]);
1752 uc
.ui
[0] = color
->ui
[0];
1753 uc
.ui
[1] = color
->ui
[3];
1754 } else if (util_format_is_pure_uint(surface_format
)) {
1755 util_format_write_4ui(surface_format
, color
->ui
, 0, &uc
, 0, 0, 0, 1, 1);
1756 } else if (util_format_is_pure_sint(surface_format
)) {
1757 util_format_write_4i(surface_format
, color
->i
, 0, &uc
, 0, 0, 0, 1, 1);
1759 util_pack_color(color
->f
, surface_format
, &uc
);
1762 memcpy(rtex
->color_clear_value
, &uc
, 2 * sizeof(uint32_t));
1765 void evergreen_do_fast_color_clear(struct r600_common_context
*rctx
,
1766 struct pipe_framebuffer_state
*fb
,
1767 struct r600_atom
*fb_state
,
1768 unsigned *buffers
, ubyte
*dirty_cbufs
,
1769 const union pipe_color_union
*color
)
1773 /* This function is broken in BE, so just disable this path for now */
1774 #if PIPE_ARCH_BIG_ENDIAN
1778 if (rctx
->render_cond
)
1781 for (i
= 0; i
< fb
->nr_cbufs
; i
++) {
1782 struct r600_texture
*tex
;
1783 unsigned clear_bit
= PIPE_CLEAR_COLOR0
<< i
;
1788 /* if this colorbuffer is not being cleared */
1789 if (!(*buffers
& clear_bit
))
1792 tex
= (struct r600_texture
*)fb
->cbufs
[i
]->texture
;
1794 /* the clear is allowed if all layers are bound */
1795 if (fb
->cbufs
[i
]->u
.tex
.first_layer
!= 0 ||
1796 fb
->cbufs
[i
]->u
.tex
.last_layer
!= util_max_layer(&tex
->resource
.b
.b
, 0)) {
1800 /* cannot clear mipmapped textures */
1801 if (fb
->cbufs
[i
]->texture
->last_level
!= 0) {
1805 /* only supported on tiled surfaces */
1806 if (tex
->surface
.is_linear
) {
1810 /* shared textures can't use fast clear without an explicit flush,
1811 * because there is no way to communicate the clear color among
1814 if (tex
->resource
.b
.is_shared
&&
1815 !(tex
->resource
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
1818 /* Use a slow clear for small surfaces where the cost of
1819 * the eliminate pass can be higher than the benefit of fast
1820 * clear. AMDGPU-pro does this, but the numbers may differ.
1822 * This helps on both dGPUs and APUs, even small ones.
1824 if (tex
->resource
.b
.b
.nr_samples
<= 1 &&
1825 tex
->resource
.b
.b
.width0
* tex
->resource
.b
.b
.height0
<= 300 * 300)
1829 /* 128-bit formats are unusupported */
1830 if (tex
->surface
.bpe
> 8) {
1834 /* ensure CMASK is enabled */
1835 r600_texture_alloc_cmask_separate(rctx
->screen
, tex
);
1836 if (tex
->cmask
.size
== 0) {
1840 /* Do the fast clear. */
1841 rctx
->clear_buffer(&rctx
->b
, &tex
->cmask_buffer
->b
.b
,
1842 tex
->cmask
.offset
, tex
->cmask
.size
, 0,
1843 R600_COHERENCY_CB_META
);
1845 bool need_compressed_update
= !tex
->dirty_level_mask
;
1847 tex
->dirty_level_mask
|= 1 << fb
->cbufs
[i
]->u
.tex
.level
;
1849 if (need_compressed_update
)
1850 p_atomic_inc(&rctx
->screen
->compressed_colortex_counter
);
1853 evergreen_set_clear_color(tex
, fb
->cbufs
[i
]->format
, color
);
1856 *dirty_cbufs
|= 1 << i
;
1857 rctx
->set_atom_dirty(rctx
, fb_state
, true);
1858 *buffers
&= ~clear_bit
;
1862 static struct pipe_memory_object
*
1863 r600_memobj_from_handle(struct pipe_screen
*screen
,
1864 struct winsys_handle
*whandle
,
1867 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1868 struct r600_memory_object
*memobj
= CALLOC_STRUCT(r600_memory_object
);
1869 struct pb_buffer
*buf
= NULL
;
1874 buf
= rscreen
->ws
->buffer_from_handle(rscreen
->ws
, whandle
,
1875 rscreen
->info
.max_alignment
);
1881 memobj
->b
.dedicated
= dedicated
;
1883 memobj
->stride
= whandle
->stride
;
1884 memobj
->offset
= whandle
->offset
;
1886 return (struct pipe_memory_object
*)memobj
;
1891 r600_memobj_destroy(struct pipe_screen
*screen
,
1892 struct pipe_memory_object
*_memobj
)
1894 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
1896 pb_reference(&memobj
->buf
, NULL
);
1900 static struct pipe_resource
*
1901 r600_texture_from_memobj(struct pipe_screen
*screen
,
1902 const struct pipe_resource
*templ
,
1903 struct pipe_memory_object
*_memobj
,
1907 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1908 struct r600_memory_object
*memobj
= (struct r600_memory_object
*)_memobj
;
1909 struct r600_texture
*rtex
;
1910 struct radeon_surf surface
= {};
1911 struct radeon_bo_metadata metadata
= {};
1912 enum radeon_surf_mode array_mode
;
1914 struct pb_buffer
*buf
= NULL
;
1916 if (memobj
->b
.dedicated
) {
1917 rscreen
->ws
->buffer_get_metadata(memobj
->buf
, &metadata
);
1918 r600_surface_import_metadata(rscreen
, &surface
, &metadata
,
1919 &array_mode
, &is_scanout
);
1922 * The bo metadata is unset for un-dedicated images. So we fall
1923 * back to linear. See answer to question 5 of the
1924 * VK_KHX_external_memory spec for some details.
1926 * It is possible that this case isn't going to work if the
1927 * surface pitch isn't correctly aligned by default.
1929 * In order to support it correctly we require multi-image
1930 * metadata to be syncrhonized between radv and radeonsi. The
1931 * semantics of associating multiple image metadata to a memory
1932 * object on the vulkan export side are not concretely defined
1935 * All the use cases we are aware of at the moment for memory
1936 * objects use dedicated allocations. So lets keep the initial
1937 * implementation simple.
1939 * A possible alternative is to attempt to reconstruct the
1940 * tiling information when the TexParameter TEXTURE_TILING_EXT
1943 array_mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1948 r
= r600_init_surface(rscreen
, &surface
, templ
,
1949 array_mode
, memobj
->stride
,
1950 offset
, true, is_scanout
,
1955 rtex
= r600_texture_create_object(screen
, templ
, memobj
->buf
, &surface
);
1959 /* r600_texture_create_object doesn't increment refcount of
1960 * memobj->buf, so increment it here.
1962 pb_reference(&buf
, memobj
->buf
);
1964 rtex
->resource
.b
.is_shared
= true;
1965 rtex
->resource
.external_usage
= PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
;
1967 return &rtex
->resource
.b
.b
;
1970 void r600_init_screen_texture_functions(struct r600_common_screen
*rscreen
)
1972 rscreen
->b
.resource_from_handle
= r600_texture_from_handle
;
1973 rscreen
->b
.resource_get_handle
= r600_texture_get_handle
;
1974 rscreen
->b
.resource_get_info
= r600_texture_get_info
;
1975 rscreen
->b
.resource_from_memobj
= r600_texture_from_memobj
;
1976 rscreen
->b
.memobj_create_from_handle
= r600_memobj_from_handle
;
1977 rscreen
->b
.memobj_destroy
= r600_memobj_destroy
;
1980 void r600_init_context_texture_functions(struct r600_common_context
*rctx
)
1982 rctx
->b
.create_surface
= r600_create_surface
;
1983 rctx
->b
.surface_destroy
= r600_surface_destroy
;
1984 rctx
->b
.clear_texture
= r600_clear_texture
;