src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_math.h>
  31 #include <util/u_inlines.h>
  32 #include <util/u_memory.h>
  33 #include "state_tracker/drm_driver.h"
  34 #include "r600_pipe.h"
  35 #include "r600_resource.h"
  36 #include "r600_state_inlines.h"
  37 #include "r600d.h"
  38 #include "r600_formats.h"
  39
  40 extern struct u_resource_vtbl r600_texture_vtbl;
  41
  42 /* Copy from a tiled texture to a detiled one. */
  43 static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  44 {
  45         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  46         struct pipe_resource *texture = transfer->resource;
  47         struct pipe_subresource subdst;
  48
  49         subdst.face = 0;
  50         subdst.level = 0;
  51         ctx->resource_copy_region(ctx, rtransfer->linear_texture,
  52                                 subdst, 0, 0, 0, texture, transfer->sr,
  53                                 transfer->box.x, transfer->box.y, transfer->box.z,
  54                                 transfer->box.width, transfer->box.height);
  55 }
  56
  57
  58 /* Copy from a detiled texture to a tiled one. */
  59 static void r600_copy_into_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  60 {
  61         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  62         struct pipe_resource *texture = transfer->resource;
  63         struct pipe_subresource subsrc;
  64
  65         subsrc.face = 0;
  66         subsrc.level = 0;
  67         ctx->resource_copy_region(ctx, texture, transfer->sr,
  68                                   transfer->box.x, transfer->box.y, transfer->box.z,
  69                                   rtransfer->linear_texture, subsrc,
  70                                   0, 0, 0,
  71                                   transfer->box.width, transfer->box.height);
  72
  73         ctx->flush(ctx, 0, NULL);
  74 }
  75
  76 static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  77                                         unsigned level, unsigned zslice,
  78                                         unsigned face)
  79 {
  80         unsigned offset = rtex->offset[level];
  81
  82         switch (rtex->resource.base.b.target) {
  83         case PIPE_TEXTURE_3D:
  84                 assert(face == 0);
  85                 return offset + zslice * rtex->layer_size[level];
  86         case PIPE_TEXTURE_CUBE:
  87                 assert(zslice == 0);
  88                 return offset + face * rtex->layer_size[level];
  89         default:
  90                 assert(zslice == 0 && face == 0);
  91                 return offset;
  92         }
  93 }
  94
  95 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
  96                                          enum pipe_format format,
  97                                          unsigned array_mode)
  98 {
  99         struct r600_screen* rscreen = (struct r600_screen *)screen;
 100         unsigned pixsize = util_format_get_blocksize(format);
 101         int p_align;
 102
 103         switch(array_mode) {
 104         case V_038000_ARRAY_1D_TILED_THIN1:
 105                 p_align = MAX2(8,
 106                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
 107                 break;
 108         case V_038000_ARRAY_2D_TILED_THIN1:
 109                 p_align = MAX2(rscreen->tiling_info->num_banks,
 110                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 111                                 rscreen->tiling_info->num_banks));
 112                 break;
 113         case 0:
 114         default:
 115                 p_align = 64;
 116                 break;
 117         }
 118         return p_align;
 119 }
 120
 121 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 122                                           unsigned array_mode)
 123 {
 124         struct r600_screen* rscreen = (struct r600_screen *)screen;
 125         int h_align;
 126
 127         switch (array_mode) {
 128         case V_038000_ARRAY_2D_TILED_THIN1:
 129                 h_align = rscreen->tiling_info->num_channels * 8;
 130                 break;
 131         case V_038000_ARRAY_1D_TILED_THIN1:
 132                 h_align = 8;
 133                 break;
 134         default:
 135                 h_align = 1;
 136                 break;
 137         }
 138         return h_align;
 139 }
 140
 141 static unsigned mip_minify(unsigned size, unsigned level)
 142 {
 143         unsigned val;
 144         val = u_minify(size, level);
 145         if (level > 0)
 146                 val = util_next_power_of_two(val);
 147         return val;
 148 }
 149
 150 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
 151                                         struct r600_resource_texture *rtex,
 152                                         unsigned level)
 153 {
 154         struct pipe_resource *ptex = &rtex->resource.base.b;
 155         struct radeon *radeon = (struct radeon *)screen->winsys;
 156         enum chip_class chipc = r600_get_family_class(radeon);
 157         unsigned width, stride, tile_width;
 158
 159         if (rtex->pitch_override)
 160                 return rtex->pitch_override;
 161
 162         width = mip_minify(ptex->width0, level);
 163         if (util_format_is_plain(ptex->format)) {
 164                 tile_width = r600_get_pixel_alignment(screen, ptex->format,
 165                                                       rtex->array_mode[level]);
 166                 width = align(width, tile_width);
 167         }
 168         stride = util_format_get_stride(ptex->format, width);
 169         if (chipc == EVERGREEN)
 170                 stride = align(stride, 512);
 171         return stride;
 172 }
 173
 174 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 175                                           struct r600_resource_texture *rtex,
 176                                           unsigned level)
 177 {
 178         struct pipe_resource *ptex = &rtex->resource.base.b;
 179         unsigned height, tile_height;
 180
 181         height = mip_minify(ptex->height0, level);
 182         if (util_format_is_plain(ptex->format)) {
 183                 tile_height = r600_get_height_alignment(screen,
 184                                                         rtex->array_mode[level]);
 185                 height = align(height, tile_height);
 186         }
 187         return util_format_get_nblocksy(ptex->format, height);
 188 }
 189
 190 /* Get a width in pixels from a stride in bytes. */
 191 static unsigned pitch_to_width(enum pipe_format format,
 192                                 unsigned pitch_in_bytes)
 193 {
 194     return (pitch_in_bytes / util_format_get_blocksize(format)) *
 195             util_format_get_blockwidth(format);
 196 }
 197
 198 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 199                                         struct r600_resource_texture *rtex,
 200                                         unsigned level, unsigned array_mode)
 201 {
 202         struct pipe_resource *ptex = &rtex->resource.base.b;
 203
 204         switch (array_mode) {
 205         case V_0280A0_ARRAY_LINEAR_GENERAL:
 206         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 207         case V_0280A0_ARRAY_1D_TILED_THIN1:
 208         default:
 209                 rtex->array_mode[level] = array_mode;
 210                 break;
 211         case V_0280A0_ARRAY_2D_TILED_THIN1:
 212         {
 213                 unsigned w, h, tile_height, tile_width;
 214
 215                 tile_height = r600_get_height_alignment(screen, array_mode);
 216                 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
 217
 218                 w = mip_minify(ptex->width0, level);
 219                 h = mip_minify(ptex->height0, level);
 220                 if (w < tile_width || h < tile_height)
 221                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 222                 else
 223                         rtex->array_mode[level] = array_mode;
 224         }
 225         break;
 226         }
 227 }
 228
 229 static void r600_setup_miptree(struct pipe_screen *screen,
 230                                struct r600_resource_texture *rtex,
 231                                unsigned array_mode)
 232 {
 233         struct pipe_resource *ptex = &rtex->resource.base.b;
 234         struct radeon *radeon = (struct radeon *)screen->winsys;
 235         enum chip_class chipc = r600_get_family_class(radeon);
 236         unsigned pitch, size, layer_size, i, offset;
 237         unsigned nblocksy;
 238
 239         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 240                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 241
 242                 pitch = r600_texture_get_stride(screen, rtex, i);
 243                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 244
 245                 layer_size = pitch * nblocksy;
 246
 247                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 248                         if (chipc >= R700)
 249                                 size = layer_size * 8;
 250                         else
 251                                 size = layer_size * 6;
 252                 }
 253                 else
 254                         size = layer_size * u_minify(ptex->depth0, i);
 255                 rtex->offset[i] = offset;
 256                 rtex->layer_size[i] = layer_size;
 257                 rtex->pitch_in_bytes[i] = pitch;
 258                 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
 259                 offset += size;
 260         }
 261         rtex->size = offset;
 262 }
 263
 264 static struct r600_resource_texture *
 265 r600_texture_create_object(struct pipe_screen *screen,
 266                            const struct pipe_resource *base,
 267                            unsigned array_mode,
 268                            unsigned pitch_in_bytes_override,
 269                            unsigned max_buffer_size,
 270                            struct r600_bo *bo)
 271 {
 272         struct r600_resource_texture *rtex;
 273         struct r600_resource *resource;
 274         struct radeon *radeon = (struct radeon *)screen->winsys;
 275
 276         rtex = CALLOC_STRUCT(r600_resource_texture);
 277         if (rtex == NULL)
 278                 return NULL;
 279
 280         resource = &rtex->resource;
 281         resource->base.b = *base;
 282         resource->base.vtbl = &r600_texture_vtbl;
 283         pipe_reference_init(&resource->base.b.reference, 1);
 284         resource->base.b.screen = screen;
 285         resource->bo = bo;
 286         resource->domain = r600_domain_from_usage(resource->base.b.bind);
 287         rtex->pitch_override = pitch_in_bytes_override;
 288
 289         if (array_mode)
 290                 rtex->tiled = 1;
 291         r600_setup_miptree(screen, rtex, array_mode);
 292
 293         resource->size = rtex->size;
 294
 295         if (!resource->bo) {
 296                 resource->bo = r600_bo(radeon, rtex->size, 4096, 0);
 297                 if (!resource->bo) {
 298                         FREE(rtex);
 299                         return NULL;
 300                 }
 301         }
 302         return rtex;
 303 }
 304
 305 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 306                                                 const struct pipe_resource *templ)
 307 {
 308         unsigned array_mode = 0;
 309
 310         if (debug_get_bool_option("R600_FORCE_TILING", FALSE)) {
 311                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 312                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 313                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 314                 }
 315         }
 316
 317         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 318                                                                   0, 0, NULL);
 319
 320 }
 321
 322 static void r600_texture_destroy(struct pipe_screen *screen,
 323                                  struct pipe_resource *ptex)
 324 {
 325         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 326         struct r600_resource *resource = &rtex->resource;
 327         struct radeon *radeon = (struct radeon *)screen->winsys;
 328
 329         if (rtex->flushed_depth_texture)
 330                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 331
 332         if (resource->bo) {
 333                 r600_bo_reference(radeon, &resource->bo, NULL);
 334         }
 335         FREE(rtex);
 336 }
 337
 338 static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
 339                                                 struct pipe_resource *texture,
 340                                                 unsigned face, unsigned level,
 341                                                 unsigned zslice, unsigned flags)
 342 {
 343         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 344         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 345         unsigned offset, tile_height;
 346
 347         if (surface == NULL)
 348                 return NULL;
 349         offset = r600_texture_get_offset(rtex, level, zslice, face);
 350         pipe_reference_init(&surface->base.reference, 1);
 351         pipe_resource_reference(&surface->base.texture, texture);
 352         surface->base.format = texture->format;
 353         surface->base.width = mip_minify(texture->width0, level);
 354         surface->base.height = mip_minify(texture->height0, level);
 355         surface->base.offset = offset;
 356         surface->base.usage = flags;
 357         surface->base.zslice = zslice;
 358         surface->base.texture = texture;
 359         surface->base.face = face;
 360         surface->base.level = level;
 361
 362         tile_height = r600_get_height_alignment(screen, rtex->array_mode[level]);
 363         surface->aligned_height = align(surface->base.height, tile_height);
 364         return &surface->base;
 365 }
 366
 367 static void r600_tex_surface_destroy(struct pipe_surface *surface)
 368 {
 369         pipe_resource_reference(&surface->texture, NULL);
 370         FREE(surface);
 371 }
 372
 373
 374 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 375                                                const struct pipe_resource *templ,
 376                                                struct winsys_handle *whandle)
 377 {
 378         struct radeon *rw = (struct radeon*)screen->winsys;
 379         struct r600_bo *bo = NULL;
 380         unsigned array_mode = 0;
 381
 382         /* Support only 2D textures without mipmaps */
 383         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 384               templ->depth0 != 1 || templ->last_level != 0)
 385                 return NULL;
 386
 387         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 388         if (bo == NULL) {
 389                 return NULL;
 390         }
 391
 392         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 393                                                                   whandle->stride,
 394                                                                   0,
 395                                                                   bo);
 396 }
 397
 398 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 399                                                 struct pipe_resource *texture,
 400                                                 unsigned face, unsigned level)
 401 {
 402         /* FIXME */
 403         return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 404 }
 405
 406 int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
 407
 408 int r600_texture_depth_flush(struct pipe_context *ctx,
 409                              struct pipe_resource *texture)
 410 {
 411         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 412         struct pipe_resource resource;
 413
 414         if (rtex->flushed_depth_texture)
 415                 goto out;
 416
 417         resource.target = PIPE_TEXTURE_2D;
 418         resource.format = texture->format;
 419         resource.width0 = texture->width0;
 420         resource.height0 = texture->height0;
 421         resource.depth0 = 1;
 422         resource.last_level = 0;
 423         resource.nr_samples = 0;
 424         resource.usage = PIPE_USAGE_DYNAMIC;
 425         resource.bind = 0;
 426         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 427
 428         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 429
 430         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 431         if (rtex->flushed_depth_texture == NULL) {
 432                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 433                 return -ENOMEM;
 434         }
 435
 436 out:
 437         r600_blit_uncompress_depth_ptr(ctx, rtex);
 438         return 0;
 439 }
 440
 441 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 442                                                 struct pipe_resource *texture,
 443                                                 struct pipe_subresource sr,
 444                                                 unsigned usage,
 445                                                 const struct pipe_box *box)
 446 {
 447         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 448         struct pipe_resource resource;
 449         struct r600_transfer *trans;
 450         int r;
 451
 452         trans = CALLOC_STRUCT(r600_transfer);
 453         if (trans == NULL)
 454                 return NULL;
 455         pipe_resource_reference(&trans->transfer.resource, texture);
 456         trans->transfer.sr = sr;
 457         trans->transfer.usage = usage;
 458         trans->transfer.box = *box;
 459         if (rtex->depth) {
 460                 r = r600_texture_depth_flush(ctx, texture);
 461                 if (r < 0) {
 462                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 463                         pipe_resource_reference(&trans->transfer.resource, NULL);
 464                         FREE(trans);
 465                         return NULL;
 466                 }
 467         } else if (rtex->tiled) {
 468                 resource.target = PIPE_TEXTURE_2D;
 469                 resource.format = texture->format;
 470                 resource.width0 = box->width;
 471                 resource.height0 = box->height;
 472                 resource.depth0 = 1;
 473                 resource.last_level = 0;
 474                 resource.nr_samples = 0;
 475                 resource.usage = PIPE_USAGE_DYNAMIC;
 476                 resource.bind = 0;
 477                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 478                 /* For texture reading, the temporary (detiled) texture is used as
 479                  * a render target when blitting from a tiled texture. */
 480                 if (usage & PIPE_TRANSFER_READ) {
 481                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 482                 }
 483                 /* For texture writing, the temporary texture is used as a sampler
 484                  * when blitting into a tiled texture. */
 485                 if (usage & PIPE_TRANSFER_WRITE) {
 486                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 487                 }
 488                 /* Create the temporary texture. */
 489                 trans->linear_texture = ctx->screen->resource_create(ctx->screen, &resource);
 490                 if (trans->linear_texture == NULL) {
 491                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 492                         pipe_resource_reference(&trans->transfer.resource, NULL);
 493                         FREE(trans);
 494                         return NULL;
 495                 }
 496
 497                 trans->transfer.stride =
 498                   ((struct r600_resource_texture *)trans->linear_texture)->pitch_in_bytes[0];
 499                 if (usage & PIPE_TRANSFER_READ) {
 500                         /* We cannot map a tiled texture directly because the data is
 501                          * in a different order, therefore we do detiling using a blit. */
 502                         r600_copy_from_tiled_texture(ctx, trans);
 503                         /* Always referenced in the blit. */
 504                         ctx->flush(ctx, 0, NULL);
 505                 }
 506                 return &trans->transfer;
 507         }
 508         trans->transfer.stride = rtex->pitch_in_bytes[sr.level];
 509         trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
 510         return &trans->transfer;
 511 }
 512
 513 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 514                                    struct pipe_transfer *transfer)
 515 {
 516         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 517         struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 518
 519         if (rtransfer->linear_texture) {
 520                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 521                         r600_copy_into_tiled_texture(ctx, rtransfer);
 522                 }
 523                 pipe_resource_reference(&rtransfer->linear_texture, NULL);
 524         }
 525         if (rtex->flushed_depth_texture) {
 526                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 527         }
 528         pipe_resource_reference(&transfer->resource, NULL);
 529         FREE(transfer);
 530 }
 531
 532 void* r600_texture_transfer_map(struct pipe_context *ctx,
 533                                 struct pipe_transfer* transfer)
 534 {
 535         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 536         struct r600_bo *bo;
 537         enum pipe_format format = transfer->resource->format;
 538         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 539         unsigned offset = 0;
 540         char *map;
 541
 542         if (rtransfer->linear_texture) {
 543                 bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 544         } else {
 545                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 546
 547                 if (rtex->flushed_depth_texture)
 548                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 549                 else
 550                         bo = ((struct r600_resource *)transfer->resource)->bo;
 551
 552                 offset = rtransfer->offset +
 553                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 554                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 555         }
 556         map = r600_bo_map(radeon, bo, 0, ctx);
 557         if (!map) {
 558                 return NULL;
 559         }
 560
 561         return map + offset;
 562 }
 563
 564 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 565                                  struct pipe_transfer* transfer)
 566 {
 567         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 568         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 569         struct r600_bo *bo;
 570
 571         if (rtransfer->linear_texture) {
 572                 bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 573         } else {
 574                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 575
 576                 if (rtex->flushed_depth_texture) {
 577                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 578                 } else {
 579                         bo = ((struct r600_resource *)transfer->resource)->bo;
 580                 }
 581         }
 582         r600_bo_unmap(radeon, bo);
 583 }
 584
 585 struct u_resource_vtbl r600_texture_vtbl =
 586 {
 587         u_default_resource_get_handle,  /* get_handle */
 588         r600_texture_destroy,           /* resource_destroy */
 589         r600_texture_is_referenced,     /* is_resource_referenced */
 590         r600_texture_get_transfer,      /* get_transfer */
 591         r600_texture_transfer_destroy,  /* transfer_destroy */
 592         r600_texture_transfer_map,      /* transfer_map */
 593         u_default_transfer_flush_region,/* transfer_flush_region */
 594         r600_texture_transfer_unmap,    /* transfer_unmap */
 595         u_default_transfer_inline_write /* transfer_inline_write */
 596 };
 597
 598 void r600_init_screen_texture_functions(struct pipe_screen *screen)
 599 {
 600         screen->get_tex_surface = r600_get_tex_surface;
 601         screen->tex_surface_destroy = r600_tex_surface_destroy;
 602 }
 603
 604 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 605                 const unsigned char *swizzle_view)
 606 {
 607         unsigned i;
 608         unsigned char swizzle[4];
 609         unsigned result = 0;
 610         const uint32_t swizzle_shift[4] = {
 611                 16, 19, 22, 25,
 612         };
 613         const uint32_t swizzle_bit[4] = {
 614                 0, 1, 2, 3,
 615         };
 616
 617         if (swizzle_view) {
 618                 /* Combine two sets of swizzles. */
 619                 for (i = 0; i < 4; i++) {
 620                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 621                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 622                 }
 623         } else {
 624                 memcpy(swizzle, swizzle_format, 4);
 625         }
 626
 627         /* Get swizzle. */
 628         for (i = 0; i < 4; i++) {
 629                 switch (swizzle[i]) {
 630                 case UTIL_FORMAT_SWIZZLE_Y:
 631                         result |= swizzle_bit[1] << swizzle_shift[i];
 632                         break;
 633                 case UTIL_FORMAT_SWIZZLE_Z:
 634                         result |= swizzle_bit[2] << swizzle_shift[i];
 635                         break;
 636                 case UTIL_FORMAT_SWIZZLE_W:
 637                         result |= swizzle_bit[3] << swizzle_shift[i];
 638                         break;
 639                 case UTIL_FORMAT_SWIZZLE_0:
 640                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 641                         break;
 642                 case UTIL_FORMAT_SWIZZLE_1:
 643                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 644                         break;
 645                 default: /* UTIL_FORMAT_SWIZZLE_X */
 646                         result |= swizzle_bit[0] << swizzle_shift[i];
 647                 }
 648         }
 649         return result;
 650 }
 651
 652 /* texture format translate */
 653 uint32_t r600_translate_texformat(enum pipe_format format,
 654                                   const unsigned char *swizzle_view,
 655                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 656 {
 657         uint32_t result = 0, word4 = 0, yuv_format = 0;
 658         const struct util_format_description *desc;
 659         boolean uniform = TRUE;
 660         int i;
 661         const uint32_t sign_bit[4] = {
 662                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 663                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 664                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 665                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 666         };
 667         desc = util_format_description(format);
 668
 669         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 670
 671         /* Colorspace (return non-RGB formats directly). */
 672         switch (desc->colorspace) {
 673                 /* Depth stencil formats */
 674         case UTIL_FORMAT_COLORSPACE_ZS:
 675                 switch (format) {
 676                 case PIPE_FORMAT_Z16_UNORM:
 677                         result = FMT_16;
 678                         goto out_word4;
 679                 case PIPE_FORMAT_X24S8_USCALED:
 680                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 681                 case PIPE_FORMAT_Z24X8_UNORM:
 682                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 683                         result = FMT_8_24;
 684                         goto out_word4;
 685                 case PIPE_FORMAT_S8X24_USCALED:
 686                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 687                 case PIPE_FORMAT_X8Z24_UNORM:
 688                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 689                         result = FMT_24_8;
 690                         goto out_word4;
 691                 case PIPE_FORMAT_S8_USCALED:
 692                         result = V_0280A0_COLOR_8;
 693                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 694                         goto out_word4;
 695                 default:
 696                         goto out_unknown;
 697                 }
 698
 699         case UTIL_FORMAT_COLORSPACE_YUV:
 700                 yuv_format |= (1 << 30);
 701                 switch (format) {
 702                 case PIPE_FORMAT_UYVY:
 703                 case PIPE_FORMAT_YUYV:
 704                 default:
 705                         break;
 706                 }
 707                 goto out_unknown; /* TODO */
 708
 709         case UTIL_FORMAT_COLORSPACE_SRGB:
 710                 word4 |= S_038010_FORCE_DEGAMMA(1);
 711                 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
 712                         goto out_unknown; /* fails for some reason - TODO */
 713                 break;
 714
 715         default:
 716                 break;
 717         }
 718
 719         /* S3TC formats. TODO */
 720         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 721                 goto out_unknown;
 722         }
 723
 724
 725         for (i = 0; i < desc->nr_channels; i++) {
 726                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 727                         word4 |= sign_bit[i];
 728                 }
 729         }
 730
 731         /* R8G8Bx_SNORM - TODO CxV8U8 */
 732
 733         /* RGTC - TODO */
 734
 735         /* See whether the components are of the same size. */
 736         for (i = 1; i < desc->nr_channels; i++) {
 737                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 738         }
 739
 740         /* Non-uniform formats. */
 741         if (!uniform) {
 742                 switch(desc->nr_channels) {
 743                 case 3:
 744                         if (desc->channel[0].size == 5 &&
 745                             desc->channel[1].size == 6 &&
 746                             desc->channel[2].size == 5) {
 747                                 result = FMT_5_6_5;
 748                                 goto out_word4;
 749                         }
 750                         goto out_unknown;
 751                 case 4:
 752                         if (desc->channel[0].size == 5 &&
 753                             desc->channel[1].size == 5 &&
 754                             desc->channel[2].size == 5 &&
 755                             desc->channel[3].size == 1) {
 756                                 result = FMT_1_5_5_5;
 757                                 goto out_word4;
 758                         }
 759                         if (desc->channel[0].size == 10 &&
 760                             desc->channel[1].size == 10 &&
 761                             desc->channel[2].size == 10 &&
 762                             desc->channel[3].size == 2) {
 763                                 result = FMT_10_10_10_2;
 764                                 goto out_word4;
 765                         }
 766                         goto out_unknown;
 767                 }
 768                 goto out_unknown;
 769         }
 770
 771         /* Find the first non-VOID channel. */
 772         for (i = 0; i < 4; i++) {
 773                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 774                         break;
 775                 }
 776         }
 777
 778         if (i == 4)
 779                 goto out_unknown;
 780
 781         /* uniform formats */
 782         switch (desc->channel[i].type) {
 783         case UTIL_FORMAT_TYPE_UNSIGNED:
 784         case UTIL_FORMAT_TYPE_SIGNED:
 785                 if (!desc->channel[i].normalized &&
 786                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 787                         goto out_unknown;
 788                 }
 789
 790                 switch (desc->channel[i].size) {
 791                 case 4:
 792                         switch (desc->nr_channels) {
 793                         case 2:
 794                                 result = FMT_4_4;
 795                                 goto out_word4;
 796                         case 4:
 797                                 result = FMT_4_4_4_4;
 798                                 goto out_word4;
 799                         }
 800                         goto out_unknown;
 801                 case 8:
 802                         switch (desc->nr_channels) {
 803                         case 1:
 804                                 result = FMT_8;
 805                                 goto out_word4;
 806                         case 2:
 807                                 result = FMT_8_8;
 808                                 goto out_word4;
 809                         case 4:
 810                                 result = FMT_8_8_8_8;
 811                                 goto out_word4;
 812                         }
 813                         goto out_unknown;
 814                 case 16:
 815                         switch (desc->nr_channels) {
 816                         case 1:
 817                                 result = FMT_16;
 818                                 goto out_word4;
 819                         case 2:
 820                                 result = FMT_16_16;
 821                                 goto out_word4;
 822                         case 4:
 823                                 result = FMT_16_16_16_16;
 824                                 goto out_word4;
 825                         }
 826                 }
 827                 goto out_unknown;
 828
 829         case UTIL_FORMAT_TYPE_FLOAT:
 830                 switch (desc->channel[i].size) {
 831                 case 16:
 832                         switch (desc->nr_channels) {
 833                         case 1:
 834                                 result = FMT_16_FLOAT;
 835                                 goto out_word4;
 836                         case 2:
 837                                 result = FMT_16_16_FLOAT;
 838                                 goto out_word4;
 839                         case 4:
 840                                 result = FMT_16_16_16_16_FLOAT;
 841                                 goto out_word4;
 842                         }
 843                         goto out_unknown;
 844                 case 32:
 845                         switch (desc->nr_channels) {
 846                         case 1:
 847                                 result = FMT_32_FLOAT;
 848                                 goto out_word4;
 849                         case 2:
 850                                 result = FMT_32_32_FLOAT;
 851                                 goto out_word4;
 852                         case 4:
 853                                 result = FMT_32_32_32_32_FLOAT;
 854                                 goto out_word4;
 855                         }
 856                 }
 857
 858         }
 859 out_word4:
 860         if (word4_p)
 861                 *word4_p = word4;
 862         if (yuv_format_p)
 863                 *yuv_format_p = yuv_format;
 864         return result;
 865 out_unknown:
 866 //      R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
 867         return ~0;
 868 }