src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_format_s3tc.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "state_tracker/drm_driver.h"
  35 #include "pipebuffer/pb_buffer.h"
  36 #include "r600_pipe.h"
  37 #include "r600_resource.h"
  38 #include "r600_state_inlines.h"
  39 #include "r600d.h"
  40 #include "r600_formats.h"
  41
  42 /* Copy from a full GPU texture to a transfer's staging one. */
  43 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  44 {
  45         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  46         struct pipe_resource *texture = transfer->resource;
  47
  48         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  49                                 0, 0, 0, 0, texture, transfer->level,
  50                                 &transfer->box);
  51 }
  52
  53
  54 /* Copy from a transfer's staging texture to a full GPU one. */
  55 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  56 {
  57         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  58         struct pipe_resource *texture = transfer->resource;
  59         struct pipe_box sbox;
  60
  61         sbox.x = sbox.y = sbox.z = 0;
  62         sbox.width = transfer->box.width;
  63         sbox.height = transfer->box.height;
  64         /* XXX that might be wrong */
  65         sbox.depth = 1;
  66         ctx->resource_copy_region(ctx, texture, transfer->level,
  67                                   transfer->box.x, transfer->box.y, transfer->box.z,
  68                                   rtransfer->staging_texture,
  69                                   0, &sbox);
  70
  71         ctx->flush(ctx, NULL);
  72 }
  73
  74 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  75                                         unsigned level, unsigned layer)
  76 {
  77         unsigned offset = rtex->offset[level];
  78
  79         switch (rtex->resource.b.b.b.target) {
  80         case PIPE_TEXTURE_3D:
  81         case PIPE_TEXTURE_CUBE:
  82         default:
  83                 return offset + layer * rtex->layer_size[level];
  84         }
  85 }
  86
  87 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
  88                                          enum pipe_format format,
  89                                          unsigned array_mode)
  90 {
  91         struct r600_screen* rscreen = (struct r600_screen *)screen;
  92         unsigned pixsize = util_format_get_blocksize(format);
  93         int p_align;
  94
  95         switch(array_mode) {
  96         case V_038000_ARRAY_1D_TILED_THIN1:
  97                 p_align = MAX2(8,
  98                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
  99                 break;
 100         case V_038000_ARRAY_2D_TILED_THIN1:
 101                 p_align = MAX2(rscreen->tiling_info->num_banks,
 102                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 103                                 rscreen->tiling_info->num_banks)) * 8;
 104                 break;
 105         case V_038000_ARRAY_LINEAR_ALIGNED:
 106                 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
 107                 break;
 108         case V_038000_ARRAY_LINEAR_GENERAL:
 109         default:
 110                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 111                 break;
 112         }
 113         return p_align;
 114 }
 115
 116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 117                                           unsigned array_mode)
 118 {
 119         struct r600_screen* rscreen = (struct r600_screen *)screen;
 120         int h_align;
 121
 122         switch (array_mode) {
 123         case V_038000_ARRAY_2D_TILED_THIN1:
 124                 h_align = rscreen->tiling_info->num_channels * 8;
 125                 break;
 126         case V_038000_ARRAY_1D_TILED_THIN1:
 127         case V_038000_ARRAY_LINEAR_ALIGNED:
 128                 h_align = 8;
 129                 break;
 130         case V_038000_ARRAY_LINEAR_GENERAL:
 131         default:
 132                 h_align = 1;
 133                 break;
 134         }
 135         return h_align;
 136 }
 137
 138 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 139                                         enum pipe_format format,
 140                                         unsigned array_mode)
 141 {
 142         struct r600_screen* rscreen = (struct r600_screen *)screen;
 143         unsigned pixsize = util_format_get_blocksize(format);
 144         int p_align = r600_get_block_alignment(screen, format, array_mode);
 145         int h_align = r600_get_height_alignment(screen, array_mode);
 146         int b_align;
 147
 148         switch (array_mode) {
 149         case V_038000_ARRAY_2D_TILED_THIN1:
 150                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 151                                p_align * pixsize * h_align);
 152                 break;
 153         case V_038000_ARRAY_1D_TILED_THIN1:
 154         case V_038000_ARRAY_LINEAR_ALIGNED:
 155         case V_038000_ARRAY_LINEAR_GENERAL:
 156         default:
 157                 b_align = rscreen->tiling_info->group_bytes;
 158                 break;
 159         }
 160         return b_align;
 161 }
 162
 163 static unsigned mip_minify(unsigned size, unsigned level)
 164 {
 165         unsigned val;
 166         val = u_minify(size, level);
 167         if (level > 0)
 168                 val = util_next_power_of_two(val);
 169         return val;
 170 }
 171
 172 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
 173                                           struct r600_resource_texture *rtex,
 174                                           unsigned level)
 175 {
 176         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 177         unsigned nblocksx, block_align, width;
 178         unsigned blocksize = util_format_get_blocksize(ptex->format);
 179
 180         if (rtex->pitch_override)
 181                 return rtex->pitch_override / blocksize;
 182
 183         width = mip_minify(ptex->width0, level);
 184         nblocksx = util_format_get_nblocksx(ptex->format, width);
 185
 186         block_align = r600_get_block_alignment(screen, ptex->format,
 187                                               rtex->array_mode[level]);
 188         nblocksx = align(nblocksx, block_align);
 189         return nblocksx;
 190 }
 191
 192 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 193                                           struct r600_resource_texture *rtex,
 194                                           unsigned level)
 195 {
 196         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 197         unsigned height, tile_height;
 198
 199         height = mip_minify(ptex->height0, level);
 200         height = util_format_get_nblocksy(ptex->format, height);
 201         tile_height = r600_get_height_alignment(screen,
 202                                                 rtex->array_mode[level]);
 203         height = align(height, tile_height);
 204         return height;
 205 }
 206
 207 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 208                                         struct r600_resource_texture *rtex,
 209                                         unsigned level, unsigned array_mode)
 210 {
 211         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 212
 213         switch (array_mode) {
 214         case V_0280A0_ARRAY_LINEAR_GENERAL:
 215         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 216         case V_0280A0_ARRAY_1D_TILED_THIN1:
 217         default:
 218                 rtex->array_mode[level] = array_mode;
 219                 break;
 220         case V_0280A0_ARRAY_2D_TILED_THIN1:
 221         {
 222                 unsigned w, h, tile_height, tile_width;
 223
 224                 tile_height = r600_get_height_alignment(screen, array_mode);
 225                 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
 226
 227                 w = mip_minify(ptex->width0, level);
 228                 h = mip_minify(ptex->height0, level);
 229                 if (w <= tile_width || h <= tile_height)
 230                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 231                 else
 232                         rtex->array_mode[level] = array_mode;
 233         }
 234         break;
 235         }
 236 }
 237
 238 static void r600_setup_miptree(struct pipe_screen *screen,
 239                                struct r600_resource_texture *rtex,
 240                                unsigned array_mode)
 241 {
 242         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 243         struct radeon *radeon = (struct radeon *)screen->winsys;
 244         enum chip_class chipc = r600_get_family_class(radeon);
 245         unsigned size, layer_size, i, offset;
 246         unsigned nblocksx, nblocksy;
 247
 248         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 249                 unsigned blocksize = util_format_get_blocksize(ptex->format);
 250
 251                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 252
 253                 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 254                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 255
 256                 layer_size = nblocksx * nblocksy * blocksize;
 257                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 258                         if (chipc >= R700)
 259                                 size = layer_size * 8;
 260                         else
 261                                 size = layer_size * 6;
 262                 }
 263                 else if (ptex->target == PIPE_TEXTURE_3D)
 264                         size = layer_size * u_minify(ptex->depth0, i);
 265                 else
 266                         size = layer_size * ptex->array_size;
 267
 268                 /* align base image and start of miptree */
 269                 if ((i == 0) || (i == 1))
 270                         offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
 271                 rtex->offset[i] = offset;
 272                 rtex->layer_size[i] = layer_size;
 273                 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
 274                 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
 275
 276                 offset += size;
 277         }
 278         rtex->size = offset;
 279 }
 280
 281 /* Figure out whether u_blitter will fallback to a transfer operation.
 282  * If so, don't use a staging resource.
 283  */
 284 static boolean permit_hardware_blit(struct pipe_screen *screen,
 285                                         const struct pipe_resource *res)
 286 {
 287         unsigned bind;
 288
 289         if (util_format_is_depth_or_stencil(res->format))
 290                 bind = PIPE_BIND_DEPTH_STENCIL;
 291         else
 292                 bind = PIPE_BIND_RENDER_TARGET;
 293
 294         /* hackaround for S3TC */
 295         if (util_format_is_compressed(res->format))
 296                 return TRUE;
 297
 298         if (!screen->is_format_supported(screen,
 299                                 res->format,
 300                                 res->target,
 301                                 res->nr_samples,
 302                                 bind))
 303                 return FALSE;
 304
 305         if (!screen->is_format_supported(screen,
 306                                 res->format,
 307                                 res->target,
 308                                 res->nr_samples,
 309                                 PIPE_BIND_SAMPLER_VIEW))
 310                 return FALSE;
 311
 312         switch (res->usage) {
 313         case PIPE_USAGE_STREAM:
 314         case PIPE_USAGE_STAGING:
 315         case PIPE_USAGE_STATIC:
 316         case PIPE_USAGE_IMMUTABLE:
 317                 return FALSE;
 318
 319         default:
 320                 return TRUE;
 321         }
 322 }
 323
 324 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 325                                         struct pipe_resource *ptex,
 326                                         struct winsys_handle *whandle)
 327 {
 328         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 329         struct r600_resource *resource = &rtex->resource;
 330         struct radeon *radeon = (struct radeon *)screen->winsys;
 331
 332         return r600_bo_get_winsys_handle(radeon, resource->bo,
 333                         rtex->pitch_in_bytes[0], whandle);
 334 }
 335
 336 static void r600_texture_destroy(struct pipe_screen *screen,
 337                                  struct pipe_resource *ptex)
 338 {
 339         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 340         struct r600_resource *resource = &rtex->resource;
 341         struct radeon *radeon = (struct radeon *)screen->winsys;
 342
 343         if (rtex->flushed_depth_texture)
 344                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 345
 346         if (resource->bo) {
 347                 r600_bo_reference(radeon, &resource->bo, NULL);
 348         }
 349         FREE(rtex);
 350 }
 351
 352 static const struct u_resource_vtbl r600_texture_vtbl =
 353 {
 354         r600_texture_get_handle,        /* get_handle */
 355         r600_texture_destroy,           /* resource_destroy */
 356         r600_texture_get_transfer,      /* get_transfer */
 357         r600_texture_transfer_destroy,  /* transfer_destroy */
 358         r600_texture_transfer_map,      /* transfer_map */
 359         u_default_transfer_flush_region,/* transfer_flush_region */
 360         r600_texture_transfer_unmap,    /* transfer_unmap */
 361         u_default_transfer_inline_write /* transfer_inline_write */
 362 };
 363
 364 static struct r600_resource_texture *
 365 r600_texture_create_object(struct pipe_screen *screen,
 366                            const struct pipe_resource *base,
 367                            unsigned array_mode,
 368                            unsigned pitch_in_bytes_override,
 369                            unsigned max_buffer_size,
 370                            struct r600_bo *bo)
 371 {
 372         struct r600_resource_texture *rtex;
 373         struct r600_resource *resource;
 374         struct radeon *radeon = (struct radeon *)screen->winsys;
 375
 376         rtex = CALLOC_STRUCT(r600_resource_texture);
 377         if (rtex == NULL)
 378                 return NULL;
 379
 380         resource = &rtex->resource;
 381         resource->b.b.b = *base;
 382         resource->b.b.vtbl = &r600_texture_vtbl;
 383         pipe_reference_init(&resource->b.b.b.reference, 1);
 384         resource->b.b.b.screen = screen;
 385         resource->bo = bo;
 386         rtex->pitch_override = pitch_in_bytes_override;
 387         /* only mark depth textures the HW can hit as depth textures */
 388         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 389                 rtex->depth = 1;
 390
 391         r600_setup_miptree(screen, rtex, array_mode);
 392
 393         resource->size = rtex->size;
 394
 395         if (!resource->bo) {
 396                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 397                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 398
 399                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 400                 if (!resource->bo) {
 401                         FREE(rtex);
 402                         return NULL;
 403                 }
 404         }
 405         return rtex;
 406 }
 407
 408 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 409                                                 const struct pipe_resource *templ)
 410 {
 411         unsigned array_mode = 0;
 412         static int force_tiling = -1;
 413
 414         /* Would like some magic "get_bool_option_once" routine.
 415          */
 416         if (force_tiling == -1) {
 417 #if 0
 418                 /* reenable when 2D tiling is fixed better */
 419                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 420                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 421                         force_tiling = debug_get_bool_option("R600_TILING", TRUE);
 422 #endif
 423                 force_tiling = debug_get_bool_option("R600_TILING", FALSE);
 424         }
 425
 426         if (force_tiling && permit_hardware_blit(screen, templ)) {
 427                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 428                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 429                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 430                 }
 431         }
 432
 433         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 434             util_format_is_compressed(templ->format))
 435                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 436
 437         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 438                                                                   0, 0, NULL);
 439
 440 }
 441
 442 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 443                                                 struct pipe_resource *texture,
 444                                                 const struct pipe_surface *surf_tmpl)
 445 {
 446         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 447         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 448         unsigned level = surf_tmpl->u.tex.level;
 449
 450         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 451         if (surface == NULL)
 452                 return NULL;
 453         /* XXX no offset */
 454 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 455         pipe_reference_init(&surface->base.reference, 1);
 456         pipe_resource_reference(&surface->base.texture, texture);
 457         surface->base.context = pipe;
 458         surface->base.format = surf_tmpl->format;
 459         surface->base.width = mip_minify(texture->width0, level);
 460         surface->base.height = mip_minify(texture->height0, level);
 461         surface->base.usage = surf_tmpl->usage;
 462         surface->base.texture = texture;
 463         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 464         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 465         surface->base.u.tex.level = level;
 466
 467         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 468                                                             rtex, level);
 469         return &surface->base;
 470 }
 471
 472 static void r600_surface_destroy(struct pipe_context *pipe,
 473                                  struct pipe_surface *surface)
 474 {
 475         pipe_resource_reference(&surface->texture, NULL);
 476         FREE(surface);
 477 }
 478
 479
 480 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 481                                                const struct pipe_resource *templ,
 482                                                struct winsys_handle *whandle)
 483 {
 484         struct radeon *rw = (struct radeon*)screen->winsys;
 485         struct r600_bo *bo = NULL;
 486         unsigned array_mode = 0;
 487
 488         /* Support only 2D textures without mipmaps */
 489         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 490               templ->depth0 != 1 || templ->last_level != 0)
 491                 return NULL;
 492
 493         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 494         if (bo == NULL) {
 495                 return NULL;
 496         }
 497
 498         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 499                                                                   whandle->stride,
 500                                                                   0,
 501                                                                   bo);
 502 }
 503
 504 int r600_texture_depth_flush(struct pipe_context *ctx,
 505                              struct pipe_resource *texture, boolean just_create)
 506 {
 507         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 508         struct pipe_resource resource;
 509
 510         if (rtex->flushed_depth_texture)
 511                 goto out;
 512
 513         resource.target = PIPE_TEXTURE_2D;
 514         resource.format = texture->format;
 515         resource.width0 = texture->width0;
 516         resource.height0 = texture->height0;
 517         resource.depth0 = 1;
 518         resource.array_size = 1;
 519         resource.last_level = texture->last_level;
 520         resource.nr_samples = 0;
 521         resource.usage = PIPE_USAGE_DYNAMIC;
 522         resource.bind = 0;
 523         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 524
 525         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 526
 527         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 528         if (rtex->flushed_depth_texture == NULL) {
 529                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 530                 return -ENOMEM;
 531         }
 532
 533         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 534 out:
 535         if (just_create)
 536                 return 0;
 537
 538         /* XXX: only do this if the depth texture has actually changed:
 539          */
 540         r600_blit_uncompress_depth(ctx, rtex);
 541         return 0;
 542 }
 543
 544 /* Needs adjustment for pixelformat:
 545  */
 546 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 547 {
 548         return box->width * box->depth * box->height;
 549 };
 550
 551 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 552                                                 struct pipe_resource *texture,
 553                                                 unsigned level,
 554                                                 unsigned usage,
 555                                                 const struct pipe_box *box)
 556 {
 557         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 558         struct pipe_resource resource;
 559         struct r600_transfer *trans;
 560         int r;
 561         boolean use_staging_texture = FALSE;
 562
 563         /* We cannot map a tiled texture directly because the data is
 564          * in a different order, therefore we do detiling using a blit.
 565          *
 566          * Also, use a temporary in GTT memory for read transfers, as
 567          * the CPU is much happier reading out of cached system memory
 568          * than uncached VRAM.
 569          */
 570         if (R600_TEX_IS_TILED(rtex, level))
 571                 use_staging_texture = TRUE;
 572
 573         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 574                 use_staging_texture = TRUE;
 575
 576         /* XXX: Use a staging texture for uploads if the underlying BO
 577          * is busy.  No interface for checking that currently? so do
 578          * it eagerly whenever the transfer doesn't require a readback
 579          * and might block.
 580          */
 581         if ((usage & PIPE_TRANSFER_WRITE) &&
 582                         !(usage & (PIPE_TRANSFER_READ |
 583                                         PIPE_TRANSFER_DONTBLOCK |
 584                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 585                 use_staging_texture = TRUE;
 586
 587         if (!permit_hardware_blit(ctx->screen, texture) ||
 588                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 589                 use_staging_texture = FALSE;
 590
 591         trans = CALLOC_STRUCT(r600_transfer);
 592         if (trans == NULL)
 593                 return NULL;
 594         pipe_resource_reference(&trans->transfer.resource, texture);
 595         trans->transfer.level = level;
 596         trans->transfer.usage = usage;
 597         trans->transfer.box = *box;
 598         if (rtex->depth) {
 599                 /* XXX: only readback the rectangle which is being mapped?
 600                 */
 601                 /* XXX: when discard is true, no need to read back from depth texture
 602                 */
 603                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 604                 if (r < 0) {
 605                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 606                         pipe_resource_reference(&trans->transfer.resource, NULL);
 607                         FREE(trans);
 608                         return NULL;
 609                 }
 610                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 611                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 612                 return &trans->transfer;
 613         } else if (use_staging_texture) {
 614                 resource.target = PIPE_TEXTURE_2D;
 615                 resource.format = texture->format;
 616                 resource.width0 = box->width;
 617                 resource.height0 = box->height;
 618                 resource.depth0 = 1;
 619                 resource.array_size = 1;
 620                 resource.last_level = 0;
 621                 resource.nr_samples = 0;
 622                 resource.usage = PIPE_USAGE_STAGING;
 623                 resource.bind = 0;
 624                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 625                 /* For texture reading, the temporary (detiled) texture is used as
 626                  * a render target when blitting from a tiled texture. */
 627                 if (usage & PIPE_TRANSFER_READ) {
 628                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 629                 }
 630                 /* For texture writing, the temporary texture is used as a sampler
 631                  * when blitting into a tiled texture. */
 632                 if (usage & PIPE_TRANSFER_WRITE) {
 633                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 634                 }
 635                 /* Create the temporary texture. */
 636                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 637                 if (trans->staging_texture == NULL) {
 638                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 639                         pipe_resource_reference(&trans->transfer.resource, NULL);
 640                         FREE(trans);
 641                         return NULL;
 642                 }
 643
 644                 trans->transfer.stride =
 645                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 646                 if (usage & PIPE_TRANSFER_READ) {
 647                         r600_copy_to_staging_texture(ctx, trans);
 648                         /* Always referenced in the blit. */
 649                         ctx->flush(ctx, NULL);
 650                 }
 651                 return &trans->transfer;
 652         }
 653         trans->transfer.stride = rtex->pitch_in_bytes[level];
 654         trans->transfer.layer_stride = rtex->layer_size[level];
 655         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 656         return &trans->transfer;
 657 }
 658
 659 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 660                                    struct pipe_transfer *transfer)
 661 {
 662         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 663         struct pipe_resource *texture = transfer->resource;
 664         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 665
 666         if (rtransfer->staging_texture) {
 667                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 668                         r600_copy_from_staging_texture(ctx, rtransfer);
 669                 }
 670                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 671         }
 672
 673         if (rtex->depth && !rtex->is_flushing_texture) {
 674                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 675                         r600_blit_push_depth(ctx, rtex);
 676         }
 677
 678         pipe_resource_reference(&transfer->resource, NULL);
 679         FREE(transfer);
 680 }
 681
 682 void* r600_texture_transfer_map(struct pipe_context *ctx,
 683                                 struct pipe_transfer* transfer)
 684 {
 685         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 686         struct r600_bo *bo;
 687         enum pipe_format format = transfer->resource->format;
 688         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 689         unsigned offset = 0;
 690         unsigned usage = 0;
 691         char *map;
 692
 693         if (rtransfer->staging_texture) {
 694                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 695         } else {
 696                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 697
 698                 if (rtex->flushed_depth_texture)
 699                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 700                 else
 701                         bo = ((struct r600_resource *)transfer->resource)->bo;
 702
 703                 offset = rtransfer->offset +
 704                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 705                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 706         }
 707
 708         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 709                 usage |= PB_USAGE_CPU_WRITE;
 710
 711                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 712                 }
 713
 714                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 715                 }
 716         }
 717
 718         if (transfer->usage & PIPE_TRANSFER_READ) {
 719                 usage |= PB_USAGE_CPU_READ;
 720         }
 721
 722         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 723                 usage |= PB_USAGE_DONTBLOCK;
 724         }
 725
 726         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 727                 usage |= PB_USAGE_UNSYNCHRONIZED;
 728         }
 729
 730         map = r600_bo_map(radeon, bo, usage, ctx);
 731         if (!map) {
 732                 return NULL;
 733         }
 734
 735         return map + offset;
 736 }
 737
 738 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 739                                  struct pipe_transfer* transfer)
 740 {
 741         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 742         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 743         struct r600_bo *bo;
 744
 745         if (rtransfer->staging_texture) {
 746                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 747         } else {
 748                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 749
 750                 if (rtex->flushed_depth_texture) {
 751                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 752                 } else {
 753                         bo = ((struct r600_resource *)transfer->resource)->bo;
 754                 }
 755         }
 756         r600_bo_unmap(radeon, bo);
 757 }
 758
 759 void r600_init_surface_functions(struct r600_pipe_context *r600)
 760 {
 761         r600->context.create_surface = r600_create_surface;
 762         r600->context.surface_destroy = r600_surface_destroy;
 763 }
 764
 765 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 766                 const unsigned char *swizzle_view)
 767 {
 768         unsigned i;
 769         unsigned char swizzle[4];
 770         unsigned result = 0;
 771         const uint32_t swizzle_shift[4] = {
 772                 16, 19, 22, 25,
 773         };
 774         const uint32_t swizzle_bit[4] = {
 775                 0, 1, 2, 3,
 776         };
 777
 778         if (swizzle_view) {
 779                 /* Combine two sets of swizzles. */
 780                 for (i = 0; i < 4; i++) {
 781                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 782                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 783                 }
 784         } else {
 785                 memcpy(swizzle, swizzle_format, 4);
 786         }
 787
 788         /* Get swizzle. */
 789         for (i = 0; i < 4; i++) {
 790                 switch (swizzle[i]) {
 791                 case UTIL_FORMAT_SWIZZLE_Y:
 792                         result |= swizzle_bit[1] << swizzle_shift[i];
 793                         break;
 794                 case UTIL_FORMAT_SWIZZLE_Z:
 795                         result |= swizzle_bit[2] << swizzle_shift[i];
 796                         break;
 797                 case UTIL_FORMAT_SWIZZLE_W:
 798                         result |= swizzle_bit[3] << swizzle_shift[i];
 799                         break;
 800                 case UTIL_FORMAT_SWIZZLE_0:
 801                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 802                         break;
 803                 case UTIL_FORMAT_SWIZZLE_1:
 804                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 805                         break;
 806                 default: /* UTIL_FORMAT_SWIZZLE_X */
 807                         result |= swizzle_bit[0] << swizzle_shift[i];
 808                 }
 809         }
 810         return result;
 811 }
 812
 813 /* texture format translate */
 814 uint32_t r600_translate_texformat(struct pipe_screen *screen,
 815                                   enum pipe_format format,
 816                                   const unsigned char *swizzle_view,
 817                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 818 {
 819         uint32_t result = 0, word4 = 0, yuv_format = 0;
 820         const struct util_format_description *desc;
 821         boolean uniform = TRUE;
 822         static int r600_enable_s3tc = -1;
 823
 824         int i;
 825         const uint32_t sign_bit[4] = {
 826                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 827                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 828                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 829                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 830         };
 831         desc = util_format_description(format);
 832
 833         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 834
 835         /* Colorspace (return non-RGB formats directly). */
 836         switch (desc->colorspace) {
 837                 /* Depth stencil formats */
 838         case UTIL_FORMAT_COLORSPACE_ZS:
 839                 switch (format) {
 840                 case PIPE_FORMAT_Z16_UNORM:
 841                         result = FMT_16;
 842                         goto out_word4;
 843                 case PIPE_FORMAT_X24S8_USCALED:
 844                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 845                 case PIPE_FORMAT_Z24X8_UNORM:
 846                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 847                         result = FMT_8_24;
 848                         goto out_word4;
 849                 case PIPE_FORMAT_S8X24_USCALED:
 850                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 851                 case PIPE_FORMAT_X8Z24_UNORM:
 852                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 853                         result = FMT_24_8;
 854                         goto out_word4;
 855                 case PIPE_FORMAT_S8_USCALED:
 856                         result = FMT_8;
 857                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 858                         goto out_word4;
 859                 default:
 860                         goto out_unknown;
 861                 }
 862
 863         case UTIL_FORMAT_COLORSPACE_YUV:
 864                 yuv_format |= (1 << 30);
 865                 switch (format) {
 866                 case PIPE_FORMAT_UYVY:
 867                 case PIPE_FORMAT_YUYV:
 868                 default:
 869                         break;
 870                 }
 871                 goto out_unknown; /* TODO */
 872
 873         case UTIL_FORMAT_COLORSPACE_SRGB:
 874                 word4 |= S_038010_FORCE_DEGAMMA(1);
 875                 break;
 876
 877         default:
 878                 break;
 879         }
 880
 881         if (r600_enable_s3tc == -1) {
 882                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 883                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 884                         r600_enable_s3tc = 1;
 885                 else
 886                         r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 887         }
 888
 889         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 890                 if (!r600_enable_s3tc)
 891                         goto out_unknown;
 892
 893                 switch (format) {
 894                 case PIPE_FORMAT_RGTC1_SNORM:
 895                 case PIPE_FORMAT_LATC1_SNORM:
 896                         word4 |= sign_bit[0];
 897                 case PIPE_FORMAT_RGTC1_UNORM:
 898                 case PIPE_FORMAT_LATC1_UNORM:
 899                         result = FMT_BC4;
 900                         goto out_word4;
 901                 case PIPE_FORMAT_RGTC2_SNORM:
 902                 case PIPE_FORMAT_LATC2_SNORM:
 903                         word4 |= sign_bit[0] | sign_bit[1];
 904                 case PIPE_FORMAT_RGTC2_UNORM:
 905                 case PIPE_FORMAT_LATC2_UNORM:
 906                         result = FMT_BC5;
 907                         goto out_word4;
 908                 default:
 909                         goto out_unknown;
 910                 }
 911         }
 912
 913         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 914
 915                 if (!r600_enable_s3tc)
 916                         goto out_unknown;
 917
 918                 if (!util_format_s3tc_enabled) {
 919                         goto out_unknown;
 920                 }
 921
 922                 switch (format) {
 923                 case PIPE_FORMAT_DXT1_RGB:
 924                 case PIPE_FORMAT_DXT1_RGBA:
 925                 case PIPE_FORMAT_DXT1_SRGB:
 926                 case PIPE_FORMAT_DXT1_SRGBA:
 927                         result = FMT_BC1;
 928                         goto out_word4;
 929                 case PIPE_FORMAT_DXT3_RGBA:
 930                 case PIPE_FORMAT_DXT3_SRGBA:
 931                         result = FMT_BC2;
 932                         goto out_word4;
 933                 case PIPE_FORMAT_DXT5_RGBA:
 934                 case PIPE_FORMAT_DXT5_SRGBA:
 935                         result = FMT_BC3;
 936                         goto out_word4;
 937                 default:
 938                         goto out_unknown;
 939                 }
 940         }
 941
 942         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 943                 result = FMT_5_9_9_9_SHAREDEXP;
 944                 goto out_word4;
 945         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 946                 result = FMT_10_11_11_FLOAT;
 947                 goto out_word4;
 948         }
 949
 950
 951         for (i = 0; i < desc->nr_channels; i++) {
 952                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 953                         word4 |= sign_bit[i];
 954                 }
 955         }
 956
 957         /* R8G8Bx_SNORM - TODO CxV8U8 */
 958
 959         /* See whether the components are of the same size. */
 960         for (i = 1; i < desc->nr_channels; i++) {
 961                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 962         }
 963
 964         /* Non-uniform formats. */
 965         if (!uniform) {
 966                 switch(desc->nr_channels) {
 967                 case 3:
 968                         if (desc->channel[0].size == 5 &&
 969                             desc->channel[1].size == 6 &&
 970                             desc->channel[2].size == 5) {
 971                                 result = FMT_5_6_5;
 972                                 goto out_word4;
 973                         }
 974                         goto out_unknown;
 975                 case 4:
 976                         if (desc->channel[0].size == 5 &&
 977                             desc->channel[1].size == 5 &&
 978                             desc->channel[2].size == 5 &&
 979                             desc->channel[3].size == 1) {
 980                                 result = FMT_1_5_5_5;
 981                                 goto out_word4;
 982                         }
 983                         if (desc->channel[0].size == 10 &&
 984                             desc->channel[1].size == 10 &&
 985                             desc->channel[2].size == 10 &&
 986                             desc->channel[3].size == 2) {
 987                                 result = FMT_2_10_10_10;
 988                                 goto out_word4;
 989                         }
 990                         goto out_unknown;
 991                 }
 992                 goto out_unknown;
 993         }
 994
 995         /* Find the first non-VOID channel. */
 996         for (i = 0; i < 4; i++) {
 997                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
 998                         break;
 999                 }
1000         }
1001
1002         if (i == 4)
1003                 goto out_unknown;
1004
1005         /* uniform formats */
1006         switch (desc->channel[i].type) {
1007         case UTIL_FORMAT_TYPE_UNSIGNED:
1008         case UTIL_FORMAT_TYPE_SIGNED:
1009                 if (!desc->channel[i].normalized &&
1010                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1011                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_SCALED);
1012                 }
1013
1014                 switch (desc->channel[i].size) {
1015                 case 4:
1016                         switch (desc->nr_channels) {
1017                         case 2:
1018                                 result = FMT_4_4;
1019                                 goto out_word4;
1020                         case 4:
1021                                 result = FMT_4_4_4_4;
1022                                 goto out_word4;
1023                         }
1024                         goto out_unknown;
1025                 case 8:
1026                         switch (desc->nr_channels) {
1027                         case 1:
1028                                 result = FMT_8;
1029                                 goto out_word4;
1030                         case 2:
1031                                 result = FMT_8_8;
1032                                 goto out_word4;
1033                         case 4:
1034                                 result = FMT_8_8_8_8;
1035                                 goto out_word4;
1036                         }
1037                         goto out_unknown;
1038                 case 16:
1039                         switch (desc->nr_channels) {
1040                         case 1:
1041                                 result = FMT_16;
1042                                 goto out_word4;
1043                         case 2:
1044                                 result = FMT_16_16;
1045                                 goto out_word4;
1046                         case 4:
1047                                 result = FMT_16_16_16_16;
1048                                 goto out_word4;
1049                         }
1050                         goto out_unknown;
1051                 case 32:
1052                         switch (desc->nr_channels) {
1053                         case 1:
1054                                 result = FMT_32;
1055                                 goto out_word4;
1056                         case 2:
1057                                 result = FMT_32_32;
1058                                 goto out_word4;
1059                         case 4:
1060                                 result = FMT_32_32_32_32;
1061                                 goto out_word4;
1062                         }
1063                 }
1064                 goto out_unknown;
1065
1066         case UTIL_FORMAT_TYPE_FLOAT:
1067                 switch (desc->channel[i].size) {
1068                 case 16:
1069                         switch (desc->nr_channels) {
1070                         case 1:
1071                                 result = FMT_16_FLOAT;
1072                                 goto out_word4;
1073                         case 2:
1074                                 result = FMT_16_16_FLOAT;
1075                                 goto out_word4;
1076                         case 4:
1077                                 result = FMT_16_16_16_16_FLOAT;
1078                                 goto out_word4;
1079                         }
1080                         goto out_unknown;
1081                 case 32:
1082                         switch (desc->nr_channels) {
1083                         case 1:
1084                                 result = FMT_32_FLOAT;
1085                                 goto out_word4;
1086                         case 2:
1087                                 result = FMT_32_32_FLOAT;
1088                                 goto out_word4;
1089                         case 4:
1090                                 result = FMT_32_32_32_32_FLOAT;
1091                                 goto out_word4;
1092                         }
1093                 }
1094
1095         }
1096 out_word4:
1097         if (word4_p)
1098                 *word4_p = word4;
1099         if (yuv_format_p)
1100                 *yuv_format_p = yuv_format;
1101         return result;
1102 out_unknown:
1103         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1104         return ~0;
1105 }