src/gallium/drivers/r600/r600_texture.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  *      Corbin Simpson
  26  */
  27 #include <errno.h>
  28 #include <pipe/p_screen.h>
  29 #include <util/u_format.h>
  30 #include <util/u_format_s3tc.h>
  31 #include <util/u_math.h>
  32 #include <util/u_inlines.h>
  33 #include <util/u_memory.h>
  34 #include "state_tracker/drm_driver.h"
  35 #include "pipebuffer/pb_buffer.h"
  36 #include "r600_pipe.h"
  37 #include "r600_resource.h"
  38 #include "r600_state_inlines.h"
  39 #include "r600d.h"
  40 #include "r600_formats.h"
  41
  42 /* Copy from a full GPU texture to a transfer's staging one. */
  43 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  44 {
  45         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  46         struct pipe_resource *texture = transfer->resource;
  47
  48         ctx->resource_copy_region(ctx, rtransfer->staging_texture,
  49                                 0, 0, 0, 0, texture, transfer->level,
  50                                 &transfer->box);
  51 }
  52
  53
  54 /* Copy from a transfer's staging texture to a full GPU one. */
  55 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
  56 {
  57         struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
  58         struct pipe_resource *texture = transfer->resource;
  59         struct pipe_box sbox;
  60
  61         sbox.x = sbox.y = sbox.z = 0;
  62         sbox.width = transfer->box.width;
  63         sbox.height = transfer->box.height;
  64         /* XXX that might be wrong */
  65         sbox.depth = 1;
  66         ctx->resource_copy_region(ctx, texture, transfer->level,
  67                                   transfer->box.x, transfer->box.y, transfer->box.z,
  68                                   rtransfer->staging_texture,
  69                                   0, &sbox);
  70
  71         ctx->flush(ctx, NULL);
  72 }
  73
  74 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
  75                                         unsigned level, unsigned layer)
  76 {
  77         unsigned offset = rtex->offset[level];
  78
  79         switch (rtex->resource.b.b.b.target) {
  80         case PIPE_TEXTURE_3D:
  81         case PIPE_TEXTURE_CUBE:
  82         default:
  83                 return offset + layer * rtex->layer_size[level];
  84         }
  85 }
  86
  87 static unsigned r600_get_block_alignment(struct pipe_screen *screen,
  88                                          enum pipe_format format,
  89                                          unsigned array_mode)
  90 {
  91         struct r600_screen* rscreen = (struct r600_screen *)screen;
  92         unsigned pixsize = util_format_get_blocksize(format);
  93         int p_align;
  94
  95         switch(array_mode) {
  96         case V_038000_ARRAY_1D_TILED_THIN1:
  97                 p_align = MAX2(8,
  98                                ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
  99                 break;
 100         case V_038000_ARRAY_2D_TILED_THIN1:
 101                 p_align = MAX2(rscreen->tiling_info->num_banks,
 102                                (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
 103                                 rscreen->tiling_info->num_banks)) * 8;
 104                 break;
 105         case V_038000_ARRAY_LINEAR_ALIGNED:
 106                 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize);
 107                 break;
 108         case V_038000_ARRAY_LINEAR_GENERAL:
 109         default:
 110                 p_align = rscreen->tiling_info->group_bytes / pixsize;
 111                 break;
 112         }
 113         return p_align;
 114 }
 115
 116 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 117                                           unsigned array_mode)
 118 {
 119         struct r600_screen* rscreen = (struct r600_screen *)screen;
 120         int h_align;
 121
 122         switch (array_mode) {
 123         case V_038000_ARRAY_2D_TILED_THIN1:
 124                 h_align = rscreen->tiling_info->num_channels * 8;
 125                 break;
 126         case V_038000_ARRAY_1D_TILED_THIN1:
 127         case V_038000_ARRAY_LINEAR_ALIGNED:
 128                 h_align = 8;
 129                 break;
 130         case V_038000_ARRAY_LINEAR_GENERAL:
 131         default:
 132                 h_align = 1;
 133                 break;
 134         }
 135         return h_align;
 136 }
 137
 138 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 139                                         enum pipe_format format,
 140                                         unsigned array_mode)
 141 {
 142         struct r600_screen* rscreen = (struct r600_screen *)screen;
 143         unsigned pixsize = util_format_get_blocksize(format);
 144         int p_align = r600_get_block_alignment(screen, format, array_mode);
 145         int h_align = r600_get_height_alignment(screen, array_mode);
 146         int b_align;
 147
 148         switch (array_mode) {
 149         case V_038000_ARRAY_2D_TILED_THIN1:
 150                 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
 151                                p_align * pixsize * h_align);
 152                 break;
 153         case V_038000_ARRAY_1D_TILED_THIN1:
 154         case V_038000_ARRAY_LINEAR_ALIGNED:
 155         case V_038000_ARRAY_LINEAR_GENERAL:
 156         default:
 157                 b_align = rscreen->tiling_info->group_bytes;
 158                 break;
 159         }
 160         return b_align;
 161 }
 162
 163 static unsigned mip_minify(unsigned size, unsigned level)
 164 {
 165         unsigned val;
 166         val = u_minify(size, level);
 167         if (level > 0)
 168                 val = util_next_power_of_two(val);
 169         return val;
 170 }
 171
 172 static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
 173                                           struct r600_resource_texture *rtex,
 174                                           unsigned level)
 175 {
 176         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 177         unsigned nblocksx, block_align, width;
 178         unsigned blocksize = util_format_get_blocksize(ptex->format);
 179
 180         if (rtex->pitch_override)
 181                 return rtex->pitch_override / blocksize;
 182
 183         width = mip_minify(ptex->width0, level);
 184         nblocksx = util_format_get_nblocksx(ptex->format, width);
 185
 186         block_align = r600_get_block_alignment(screen, ptex->format,
 187                                               rtex->array_mode[level]);
 188         nblocksx = align(nblocksx, block_align);
 189         return nblocksx;
 190 }
 191
 192 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
 193                                           struct r600_resource_texture *rtex,
 194                                           unsigned level)
 195 {
 196         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 197         unsigned height, tile_height;
 198
 199         height = mip_minify(ptex->height0, level);
 200         height = util_format_get_nblocksy(ptex->format, height);
 201         tile_height = r600_get_height_alignment(screen,
 202                                                 rtex->array_mode[level]);
 203         height = align(height, tile_height);
 204         return height;
 205 }
 206
 207 static void r600_texture_set_array_mode(struct pipe_screen *screen,
 208                                         struct r600_resource_texture *rtex,
 209                                         unsigned level, unsigned array_mode)
 210 {
 211         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 212
 213         switch (array_mode) {
 214         case V_0280A0_ARRAY_LINEAR_GENERAL:
 215         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 216         case V_0280A0_ARRAY_1D_TILED_THIN1:
 217         default:
 218                 rtex->array_mode[level] = array_mode;
 219                 break;
 220         case V_0280A0_ARRAY_2D_TILED_THIN1:
 221         {
 222                 unsigned w, h, tile_height, tile_width;
 223
 224                 tile_height = r600_get_height_alignment(screen, array_mode);
 225                 tile_width = r600_get_block_alignment(screen, ptex->format, array_mode);
 226
 227                 w = mip_minify(ptex->width0, level);
 228                 h = mip_minify(ptex->height0, level);
 229                 if (w <= tile_width || h <= tile_height)
 230                         rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
 231                 else
 232                         rtex->array_mode[level] = array_mode;
 233         }
 234         break;
 235         }
 236 }
 237
 238 static void r600_setup_miptree(struct pipe_screen *screen,
 239                                struct r600_resource_texture *rtex,
 240                                unsigned array_mode)
 241 {
 242         struct pipe_resource *ptex = &rtex->resource.b.b.b;
 243         struct radeon *radeon = (struct radeon *)screen->winsys;
 244         enum chip_class chipc = r600_get_family_class(radeon);
 245         unsigned size, layer_size, i, offset;
 246         unsigned nblocksx, nblocksy, extra_size = 0;
 247
 248         for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 249                 unsigned blocksize = util_format_get_blocksize(ptex->format);
 250                 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 251
 252                 r600_texture_set_array_mode(screen, rtex, i, array_mode);
 253
 254                 nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 255                 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 256
 257                 layer_size = nblocksx * nblocksy * blocksize;
 258                 if (ptex->target == PIPE_TEXTURE_CUBE) {
 259                         if (chipc >= R700)
 260                                 size = layer_size * 8;
 261                         else
 262                                 size = layer_size * 6;
 263                 }
 264                 else if (ptex->target == PIPE_TEXTURE_3D)
 265                         size = layer_size * u_minify(ptex->depth0, i);
 266                 else
 267                         size = layer_size * ptex->array_size;
 268
 269                 /* evergreen stores depth and stencil separately */
 270                 if ((chipc >= EVERGREEN) && util_format_is_depth_or_stencil(ptex->format))
 271                         extra_size = align(extra_size + (nblocksx * nblocksy * 1), base_align);
 272
 273                 /* align base image and start of miptree */
 274                 if ((i == 0) || (i == 1))
 275                         offset = align(offset, base_align);
 276                 rtex->offset[i] = offset;
 277                 rtex->layer_size[i] = layer_size;
 278                 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
 279                 rtex->pitch_in_bytes[i] = nblocksx * blocksize;
 280
 281                 offset += size;
 282         }
 283         rtex->size = offset + extra_size;
 284 }
 285
 286 /* Figure out whether u_blitter will fallback to a transfer operation.
 287  * If so, don't use a staging resource.
 288  */
 289 static boolean permit_hardware_blit(struct pipe_screen *screen,
 290                                         const struct pipe_resource *res)
 291 {
 292         unsigned bind;
 293
 294         if (util_format_is_depth_or_stencil(res->format))
 295                 bind = PIPE_BIND_DEPTH_STENCIL;
 296         else
 297                 bind = PIPE_BIND_RENDER_TARGET;
 298
 299         /* hackaround for S3TC */
 300         if (util_format_is_compressed(res->format))
 301                 return TRUE;
 302
 303         if (!screen->is_format_supported(screen,
 304                                 res->format,
 305                                 res->target,
 306                                 res->nr_samples,
 307                                 bind))
 308                 return FALSE;
 309
 310         if (!screen->is_format_supported(screen,
 311                                 res->format,
 312                                 res->target,
 313                                 res->nr_samples,
 314                                 PIPE_BIND_SAMPLER_VIEW))
 315                 return FALSE;
 316
 317         switch (res->usage) {
 318         case PIPE_USAGE_STREAM:
 319         case PIPE_USAGE_STAGING:
 320         case PIPE_USAGE_STATIC:
 321         case PIPE_USAGE_IMMUTABLE:
 322                 return FALSE;
 323
 324         default:
 325                 return TRUE;
 326         }
 327 }
 328
 329 static boolean r600_texture_get_handle(struct pipe_screen* screen,
 330                                         struct pipe_resource *ptex,
 331                                         struct winsys_handle *whandle)
 332 {
 333         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 334         struct r600_resource *resource = &rtex->resource;
 335         struct radeon *radeon = (struct radeon *)screen->winsys;
 336
 337         return r600_bo_get_winsys_handle(radeon, resource->bo,
 338                         rtex->pitch_in_bytes[0], whandle);
 339 }
 340
 341 static void r600_texture_destroy(struct pipe_screen *screen,
 342                                  struct pipe_resource *ptex)
 343 {
 344         struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 345         struct r600_resource *resource = &rtex->resource;
 346         struct radeon *radeon = (struct radeon *)screen->winsys;
 347
 348         if (rtex->flushed_depth_texture)
 349                 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
 350
 351         if (resource->bo) {
 352                 r600_bo_reference(radeon, &resource->bo, NULL);
 353         }
 354         FREE(rtex);
 355 }
 356
 357 static const struct u_resource_vtbl r600_texture_vtbl =
 358 {
 359         r600_texture_get_handle,        /* get_handle */
 360         r600_texture_destroy,           /* resource_destroy */
 361         r600_texture_get_transfer,      /* get_transfer */
 362         r600_texture_transfer_destroy,  /* transfer_destroy */
 363         r600_texture_transfer_map,      /* transfer_map */
 364         u_default_transfer_flush_region,/* transfer_flush_region */
 365         r600_texture_transfer_unmap,    /* transfer_unmap */
 366         u_default_transfer_inline_write /* transfer_inline_write */
 367 };
 368
 369 static struct r600_resource_texture *
 370 r600_texture_create_object(struct pipe_screen *screen,
 371                            const struct pipe_resource *base,
 372                            unsigned array_mode,
 373                            unsigned pitch_in_bytes_override,
 374                            unsigned max_buffer_size,
 375                            struct r600_bo *bo)
 376 {
 377         struct r600_resource_texture *rtex;
 378         struct r600_resource *resource;
 379         struct radeon *radeon = (struct radeon *)screen->winsys;
 380
 381         rtex = CALLOC_STRUCT(r600_resource_texture);
 382         if (rtex == NULL)
 383                 return NULL;
 384
 385         resource = &rtex->resource;
 386         resource->b.b.b = *base;
 387         resource->b.b.vtbl = &r600_texture_vtbl;
 388         pipe_reference_init(&resource->b.b.b.reference, 1);
 389         resource->b.b.b.screen = screen;
 390         resource->bo = bo;
 391         rtex->pitch_override = pitch_in_bytes_override;
 392         /* only mark depth textures the HW can hit as depth textures */
 393         if (util_format_is_depth_or_stencil(base->format) && permit_hardware_blit(screen, base))
 394                 rtex->depth = 1;
 395
 396         r600_setup_miptree(screen, rtex, array_mode);
 397
 398         resource->size = rtex->size;
 399
 400         if (!resource->bo) {
 401                 struct pipe_resource *ptex = &rtex->resource.b.b.b;
 402                 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 403
 404                 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
 405                 if (!resource->bo) {
 406                         FREE(rtex);
 407                         return NULL;
 408                 }
 409         }
 410         return rtex;
 411 }
 412
 413 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 414                                                 const struct pipe_resource *templ)
 415 {
 416         unsigned array_mode = 0;
 417         static int force_tiling = -1;
 418
 419         /* Would like some magic "get_bool_option_once" routine.
 420          */
 421         if (force_tiling == -1) {
 422 #if 0
 423                 /* reenable when 2D tiling is fixed better */
 424                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 425                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 426                         force_tiling = debug_get_bool_option("R600_TILING", TRUE);
 427 #endif
 428                 force_tiling = debug_get_bool_option("R600_TILING", FALSE);
 429         }
 430
 431         if (force_tiling && permit_hardware_blit(screen, templ)) {
 432                 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 433                     !(templ->bind & PIPE_BIND_SCANOUT)) {
 434                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 435                 }
 436         }
 437
 438         if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 439             util_format_is_compressed(templ->format))
 440                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 441
 442         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 443                                                                   0, 0, NULL);
 444
 445 }
 446
 447 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
 448                                                 struct pipe_resource *texture,
 449                                                 const struct pipe_surface *surf_tmpl)
 450 {
 451         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 452         struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
 453         unsigned level = surf_tmpl->u.tex.level;
 454
 455         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 456         if (surface == NULL)
 457                 return NULL;
 458         /* XXX no offset */
 459 /*      offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
 460         pipe_reference_init(&surface->base.reference, 1);
 461         pipe_resource_reference(&surface->base.texture, texture);
 462         surface->base.context = pipe;
 463         surface->base.format = surf_tmpl->format;
 464         surface->base.width = mip_minify(texture->width0, level);
 465         surface->base.height = mip_minify(texture->height0, level);
 466         surface->base.usage = surf_tmpl->usage;
 467         surface->base.texture = texture;
 468         surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 469         surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 470         surface->base.u.tex.level = level;
 471
 472         surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
 473                                                             rtex, level);
 474         return &surface->base;
 475 }
 476
 477 static void r600_surface_destroy(struct pipe_context *pipe,
 478                                  struct pipe_surface *surface)
 479 {
 480         pipe_resource_reference(&surface->texture, NULL);
 481         FREE(surface);
 482 }
 483
 484
 485 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 486                                                const struct pipe_resource *templ,
 487                                                struct winsys_handle *whandle)
 488 {
 489         struct radeon *rw = (struct radeon*)screen->winsys;
 490         struct r600_bo *bo = NULL;
 491         unsigned array_mode = 0;
 492
 493         /* Support only 2D textures without mipmaps */
 494         if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 495               templ->depth0 != 1 || templ->last_level != 0)
 496                 return NULL;
 497
 498         bo = r600_bo_handle(rw, whandle->handle, &array_mode);
 499         if (bo == NULL) {
 500                 return NULL;
 501         }
 502
 503         return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
 504                                                                   whandle->stride,
 505                                                                   0,
 506                                                                   bo);
 507 }
 508
 509 int r600_texture_depth_flush(struct pipe_context *ctx,
 510                              struct pipe_resource *texture, boolean just_create)
 511 {
 512         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 513         struct pipe_resource resource;
 514
 515         if (rtex->flushed_depth_texture)
 516                 goto out;
 517
 518         resource.target = PIPE_TEXTURE_2D;
 519         resource.format = texture->format;
 520         resource.width0 = texture->width0;
 521         resource.height0 = texture->height0;
 522         resource.depth0 = 1;
 523         resource.array_size = 1;
 524         resource.last_level = texture->last_level;
 525         resource.nr_samples = 0;
 526         resource.usage = PIPE_USAGE_DYNAMIC;
 527         resource.bind = 0;
 528         resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 529
 530         resource.bind |= PIPE_BIND_DEPTH_STENCIL;
 531
 532         rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
 533         if (rtex->flushed_depth_texture == NULL) {
 534                 R600_ERR("failed to create temporary texture to hold untiled copy\n");
 535                 return -ENOMEM;
 536         }
 537
 538         ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
 539 out:
 540         if (just_create)
 541                 return 0;
 542
 543         /* XXX: only do this if the depth texture has actually changed:
 544          */
 545         r600_blit_uncompress_depth(ctx, rtex);
 546         return 0;
 547 }
 548
 549 /* Needs adjustment for pixelformat:
 550  */
 551 static INLINE unsigned u_box_volume( const struct pipe_box *box )
 552 {
 553         return box->width * box->depth * box->height;
 554 };
 555
 556 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 557                                                 struct pipe_resource *texture,
 558                                                 unsigned level,
 559                                                 unsigned usage,
 560                                                 const struct pipe_box *box)
 561 {
 562         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 563         struct pipe_resource resource;
 564         struct r600_transfer *trans;
 565         int r;
 566         boolean use_staging_texture = FALSE;
 567
 568         /* We cannot map a tiled texture directly because the data is
 569          * in a different order, therefore we do detiling using a blit.
 570          *
 571          * Also, use a temporary in GTT memory for read transfers, as
 572          * the CPU is much happier reading out of cached system memory
 573          * than uncached VRAM.
 574          */
 575         if (R600_TEX_IS_TILED(rtex, level))
 576                 use_staging_texture = TRUE;
 577
 578         if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 579                 use_staging_texture = TRUE;
 580
 581         /* XXX: Use a staging texture for uploads if the underlying BO
 582          * is busy.  No interface for checking that currently? so do
 583          * it eagerly whenever the transfer doesn't require a readback
 584          * and might block.
 585          */
 586         if ((usage & PIPE_TRANSFER_WRITE) &&
 587                         !(usage & (PIPE_TRANSFER_READ |
 588                                         PIPE_TRANSFER_DONTBLOCK |
 589                                         PIPE_TRANSFER_UNSYNCHRONIZED)))
 590                 use_staging_texture = TRUE;
 591
 592         if (!permit_hardware_blit(ctx->screen, texture) ||
 593                 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
 594                 use_staging_texture = FALSE;
 595
 596         trans = CALLOC_STRUCT(r600_transfer);
 597         if (trans == NULL)
 598                 return NULL;
 599         pipe_resource_reference(&trans->transfer.resource, texture);
 600         trans->transfer.level = level;
 601         trans->transfer.usage = usage;
 602         trans->transfer.box = *box;
 603         if (rtex->depth) {
 604                 /* XXX: only readback the rectangle which is being mapped?
 605                 */
 606                 /* XXX: when discard is true, no need to read back from depth texture
 607                 */
 608                 r = r600_texture_depth_flush(ctx, texture, FALSE);
 609                 if (r < 0) {
 610                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 611                         pipe_resource_reference(&trans->transfer.resource, NULL);
 612                         FREE(trans);
 613                         return NULL;
 614                 }
 615                 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
 616                 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
 617                 return &trans->transfer;
 618         } else if (use_staging_texture) {
 619                 resource.target = PIPE_TEXTURE_2D;
 620                 resource.format = texture->format;
 621                 resource.width0 = box->width;
 622                 resource.height0 = box->height;
 623                 resource.depth0 = 1;
 624                 resource.array_size = 1;
 625                 resource.last_level = 0;
 626                 resource.nr_samples = 0;
 627                 resource.usage = PIPE_USAGE_STAGING;
 628                 resource.bind = 0;
 629                 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
 630                 /* For texture reading, the temporary (detiled) texture is used as
 631                  * a render target when blitting from a tiled texture. */
 632                 if (usage & PIPE_TRANSFER_READ) {
 633                         resource.bind |= PIPE_BIND_RENDER_TARGET;
 634                 }
 635                 /* For texture writing, the temporary texture is used as a sampler
 636                  * when blitting into a tiled texture. */
 637                 if (usage & PIPE_TRANSFER_WRITE) {
 638                         resource.bind |= PIPE_BIND_SAMPLER_VIEW;
 639                 }
 640                 /* Create the temporary texture. */
 641                 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
 642                 if (trans->staging_texture == NULL) {
 643                         R600_ERR("failed to create temporary texture to hold untiled copy\n");
 644                         pipe_resource_reference(&trans->transfer.resource, NULL);
 645                         FREE(trans);
 646                         return NULL;
 647                 }
 648
 649                 trans->transfer.stride =
 650                         ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
 651                 if (usage & PIPE_TRANSFER_READ) {
 652                         r600_copy_to_staging_texture(ctx, trans);
 653                         /* Always referenced in the blit. */
 654                         ctx->flush(ctx, NULL);
 655                 }
 656                 return &trans->transfer;
 657         }
 658         trans->transfer.stride = rtex->pitch_in_bytes[level];
 659         trans->transfer.layer_stride = rtex->layer_size[level];
 660         trans->offset = r600_texture_get_offset(rtex, level, box->z);
 661         return &trans->transfer;
 662 }
 663
 664 void r600_texture_transfer_destroy(struct pipe_context *ctx,
 665                                    struct pipe_transfer *transfer)
 666 {
 667         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 668         struct pipe_resource *texture = transfer->resource;
 669         struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 670
 671         if (rtransfer->staging_texture) {
 672                 if (transfer->usage & PIPE_TRANSFER_WRITE) {
 673                         r600_copy_from_staging_texture(ctx, rtransfer);
 674                 }
 675                 pipe_resource_reference(&rtransfer->staging_texture, NULL);
 676         }
 677
 678         if (rtex->depth && !rtex->is_flushing_texture) {
 679                 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
 680                         r600_blit_push_depth(ctx, rtex);
 681         }
 682
 683         pipe_resource_reference(&transfer->resource, NULL);
 684         FREE(transfer);
 685 }
 686
 687 void* r600_texture_transfer_map(struct pipe_context *ctx,
 688                                 struct pipe_transfer* transfer)
 689 {
 690         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 691         struct r600_bo *bo;
 692         enum pipe_format format = transfer->resource->format;
 693         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 694         unsigned offset = 0;
 695         unsigned usage = 0;
 696         char *map;
 697
 698         if (rtransfer->staging_texture) {
 699                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 700         } else {
 701                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 702
 703                 if (rtex->flushed_depth_texture)
 704                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 705                 else
 706                         bo = ((struct r600_resource *)transfer->resource)->bo;
 707
 708                 offset = rtransfer->offset +
 709                         transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 710                         transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 711         }
 712
 713         if (transfer->usage & PIPE_TRANSFER_WRITE) {
 714                 usage |= PB_USAGE_CPU_WRITE;
 715
 716                 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
 717                 }
 718
 719                 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
 720                 }
 721         }
 722
 723         if (transfer->usage & PIPE_TRANSFER_READ) {
 724                 usage |= PB_USAGE_CPU_READ;
 725         }
 726
 727         if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
 728                 usage |= PB_USAGE_DONTBLOCK;
 729         }
 730
 731         if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
 732                 usage |= PB_USAGE_UNSYNCHRONIZED;
 733         }
 734
 735         map = r600_bo_map(radeon, bo, usage, ctx);
 736         if (!map) {
 737                 return NULL;
 738         }
 739
 740         return map + offset;
 741 }
 742
 743 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 744                                  struct pipe_transfer* transfer)
 745 {
 746         struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 747         struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
 748         struct r600_bo *bo;
 749
 750         if (rtransfer->staging_texture) {
 751                 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
 752         } else {
 753                 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 754
 755                 if (rtex->flushed_depth_texture) {
 756                         bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 757                 } else {
 758                         bo = ((struct r600_resource *)transfer->resource)->bo;
 759                 }
 760         }
 761         r600_bo_unmap(radeon, bo);
 762 }
 763
 764 void r600_init_surface_functions(struct r600_pipe_context *r600)
 765 {
 766         r600->context.create_surface = r600_create_surface;
 767         r600->context.surface_destroy = r600_surface_destroy;
 768 }
 769
 770 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
 771                 const unsigned char *swizzle_view)
 772 {
 773         unsigned i;
 774         unsigned char swizzle[4];
 775         unsigned result = 0;
 776         const uint32_t swizzle_shift[4] = {
 777                 16, 19, 22, 25,
 778         };
 779         const uint32_t swizzle_bit[4] = {
 780                 0, 1, 2, 3,
 781         };
 782
 783         if (swizzle_view) {
 784                 /* Combine two sets of swizzles. */
 785                 for (i = 0; i < 4; i++) {
 786                         swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
 787                                 swizzle_format[swizzle_view[i]] : swizzle_view[i];
 788                 }
 789         } else {
 790                 memcpy(swizzle, swizzle_format, 4);
 791         }
 792
 793         /* Get swizzle. */
 794         for (i = 0; i < 4; i++) {
 795                 switch (swizzle[i]) {
 796                 case UTIL_FORMAT_SWIZZLE_Y:
 797                         result |= swizzle_bit[1] << swizzle_shift[i];
 798                         break;
 799                 case UTIL_FORMAT_SWIZZLE_Z:
 800                         result |= swizzle_bit[2] << swizzle_shift[i];
 801                         break;
 802                 case UTIL_FORMAT_SWIZZLE_W:
 803                         result |= swizzle_bit[3] << swizzle_shift[i];
 804                         break;
 805                 case UTIL_FORMAT_SWIZZLE_0:
 806                         result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
 807                         break;
 808                 case UTIL_FORMAT_SWIZZLE_1:
 809                         result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
 810                         break;
 811                 default: /* UTIL_FORMAT_SWIZZLE_X */
 812                         result |= swizzle_bit[0] << swizzle_shift[i];
 813                 }
 814         }
 815         return result;
 816 }
 817
 818 /* texture format translate */
 819 uint32_t r600_translate_texformat(struct pipe_screen *screen,
 820                                   enum pipe_format format,
 821                                   const unsigned char *swizzle_view,
 822                                   uint32_t *word4_p, uint32_t *yuv_format_p)
 823 {
 824         uint32_t result = 0, word4 = 0, yuv_format = 0;
 825         const struct util_format_description *desc;
 826         boolean uniform = TRUE;
 827         static int r600_enable_s3tc = -1;
 828
 829         int i;
 830         const uint32_t sign_bit[4] = {
 831                 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
 832                 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
 833                 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
 834                 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
 835         };
 836         desc = util_format_description(format);
 837
 838         word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
 839
 840         /* Colorspace (return non-RGB formats directly). */
 841         switch (desc->colorspace) {
 842                 /* Depth stencil formats */
 843         case UTIL_FORMAT_COLORSPACE_ZS:
 844                 switch (format) {
 845                 case PIPE_FORMAT_Z16_UNORM:
 846                         result = FMT_16;
 847                         goto out_word4;
 848                 case PIPE_FORMAT_X24S8_USCALED:
 849                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 850                 case PIPE_FORMAT_Z24X8_UNORM:
 851                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 852                         result = FMT_8_24;
 853                         goto out_word4;
 854                 case PIPE_FORMAT_S8X24_USCALED:
 855                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 856                 case PIPE_FORMAT_X8Z24_UNORM:
 857                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 858                         result = FMT_24_8;
 859                         goto out_word4;
 860                 case PIPE_FORMAT_S8_USCALED:
 861                         result = FMT_8;
 862                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 863                         goto out_word4;
 864                 default:
 865                         goto out_unknown;
 866                 }
 867
 868         case UTIL_FORMAT_COLORSPACE_YUV:
 869                 yuv_format |= (1 << 30);
 870                 switch (format) {
 871                 case PIPE_FORMAT_UYVY:
 872                 case PIPE_FORMAT_YUYV:
 873                 default:
 874                         break;
 875                 }
 876                 goto out_unknown; /* TODO */
 877
 878         case UTIL_FORMAT_COLORSPACE_SRGB:
 879                 word4 |= S_038010_FORCE_DEGAMMA(1);
 880                 break;
 881
 882         default:
 883                 break;
 884         }
 885
 886         if (r600_enable_s3tc == -1) {
 887                 struct r600_screen *rscreen = (struct r600_screen *)screen;
 888                 if (r600_get_minor_version(rscreen->radeon) >= 9)
 889                         r600_enable_s3tc = 1;
 890                 else
 891                         r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
 892         }
 893
 894         if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
 895                 if (!r600_enable_s3tc)
 896                         goto out_unknown;
 897
 898                 switch (format) {
 899                 case PIPE_FORMAT_RGTC1_SNORM:
 900                 case PIPE_FORMAT_LATC1_SNORM:
 901                         word4 |= sign_bit[0];
 902                 case PIPE_FORMAT_RGTC1_UNORM:
 903                 case PIPE_FORMAT_LATC1_UNORM:
 904                         result = FMT_BC4;
 905                         goto out_word4;
 906                 case PIPE_FORMAT_RGTC2_SNORM:
 907                 case PIPE_FORMAT_LATC2_SNORM:
 908                         word4 |= sign_bit[0] | sign_bit[1];
 909                 case PIPE_FORMAT_RGTC2_UNORM:
 910                 case PIPE_FORMAT_LATC2_UNORM:
 911                         result = FMT_BC5;
 912                         goto out_word4;
 913                 default:
 914                         goto out_unknown;
 915                 }
 916         }
 917
 918         if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 919
 920                 if (!r600_enable_s3tc)
 921                         goto out_unknown;
 922
 923                 if (!util_format_s3tc_enabled) {
 924                         goto out_unknown;
 925                 }
 926
 927                 switch (format) {
 928                 case PIPE_FORMAT_DXT1_RGB:
 929                 case PIPE_FORMAT_DXT1_RGBA:
 930                 case PIPE_FORMAT_DXT1_SRGB:
 931                 case PIPE_FORMAT_DXT1_SRGBA:
 932                         result = FMT_BC1;
 933                         goto out_word4;
 934                 case PIPE_FORMAT_DXT3_RGBA:
 935                 case PIPE_FORMAT_DXT3_SRGBA:
 936                         result = FMT_BC2;
 937                         goto out_word4;
 938                 case PIPE_FORMAT_DXT5_RGBA:
 939                 case PIPE_FORMAT_DXT5_SRGBA:
 940                         result = FMT_BC3;
 941                         goto out_word4;
 942                 default:
 943                         goto out_unknown;
 944                 }
 945         }
 946
 947         if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
 948                 result = FMT_5_9_9_9_SHAREDEXP;
 949                 goto out_word4;
 950         } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
 951                 result = FMT_10_11_11_FLOAT;
 952                 goto out_word4;
 953         }
 954
 955
 956         for (i = 0; i < desc->nr_channels; i++) {
 957                 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
 958                         word4 |= sign_bit[i];
 959                 }
 960         }
 961
 962         /* R8G8Bx_SNORM - TODO CxV8U8 */
 963
 964         /* See whether the components are of the same size. */
 965         for (i = 1; i < desc->nr_channels; i++) {
 966                 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
 967         }
 968
 969         /* Non-uniform formats. */
 970         if (!uniform) {
 971                 switch(desc->nr_channels) {
 972                 case 3:
 973                         if (desc->channel[0].size == 5 &&
 974                             desc->channel[1].size == 6 &&
 975                             desc->channel[2].size == 5) {
 976                                 result = FMT_5_6_5;
 977                                 goto out_word4;
 978                         }
 979                         goto out_unknown;
 980                 case 4:
 981                         if (desc->channel[0].size == 5 &&
 982                             desc->channel[1].size == 5 &&
 983                             desc->channel[2].size == 5 &&
 984                             desc->channel[3].size == 1) {
 985                                 result = FMT_1_5_5_5;
 986                                 goto out_word4;
 987                         }
 988                         if (desc->channel[0].size == 10 &&
 989                             desc->channel[1].size == 10 &&
 990                             desc->channel[2].size == 10 &&
 991                             desc->channel[3].size == 2) {
 992                                 result = FMT_2_10_10_10;
 993                                 goto out_word4;
 994                         }
 995                         goto out_unknown;
 996                 }
 997                 goto out_unknown;
 998         }
 999
1000         /* Find the first non-VOID channel. */
1001         for (i = 0; i < 4; i++) {
1002                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1003                         break;
1004                 }
1005         }
1006
1007         if (i == 4)
1008                 goto out_unknown;
1009
1010         /* uniform formats */
1011         switch (desc->channel[i].type) {
1012         case UTIL_FORMAT_TYPE_UNSIGNED:
1013         case UTIL_FORMAT_TYPE_SIGNED:
1014                 if (!desc->channel[i].normalized &&
1015                     desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
1016                         word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_SCALED);
1017                 }
1018
1019                 switch (desc->channel[i].size) {
1020                 case 4:
1021                         switch (desc->nr_channels) {
1022                         case 2:
1023                                 result = FMT_4_4;
1024                                 goto out_word4;
1025                         case 4:
1026                                 result = FMT_4_4_4_4;
1027                                 goto out_word4;
1028                         }
1029                         goto out_unknown;
1030                 case 8:
1031                         switch (desc->nr_channels) {
1032                         case 1:
1033                                 result = FMT_8;
1034                                 goto out_word4;
1035                         case 2:
1036                                 result = FMT_8_8;
1037                                 goto out_word4;
1038                         case 4:
1039                                 result = FMT_8_8_8_8;
1040                                 goto out_word4;
1041                         }
1042                         goto out_unknown;
1043                 case 16:
1044                         switch (desc->nr_channels) {
1045                         case 1:
1046                                 result = FMT_16;
1047                                 goto out_word4;
1048                         case 2:
1049                                 result = FMT_16_16;
1050                                 goto out_word4;
1051                         case 4:
1052                                 result = FMT_16_16_16_16;
1053                                 goto out_word4;
1054                         }
1055                         goto out_unknown;
1056                 case 32:
1057                         switch (desc->nr_channels) {
1058                         case 1:
1059                                 result = FMT_32;
1060                                 goto out_word4;
1061                         case 2:
1062                                 result = FMT_32_32;
1063                                 goto out_word4;
1064                         case 4:
1065                                 result = FMT_32_32_32_32;
1066                                 goto out_word4;
1067                         }
1068                 }
1069                 goto out_unknown;
1070
1071         case UTIL_FORMAT_TYPE_FLOAT:
1072                 switch (desc->channel[i].size) {
1073                 case 16:
1074                         switch (desc->nr_channels) {
1075                         case 1:
1076                                 result = FMT_16_FLOAT;
1077                                 goto out_word4;
1078                         case 2:
1079                                 result = FMT_16_16_FLOAT;
1080                                 goto out_word4;
1081                         case 4:
1082                                 result = FMT_16_16_16_16_FLOAT;
1083                                 goto out_word4;
1084                         }
1085                         goto out_unknown;
1086                 case 32:
1087                         switch (desc->nr_channels) {
1088                         case 1:
1089                                 result = FMT_32_FLOAT;
1090                                 goto out_word4;
1091                         case 2:
1092                                 result = FMT_32_32_FLOAT;
1093                                 goto out_word4;
1094                         case 4:
1095                                 result = FMT_32_32_32_32_FLOAT;
1096                                 goto out_word4;
1097                         }
1098                 }
1099                 goto out_unknown;
1100         }
1101
1102 out_word4:
1103         if (word4_p)
1104                 *word4_p = word4;
1105         if (yuv_format_p)
1106                 *yuv_format_p = yuv_format;
1107         return result;
1108 out_unknown:
1109         /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1110         return ~0;
1111 }