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Merge branch 'lp-offset-twoside'
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include <errno.h>
28 #include <pipe/p_screen.h>
29 #include <util/u_format.h>
30 #include <util/u_math.h>
31 #include <util/u_inlines.h>
32 #include <util/u_memory.h>
33 #include "state_tracker/drm_driver.h"
34 #include "pipebuffer/pb_buffer.h"
35 #include "r600_pipe.h"
36 #include "r600_resource.h"
37 #include "r600_state_inlines.h"
38 #include "r600d.h"
39 #include "r600_formats.h"
40
41 extern struct u_resource_vtbl r600_texture_vtbl;
42
43 /* Copy from a full GPU texture to a transfer's staging one. */
44 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
45 {
46 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
47 struct pipe_resource *texture = transfer->resource;
48 struct pipe_subresource subdst;
49
50 subdst.face = 0;
51 subdst.level = 0;
52 ctx->resource_copy_region(ctx, rtransfer->staging_texture,
53 subdst, 0, 0, 0, texture, transfer->sr,
54 transfer->box.x, transfer->box.y, transfer->box.z,
55 transfer->box.width, transfer->box.height);
56 }
57
58
59 /* Copy from a transfer's staging texture to a full GPU one. */
60 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
61 {
62 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
63 struct pipe_resource *texture = transfer->resource;
64 struct pipe_subresource subsrc;
65
66 subsrc.face = 0;
67 subsrc.level = 0;
68 ctx->resource_copy_region(ctx, texture, transfer->sr,
69 transfer->box.x, transfer->box.y, transfer->box.z,
70 rtransfer->staging_texture, subsrc,
71 0, 0, 0,
72 transfer->box.width, transfer->box.height);
73
74 ctx->flush(ctx, 0, NULL);
75 }
76
77 static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
78 unsigned level, unsigned zslice,
79 unsigned face)
80 {
81 unsigned offset = rtex->offset[level];
82
83 switch (rtex->resource.base.b.target) {
84 case PIPE_TEXTURE_3D:
85 assert(face == 0);
86 return offset + zslice * rtex->layer_size[level];
87 case PIPE_TEXTURE_CUBE:
88 assert(zslice == 0);
89 return offset + face * rtex->layer_size[level];
90 default:
91 assert(zslice == 0 && face == 0);
92 return offset;
93 }
94 }
95
96 static unsigned r600_get_pixel_alignment(struct pipe_screen *screen,
97 enum pipe_format format,
98 unsigned array_mode)
99 {
100 struct r600_screen* rscreen = (struct r600_screen *)screen;
101 unsigned pixsize = util_format_get_blocksize(format);
102 int p_align;
103
104 switch(array_mode) {
105 case V_038000_ARRAY_1D_TILED_THIN1:
106 p_align = MAX2(8,
107 ((rscreen->tiling_info->group_bytes / 8 / pixsize)));
108 break;
109 case V_038000_ARRAY_2D_TILED_THIN1:
110 p_align = MAX2(rscreen->tiling_info->num_banks,
111 (((rscreen->tiling_info->group_bytes / 8 / pixsize)) *
112 rscreen->tiling_info->num_banks)) * 8;
113 break;
114 case V_038000_ARRAY_LINEAR_GENERAL:
115 default:
116 p_align = rscreen->tiling_info->group_bytes / pixsize;
117 break;
118 }
119 return p_align;
120 }
121
122 static unsigned r600_get_height_alignment(struct pipe_screen *screen,
123 unsigned array_mode)
124 {
125 struct r600_screen* rscreen = (struct r600_screen *)screen;
126 int h_align;
127
128 switch (array_mode) {
129 case V_038000_ARRAY_2D_TILED_THIN1:
130 h_align = rscreen->tiling_info->num_channels * 8;
131 break;
132 case V_038000_ARRAY_1D_TILED_THIN1:
133 h_align = 8;
134 break;
135 default:
136 h_align = 1;
137 break;
138 }
139 return h_align;
140 }
141
142 static unsigned r600_get_base_alignment(struct pipe_screen *screen,
143 enum pipe_format format,
144 unsigned array_mode)
145 {
146 struct r600_screen* rscreen = (struct r600_screen *)screen;
147 unsigned pixsize = util_format_get_blocksize(format);
148 int p_align = r600_get_pixel_alignment(screen, format, array_mode);
149 int h_align = r600_get_height_alignment(screen, array_mode);
150 int b_align;
151
152 switch (array_mode) {
153 case V_038000_ARRAY_2D_TILED_THIN1:
154 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize,
155 p_align * pixsize * h_align);
156 break;
157 case V_038000_ARRAY_1D_TILED_THIN1:
158 default:
159 b_align = rscreen->tiling_info->group_bytes;
160 break;
161 }
162 return b_align;
163 }
164
165 static unsigned mip_minify(unsigned size, unsigned level)
166 {
167 unsigned val;
168 val = u_minify(size, level);
169 if (level > 0)
170 val = util_next_power_of_two(val);
171 return val;
172 }
173
174 static unsigned r600_texture_get_stride(struct pipe_screen *screen,
175 struct r600_resource_texture *rtex,
176 unsigned level)
177 {
178 struct r600_screen* rscreen = (struct r600_screen *)screen;
179 struct pipe_resource *ptex = &rtex->resource.base.b;
180 struct radeon *radeon = (struct radeon *)screen->winsys;
181 enum chip_class chipc = r600_get_family_class(radeon);
182 unsigned width, stride, tile_width;
183
184 if (rtex->pitch_override)
185 return rtex->pitch_override;
186
187 width = mip_minify(ptex->width0, level);
188 if (util_format_is_plain(ptex->format)) {
189 tile_width = r600_get_pixel_alignment(screen, ptex->format,
190 rtex->array_mode[level]);
191 width = align(width, tile_width);
192 }
193 stride = util_format_get_stride(ptex->format, width);
194
195 return stride;
196 }
197
198 static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
199 struct r600_resource_texture *rtex,
200 unsigned level)
201 {
202 struct pipe_resource *ptex = &rtex->resource.base.b;
203 unsigned height, tile_height;
204
205 height = mip_minify(ptex->height0, level);
206 if (util_format_is_plain(ptex->format)) {
207 tile_height = r600_get_height_alignment(screen,
208 rtex->array_mode[level]);
209 height = align(height, tile_height);
210 }
211 return util_format_get_nblocksy(ptex->format, height);
212 }
213
214 /* Get a width in pixels from a stride in bytes. */
215 static unsigned pitch_to_width(enum pipe_format format,
216 unsigned pitch_in_bytes)
217 {
218 return (pitch_in_bytes / util_format_get_blocksize(format)) *
219 util_format_get_blockwidth(format);
220 }
221
222 static void r600_texture_set_array_mode(struct pipe_screen *screen,
223 struct r600_resource_texture *rtex,
224 unsigned level, unsigned array_mode)
225 {
226 struct pipe_resource *ptex = &rtex->resource.base.b;
227
228 switch (array_mode) {
229 case V_0280A0_ARRAY_LINEAR_GENERAL:
230 case V_0280A0_ARRAY_LINEAR_ALIGNED:
231 case V_0280A0_ARRAY_1D_TILED_THIN1:
232 default:
233 rtex->array_mode[level] = array_mode;
234 break;
235 case V_0280A0_ARRAY_2D_TILED_THIN1:
236 {
237 unsigned w, h, tile_height, tile_width;
238
239 tile_height = r600_get_height_alignment(screen, array_mode);
240 tile_width = r600_get_pixel_alignment(screen, ptex->format, array_mode);
241
242 w = mip_minify(ptex->width0, level);
243 h = mip_minify(ptex->height0, level);
244 if (w < tile_width || h < tile_height)
245 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
246 else
247 rtex->array_mode[level] = array_mode;
248 }
249 break;
250 }
251 }
252
253 static void r600_setup_miptree(struct pipe_screen *screen,
254 struct r600_resource_texture *rtex,
255 unsigned array_mode)
256 {
257 struct pipe_resource *ptex = &rtex->resource.base.b;
258 struct radeon *radeon = (struct radeon *)screen->winsys;
259 enum chip_class chipc = r600_get_family_class(radeon);
260 unsigned pitch, size, layer_size, i, offset;
261 unsigned nblocksy;
262
263 for (i = 0, offset = 0; i <= ptex->last_level; i++) {
264 r600_texture_set_array_mode(screen, rtex, i, array_mode);
265
266 pitch = r600_texture_get_stride(screen, rtex, i);
267 nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
268
269 layer_size = pitch * nblocksy;
270
271 if (ptex->target == PIPE_TEXTURE_CUBE) {
272 if (chipc >= R700)
273 size = layer_size * 8;
274 else
275 size = layer_size * 6;
276 }
277 else
278 size = layer_size * u_minify(ptex->depth0, i);
279 /* align base image and start of miptree */
280 if ((i == 0) || (i == 1))
281 offset = align(offset, r600_get_base_alignment(screen, ptex->format, array_mode));
282 rtex->offset[i] = offset;
283 rtex->layer_size[i] = layer_size;
284 rtex->pitch_in_bytes[i] = pitch;
285 rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
286 offset += size;
287 }
288 rtex->size = offset;
289 }
290
291 static struct r600_resource_texture *
292 r600_texture_create_object(struct pipe_screen *screen,
293 const struct pipe_resource *base,
294 unsigned array_mode,
295 unsigned pitch_in_bytes_override,
296 unsigned max_buffer_size,
297 struct r600_bo *bo)
298 {
299 struct r600_resource_texture *rtex;
300 struct r600_resource *resource;
301 struct radeon *radeon = (struct radeon *)screen->winsys;
302
303 rtex = CALLOC_STRUCT(r600_resource_texture);
304 if (rtex == NULL)
305 return NULL;
306
307 resource = &rtex->resource;
308 resource->base.b = *base;
309 resource->base.vtbl = &r600_texture_vtbl;
310 pipe_reference_init(&resource->base.b.reference, 1);
311 resource->base.b.screen = screen;
312 resource->bo = bo;
313 rtex->pitch_override = pitch_in_bytes_override;
314
315 if (array_mode)
316 rtex->tiled = 1;
317 r600_setup_miptree(screen, rtex, array_mode);
318
319 resource->size = rtex->size;
320
321 if (!resource->bo) {
322 struct pipe_resource *ptex = &rtex->resource.base.b;
323 int base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
324
325 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage);
326 if (!resource->bo) {
327 FREE(rtex);
328 return NULL;
329 }
330 }
331 return rtex;
332 }
333
334 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
335 const struct pipe_resource *templ)
336 {
337 unsigned array_mode = 0;
338 static int force_tiling = -1;
339
340 /* Would like some magic "get_bool_option_once" routine.
341 */
342 if (force_tiling == -1)
343 force_tiling = debug_get_bool_option("R600_FORCE_TILING", FALSE);
344
345 if (force_tiling) {
346 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
347 !(templ->bind & PIPE_BIND_SCANOUT)) {
348 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
349 }
350 }
351
352 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
353 0, 0, NULL);
354
355 }
356
357 static void r600_texture_destroy(struct pipe_screen *screen,
358 struct pipe_resource *ptex)
359 {
360 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
361 struct r600_resource *resource = &rtex->resource;
362 struct radeon *radeon = (struct radeon *)screen->winsys;
363
364 if (rtex->flushed_depth_texture)
365 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
366
367 if (resource->bo) {
368 r600_bo_reference(radeon, &resource->bo, NULL);
369 }
370 FREE(rtex);
371 }
372
373 static boolean r600_texture_get_handle(struct pipe_screen* screen,
374 struct pipe_resource *ptex,
375 struct winsys_handle *whandle)
376 {
377 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
378 struct r600_resource *resource = &rtex->resource;
379 struct radeon *radeon = (struct radeon *)screen->winsys;
380
381 return r600_bo_get_winsys_handle(radeon, resource->bo,
382 rtex->pitch_in_bytes[0], whandle);
383 }
384
385 static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
386 struct pipe_resource *texture,
387 unsigned face, unsigned level,
388 unsigned zslice, unsigned flags)
389 {
390 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
391 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
392 unsigned offset, tile_height;
393
394 if (surface == NULL)
395 return NULL;
396 offset = r600_texture_get_offset(rtex, level, zslice, face);
397 pipe_reference_init(&surface->base.reference, 1);
398 pipe_resource_reference(&surface->base.texture, texture);
399 surface->base.format = texture->format;
400 surface->base.width = mip_minify(texture->width0, level);
401 surface->base.height = mip_minify(texture->height0, level);
402 surface->base.offset = offset;
403 surface->base.usage = flags;
404 surface->base.zslice = zslice;
405 surface->base.texture = texture;
406 surface->base.face = face;
407 surface->base.level = level;
408
409 tile_height = r600_get_height_alignment(screen, rtex->array_mode[level]);
410 surface->aligned_height = align(surface->base.height, tile_height);
411 return &surface->base;
412 }
413
414 static void r600_tex_surface_destroy(struct pipe_surface *surface)
415 {
416 pipe_resource_reference(&surface->texture, NULL);
417 FREE(surface);
418 }
419
420
421 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
422 const struct pipe_resource *templ,
423 struct winsys_handle *whandle)
424 {
425 struct radeon *rw = (struct radeon*)screen->winsys;
426 struct r600_bo *bo = NULL;
427 unsigned array_mode = 0;
428
429 /* Support only 2D textures without mipmaps */
430 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
431 templ->depth0 != 1 || templ->last_level != 0)
432 return NULL;
433
434 bo = r600_bo_handle(rw, whandle->handle, &array_mode);
435 if (bo == NULL) {
436 return NULL;
437 }
438
439 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
440 whandle->stride,
441 0,
442 bo);
443 }
444
445 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
446 struct pipe_resource *texture,
447 unsigned face, unsigned level)
448 {
449 /* FIXME */
450 return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
451 }
452
453 int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
454
455 int r600_texture_depth_flush(struct pipe_context *ctx,
456 struct pipe_resource *texture)
457 {
458 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
459 struct pipe_resource resource;
460
461 if (rtex->flushed_depth_texture)
462 goto out;
463
464 resource.target = PIPE_TEXTURE_2D;
465 resource.format = texture->format;
466 resource.width0 = texture->width0;
467 resource.height0 = texture->height0;
468 resource.depth0 = 1;
469 resource.last_level = 0;
470 resource.nr_samples = 0;
471 resource.usage = PIPE_USAGE_DYNAMIC;
472 resource.bind = 0;
473 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
474
475 resource.bind |= PIPE_BIND_DEPTH_STENCIL;
476
477 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
478 if (rtex->flushed_depth_texture == NULL) {
479 R600_ERR("failed to create temporary texture to hold untiled copy\n");
480 return -ENOMEM;
481 }
482
483 out:
484 /* XXX: only do this if the depth texture has actually changed:
485 */
486 r600_blit_uncompress_depth_ptr(ctx, rtex);
487 return 0;
488 }
489
490 /* Needs adjustment for pixelformat:
491 */
492 static INLINE unsigned u_box_volume( const struct pipe_box *box )
493 {
494 return box->width * box->depth * box->height;
495 };
496
497
498 /* Figure out whether u_blitter will fallback to a transfer operation.
499 * If so, don't use a staging resource.
500 */
501 static boolean permit_hardware_blit(struct pipe_screen *screen,
502 struct pipe_resource *res)
503 {
504 unsigned bind;
505
506 if (util_format_is_depth_or_stencil(res->format))
507 bind = PIPE_BIND_DEPTH_STENCIL;
508 else
509 bind = PIPE_BIND_RENDER_TARGET;
510
511 /* See r600_resource_copy_region: there is something wrong
512 * with depth resource copies at the moment so avoid them for
513 * now.
514 */
515 if (util_format_get_component_bits(res->format,
516 UTIL_FORMAT_COLORSPACE_ZS,
517 0) != 0)
518 return FALSE;
519
520 if (!screen->is_format_supported(screen,
521 res->format,
522 res->target,
523 res->nr_samples,
524 bind, 0))
525 return FALSE;
526
527 if (!screen->is_format_supported(screen,
528 res->format,
529 res->target,
530 res->nr_samples,
531 PIPE_BIND_SAMPLER_VIEW, 0))
532 return FALSE;
533
534 return TRUE;
535 }
536
537 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
538 struct pipe_resource *texture,
539 struct pipe_subresource sr,
540 unsigned usage,
541 const struct pipe_box *box)
542 {
543 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
544 struct pipe_resource resource;
545 struct r600_transfer *trans;
546 int r;
547 boolean use_staging_texture = FALSE;
548
549 /* We cannot map a tiled texture directly because the data is
550 * in a different order, therefore we do detiling using a blit.
551 *
552 * Also, use a temporary in GTT memory for read transfers, as
553 * the CPU is much happier reading out of cached system memory
554 * than uncached VRAM.
555 */
556 if (rtex->tiled)
557 use_staging_texture = TRUE;
558
559 if ((usage & PIPE_TRANSFER_READ) &&
560 u_box_volume(box) > 1024)
561 use_staging_texture = TRUE;
562
563 /* XXX: Use a staging texture for uploads if the underlying BO
564 * is busy. No interface for checking that currently? so do
565 * it eagerly whenever the transfer doesn't require a readback
566 * and might block.
567 */
568 if ((usage & PIPE_TRANSFER_WRITE) &&
569 !(usage & (PIPE_TRANSFER_READ |
570 PIPE_TRANSFER_DONTBLOCK |
571 PIPE_TRANSFER_UNSYNCHRONIZED)))
572 use_staging_texture = TRUE;
573
574 if (!permit_hardware_blit(ctx->screen, texture) ||
575 (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
576 use_staging_texture = FALSE;
577
578 trans = CALLOC_STRUCT(r600_transfer);
579 if (trans == NULL)
580 return NULL;
581 pipe_resource_reference(&trans->transfer.resource, texture);
582 trans->transfer.sr = sr;
583 trans->transfer.usage = usage;
584 trans->transfer.box = *box;
585 if (rtex->depth) {
586 /* XXX: only readback the rectangle which is being mapped?
587 */
588 /* XXX: when discard is true, no need to read back from depth texture
589 */
590 r = r600_texture_depth_flush(ctx, texture);
591 if (r < 0) {
592 R600_ERR("failed to create temporary texture to hold untiled copy\n");
593 pipe_resource_reference(&trans->transfer.resource, NULL);
594 FREE(trans);
595 return NULL;
596 }
597 } else if (use_staging_texture) {
598 resource.target = PIPE_TEXTURE_2D;
599 resource.format = texture->format;
600 resource.width0 = box->width;
601 resource.height0 = box->height;
602 resource.depth0 = 1;
603 resource.last_level = 0;
604 resource.nr_samples = 0;
605 resource.usage = PIPE_USAGE_STAGING;
606 resource.bind = 0;
607 resource.flags = R600_RESOURCE_FLAG_TRANSFER;
608 /* For texture reading, the temporary (detiled) texture is used as
609 * a render target when blitting from a tiled texture. */
610 if (usage & PIPE_TRANSFER_READ) {
611 resource.bind |= PIPE_BIND_RENDER_TARGET;
612 }
613 /* For texture writing, the temporary texture is used as a sampler
614 * when blitting into a tiled texture. */
615 if (usage & PIPE_TRANSFER_WRITE) {
616 resource.bind |= PIPE_BIND_SAMPLER_VIEW;
617 }
618 /* Create the temporary texture. */
619 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
620 if (trans->staging_texture == NULL) {
621 R600_ERR("failed to create temporary texture to hold untiled copy\n");
622 pipe_resource_reference(&trans->transfer.resource, NULL);
623 FREE(trans);
624 return NULL;
625 }
626
627 trans->transfer.stride =
628 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
629 if (usage & PIPE_TRANSFER_READ) {
630 r600_copy_to_staging_texture(ctx, trans);
631 /* Always referenced in the blit. */
632 ctx->flush(ctx, 0, NULL);
633 }
634 return &trans->transfer;
635 }
636 trans->transfer.stride = rtex->pitch_in_bytes[sr.level];
637 trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
638 return &trans->transfer;
639 }
640
641 void r600_texture_transfer_destroy(struct pipe_context *ctx,
642 struct pipe_transfer *transfer)
643 {
644 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
645 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
646
647 if (rtransfer->staging_texture) {
648 if (transfer->usage & PIPE_TRANSFER_WRITE) {
649 r600_copy_from_staging_texture(ctx, rtransfer);
650 }
651 pipe_resource_reference(&rtransfer->staging_texture, NULL);
652 }
653 if (rtex->flushed_depth_texture) {
654 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
655 }
656 pipe_resource_reference(&transfer->resource, NULL);
657 FREE(transfer);
658 }
659
660 void* r600_texture_transfer_map(struct pipe_context *ctx,
661 struct pipe_transfer* transfer)
662 {
663 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
664 struct r600_bo *bo;
665 enum pipe_format format = transfer->resource->format;
666 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
667 unsigned offset = 0;
668 unsigned usage = 0;
669 char *map;
670
671 if (rtransfer->staging_texture) {
672 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
673 } else {
674 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
675
676 if (rtex->flushed_depth_texture)
677 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
678 else
679 bo = ((struct r600_resource *)transfer->resource)->bo;
680
681 offset = rtransfer->offset +
682 transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
683 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
684 }
685
686 if (transfer->usage & PIPE_TRANSFER_WRITE) {
687 usage |= PB_USAGE_CPU_WRITE;
688
689 if (transfer->usage & PIPE_TRANSFER_DISCARD) {
690 }
691
692 if (transfer->usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
693 }
694 }
695
696 if (transfer->usage & PIPE_TRANSFER_READ) {
697 usage |= PB_USAGE_CPU_READ;
698 }
699
700 if (transfer->usage & PIPE_TRANSFER_DONTBLOCK) {
701 usage |= PB_USAGE_DONTBLOCK;
702 }
703
704 if (transfer->usage & PIPE_TRANSFER_UNSYNCHRONIZED) {
705 usage |= PB_USAGE_UNSYNCHRONIZED;
706 }
707
708 map = r600_bo_map(radeon, bo, usage, ctx);
709 if (!map) {
710 return NULL;
711 }
712
713 return map + offset;
714 }
715
716 void r600_texture_transfer_unmap(struct pipe_context *ctx,
717 struct pipe_transfer* transfer)
718 {
719 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
720 struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
721 struct r600_bo *bo;
722
723 if (rtransfer->staging_texture) {
724 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo;
725 } else {
726 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
727
728 if (rtex->flushed_depth_texture) {
729 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
730 } else {
731 bo = ((struct r600_resource *)transfer->resource)->bo;
732 }
733 }
734 r600_bo_unmap(radeon, bo);
735 }
736
737 struct u_resource_vtbl r600_texture_vtbl =
738 {
739 r600_texture_get_handle, /* get_handle */
740 r600_texture_destroy, /* resource_destroy */
741 r600_texture_is_referenced, /* is_resource_referenced */
742 r600_texture_get_transfer, /* get_transfer */
743 r600_texture_transfer_destroy, /* transfer_destroy */
744 r600_texture_transfer_map, /* transfer_map */
745 u_default_transfer_flush_region,/* transfer_flush_region */
746 r600_texture_transfer_unmap, /* transfer_unmap */
747 u_default_transfer_inline_write /* transfer_inline_write */
748 };
749
750 void r600_init_screen_texture_functions(struct pipe_screen *screen)
751 {
752 screen->get_tex_surface = r600_get_tex_surface;
753 screen->tex_surface_destroy = r600_tex_surface_destroy;
754 }
755
756 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
757 const unsigned char *swizzle_view)
758 {
759 unsigned i;
760 unsigned char swizzle[4];
761 unsigned result = 0;
762 const uint32_t swizzle_shift[4] = {
763 16, 19, 22, 25,
764 };
765 const uint32_t swizzle_bit[4] = {
766 0, 1, 2, 3,
767 };
768
769 if (swizzle_view) {
770 /* Combine two sets of swizzles. */
771 for (i = 0; i < 4; i++) {
772 swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
773 swizzle_format[swizzle_view[i]] : swizzle_view[i];
774 }
775 } else {
776 memcpy(swizzle, swizzle_format, 4);
777 }
778
779 /* Get swizzle. */
780 for (i = 0; i < 4; i++) {
781 switch (swizzle[i]) {
782 case UTIL_FORMAT_SWIZZLE_Y:
783 result |= swizzle_bit[1] << swizzle_shift[i];
784 break;
785 case UTIL_FORMAT_SWIZZLE_Z:
786 result |= swizzle_bit[2] << swizzle_shift[i];
787 break;
788 case UTIL_FORMAT_SWIZZLE_W:
789 result |= swizzle_bit[3] << swizzle_shift[i];
790 break;
791 case UTIL_FORMAT_SWIZZLE_0:
792 result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
793 break;
794 case UTIL_FORMAT_SWIZZLE_1:
795 result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
796 break;
797 default: /* UTIL_FORMAT_SWIZZLE_X */
798 result |= swizzle_bit[0] << swizzle_shift[i];
799 }
800 }
801 return result;
802 }
803
804 /* texture format translate */
805 uint32_t r600_translate_texformat(enum pipe_format format,
806 const unsigned char *swizzle_view,
807 uint32_t *word4_p, uint32_t *yuv_format_p)
808 {
809 uint32_t result = 0, word4 = 0, yuv_format = 0;
810 const struct util_format_description *desc;
811 boolean uniform = TRUE;
812 int i;
813 const uint32_t sign_bit[4] = {
814 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
815 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
816 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
817 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
818 };
819 desc = util_format_description(format);
820
821 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
822
823 /* Colorspace (return non-RGB formats directly). */
824 switch (desc->colorspace) {
825 /* Depth stencil formats */
826 case UTIL_FORMAT_COLORSPACE_ZS:
827 switch (format) {
828 case PIPE_FORMAT_Z16_UNORM:
829 result = FMT_16;
830 goto out_word4;
831 case PIPE_FORMAT_X24S8_USCALED:
832 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
833 case PIPE_FORMAT_Z24X8_UNORM:
834 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
835 result = FMT_8_24;
836 goto out_word4;
837 case PIPE_FORMAT_S8X24_USCALED:
838 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
839 case PIPE_FORMAT_X8Z24_UNORM:
840 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
841 result = FMT_24_8;
842 goto out_word4;
843 case PIPE_FORMAT_S8_USCALED:
844 result = FMT_8;
845 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
846 goto out_word4;
847 default:
848 goto out_unknown;
849 }
850
851 case UTIL_FORMAT_COLORSPACE_YUV:
852 yuv_format |= (1 << 30);
853 switch (format) {
854 case PIPE_FORMAT_UYVY:
855 case PIPE_FORMAT_YUYV:
856 default:
857 break;
858 }
859 goto out_unknown; /* TODO */
860
861 case UTIL_FORMAT_COLORSPACE_SRGB:
862 word4 |= S_038010_FORCE_DEGAMMA(1);
863 if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
864 goto out_unknown; /* fails for some reason - TODO */
865 break;
866
867 default:
868 break;
869 }
870
871 /* S3TC formats. TODO */
872 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
873 static int r600_enable_s3tc = -1;
874
875 if (r600_enable_s3tc == -1)
876 r600_enable_s3tc =
877 debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
878
879 if (!r600_enable_s3tc)
880 goto out_unknown;
881
882 switch (format) {
883 case PIPE_FORMAT_DXT1_RGB:
884 case PIPE_FORMAT_DXT1_RGBA:
885 result = FMT_BC1;
886 goto out_word4;
887 case PIPE_FORMAT_DXT3_RGBA:
888 result = FMT_BC2;
889 goto out_word4;
890 case PIPE_FORMAT_DXT5_RGBA:
891 result = FMT_BC3;
892 goto out_word4;
893 default:
894 goto out_unknown;
895 }
896 }
897
898
899 for (i = 0; i < desc->nr_channels; i++) {
900 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
901 word4 |= sign_bit[i];
902 }
903 }
904
905 /* R8G8Bx_SNORM - TODO CxV8U8 */
906
907 /* RGTC - TODO */
908
909 /* See whether the components are of the same size. */
910 for (i = 1; i < desc->nr_channels; i++) {
911 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
912 }
913
914 /* Non-uniform formats. */
915 if (!uniform) {
916 switch(desc->nr_channels) {
917 case 3:
918 if (desc->channel[0].size == 5 &&
919 desc->channel[1].size == 6 &&
920 desc->channel[2].size == 5) {
921 result = FMT_5_6_5;
922 goto out_word4;
923 }
924 goto out_unknown;
925 case 4:
926 if (desc->channel[0].size == 5 &&
927 desc->channel[1].size == 5 &&
928 desc->channel[2].size == 5 &&
929 desc->channel[3].size == 1) {
930 result = FMT_1_5_5_5;
931 goto out_word4;
932 }
933 if (desc->channel[0].size == 10 &&
934 desc->channel[1].size == 10 &&
935 desc->channel[2].size == 10 &&
936 desc->channel[3].size == 2) {
937 result = FMT_10_10_10_2;
938 goto out_word4;
939 }
940 goto out_unknown;
941 }
942 goto out_unknown;
943 }
944
945 /* Find the first non-VOID channel. */
946 for (i = 0; i < 4; i++) {
947 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
948 break;
949 }
950 }
951
952 if (i == 4)
953 goto out_unknown;
954
955 /* uniform formats */
956 switch (desc->channel[i].type) {
957 case UTIL_FORMAT_TYPE_UNSIGNED:
958 case UTIL_FORMAT_TYPE_SIGNED:
959 if (!desc->channel[i].normalized &&
960 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
961 goto out_unknown;
962 }
963
964 switch (desc->channel[i].size) {
965 case 4:
966 switch (desc->nr_channels) {
967 case 2:
968 result = FMT_4_4;
969 goto out_word4;
970 case 4:
971 result = FMT_4_4_4_4;
972 goto out_word4;
973 }
974 goto out_unknown;
975 case 8:
976 switch (desc->nr_channels) {
977 case 1:
978 result = FMT_8;
979 goto out_word4;
980 case 2:
981 result = FMT_8_8;
982 goto out_word4;
983 case 4:
984 result = FMT_8_8_8_8;
985 goto out_word4;
986 }
987 goto out_unknown;
988 case 16:
989 switch (desc->nr_channels) {
990 case 1:
991 result = FMT_16;
992 goto out_word4;
993 case 2:
994 result = FMT_16_16;
995 goto out_word4;
996 case 4:
997 result = FMT_16_16_16_16;
998 goto out_word4;
999 }
1000 }
1001 goto out_unknown;
1002
1003 case UTIL_FORMAT_TYPE_FLOAT:
1004 switch (desc->channel[i].size) {
1005 case 16:
1006 switch (desc->nr_channels) {
1007 case 1:
1008 result = FMT_16_FLOAT;
1009 goto out_word4;
1010 case 2:
1011 result = FMT_16_16_FLOAT;
1012 goto out_word4;
1013 case 4:
1014 result = FMT_16_16_16_16_FLOAT;
1015 goto out_word4;
1016 }
1017 goto out_unknown;
1018 case 32:
1019 switch (desc->nr_channels) {
1020 case 1:
1021 result = FMT_32_FLOAT;
1022 goto out_word4;
1023 case 2:
1024 result = FMT_32_32_FLOAT;
1025 goto out_word4;
1026 case 4:
1027 result = FMT_32_32_32_32_FLOAT;
1028 goto out_word4;
1029 }
1030 }
1031
1032 }
1033 out_word4:
1034 if (word4_p)
1035 *word4_p = word4;
1036 if (yuv_format_p)
1037 *yuv_format_p = yuv_format;
1038 return result;
1039 out_unknown:
1040 // R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
1041 return ~0;
1042 }