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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / gallium / drivers / r600 / r600_texture.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 * Corbin Simpson
26 */
27 #include "r600_pipe_common.h"
28 #include "r600_cs.h"
29 #include "r600_query.h"
30 #include "util/format/u_format.h"
31 #include "util/u_log.h"
32 #include "util/u_memory.h"
33 #include "util/u_pack_color.h"
34 #include "util/u_surface.h"
35 #include "util/os_time.h"
36 #include "frontend/winsys_handle.h"
37 #include <errno.h>
38 #include <inttypes.h>
39
40 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
41 struct r600_texture *rtex);
42 static enum radeon_surf_mode
43 r600_choose_tiling(struct r600_common_screen *rscreen,
44 const struct pipe_resource *templ);
45
46
47 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
48 struct r600_texture *rdst,
49 unsigned dst_level, unsigned dstx,
50 unsigned dsty, unsigned dstz,
51 struct r600_texture *rsrc,
52 unsigned src_level,
53 const struct pipe_box *src_box)
54 {
55 if (!rctx->dma.cs)
56 return false;
57
58 if (rdst->surface.bpe != rsrc->surface.bpe)
59 return false;
60
61 /* MSAA: Blits don't exist in the real world. */
62 if (rsrc->resource.b.b.nr_samples > 1 ||
63 rdst->resource.b.b.nr_samples > 1)
64 return false;
65
66 /* Depth-stencil surfaces:
67 * When dst is linear, the DB->CB copy preserves HTILE.
68 * When dst is tiled, the 3D path must be used to update HTILE.
69 */
70 if (rsrc->is_depth || rdst->is_depth)
71 return false;
72
73 /* CMASK as:
74 * src: Both texture and SDMA paths need decompression. Use SDMA.
75 * dst: If overwriting the whole texture, discard CMASK and use
76 * SDMA. Otherwise, use the 3D path.
77 */
78 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) {
79 /* The CMASK clear is only enabled for the first level. */
80 assert(dst_level == 0);
81 if (!util_texrange_covers_whole_level(&rdst->resource.b.b, dst_level,
82 dstx, dsty, dstz, src_box->width,
83 src_box->height, src_box->depth))
84 return false;
85
86 r600_texture_discard_cmask(rctx->screen, rdst);
87 }
88
89 /* All requirements are met. Prepare textures for SDMA. */
90 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level))
91 rctx->b.flush_resource(&rctx->b, &rsrc->resource.b.b);
92
93 assert(!(rsrc->dirty_level_mask & (1 << src_level)));
94 assert(!(rdst->dirty_level_mask & (1 << dst_level)));
95
96 return true;
97 }
98
99 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
100 static void r600_copy_region_with_blit(struct pipe_context *pipe,
101 struct pipe_resource *dst,
102 unsigned dst_level,
103 unsigned dstx, unsigned dsty, unsigned dstz,
104 struct pipe_resource *src,
105 unsigned src_level,
106 const struct pipe_box *src_box)
107 {
108 struct pipe_blit_info blit;
109
110 memset(&blit, 0, sizeof(blit));
111 blit.src.resource = src;
112 blit.src.format = src->format;
113 blit.src.level = src_level;
114 blit.src.box = *src_box;
115 blit.dst.resource = dst;
116 blit.dst.format = dst->format;
117 blit.dst.level = dst_level;
118 blit.dst.box.x = dstx;
119 blit.dst.box.y = dsty;
120 blit.dst.box.z = dstz;
121 blit.dst.box.width = src_box->width;
122 blit.dst.box.height = src_box->height;
123 blit.dst.box.depth = src_box->depth;
124 blit.mask = util_format_get_mask(src->format) &
125 util_format_get_mask(dst->format);
126 blit.filter = PIPE_TEX_FILTER_NEAREST;
127
128 if (blit.mask) {
129 pipe->blit(pipe, &blit);
130 }
131 }
132
133 /* Copy from a full GPU texture to a transfer's staging one. */
134 static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
135 {
136 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
137 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
138 struct pipe_resource *dst = &rtransfer->staging->b.b;
139 struct pipe_resource *src = transfer->resource;
140
141 if (src->nr_samples > 1) {
142 r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
143 src, transfer->level, &transfer->box);
144 return;
145 }
146
147 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
148 &transfer->box);
149 }
150
151 /* Copy from a transfer's staging texture to a full GPU one. */
152 static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
153 {
154 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
155 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
156 struct pipe_resource *dst = transfer->resource;
157 struct pipe_resource *src = &rtransfer->staging->b.b;
158 struct pipe_box sbox;
159
160 u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
161
162 if (dst->nr_samples > 1) {
163 r600_copy_region_with_blit(ctx, dst, transfer->level,
164 transfer->box.x, transfer->box.y, transfer->box.z,
165 src, 0, &sbox);
166 return;
167 }
168
169 rctx->dma_copy(ctx, dst, transfer->level,
170 transfer->box.x, transfer->box.y, transfer->box.z,
171 src, 0, &sbox);
172 }
173
174 static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
175 struct r600_texture *rtex, unsigned level,
176 const struct pipe_box *box,
177 unsigned *stride,
178 unsigned *layer_stride)
179 {
180 *stride = rtex->surface.u.legacy.level[level].nblk_x *
181 rtex->surface.bpe;
182 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
183 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
184
185 if (!box)
186 return rtex->surface.u.legacy.level[level].offset;
187
188 /* Each texture is an array of mipmap levels. Each level is
189 * an array of slices. */
190 return rtex->surface.u.legacy.level[level].offset +
191 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
192 (box->y / rtex->surface.blk_h *
193 rtex->surface.u.legacy.level[level].nblk_x +
194 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
195 }
196
197 static int r600_init_surface(struct r600_common_screen *rscreen,
198 struct radeon_surf *surface,
199 const struct pipe_resource *ptex,
200 enum radeon_surf_mode array_mode,
201 unsigned pitch_in_bytes_override,
202 unsigned offset,
203 bool is_imported,
204 bool is_scanout,
205 bool is_flushed_depth)
206 {
207 const struct util_format_description *desc =
208 util_format_description(ptex->format);
209 bool is_depth, is_stencil;
210 int r;
211 unsigned i, bpe, flags = 0;
212
213 is_depth = util_format_has_depth(desc);
214 is_stencil = util_format_has_stencil(desc);
215
216 if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
217 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
218 bpe = 4; /* stencil is allocated separately on evergreen */
219 } else {
220 bpe = util_format_get_blocksize(ptex->format);
221 assert(util_is_power_of_two_or_zero(bpe));
222 }
223
224 if (!is_flushed_depth && is_depth) {
225 flags |= RADEON_SURF_ZBUFFER;
226
227 if (is_stencil)
228 flags |= RADEON_SURF_SBUFFER;
229 }
230
231 if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
232 /* This should catch bugs in gallium users setting incorrect flags. */
233 assert(ptex->nr_samples <= 1 &&
234 ptex->array_size == 1 &&
235 ptex->depth0 == 1 &&
236 ptex->last_level == 0 &&
237 !(flags & RADEON_SURF_Z_OR_SBUFFER));
238
239 flags |= RADEON_SURF_SCANOUT;
240 }
241
242 if (ptex->bind & PIPE_BIND_SHARED)
243 flags |= RADEON_SURF_SHAREABLE;
244 if (is_imported)
245 flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
246
247 r = rscreen->ws->surface_init(rscreen->ws, ptex,
248 flags, bpe, array_mode, surface);
249 if (r) {
250 return r;
251 }
252
253 if (pitch_in_bytes_override &&
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
255 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
256 * for those
257 */
258 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
259 surface->u.legacy.level[0].slice_size_dw =
260 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4;
261 }
262
263 if (offset) {
264 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
265 surface->u.legacy.level[i].offset += offset;
266 }
267
268 return 0;
269 }
270
271 static void r600_texture_init_metadata(struct r600_common_screen *rscreen,
272 struct r600_texture *rtex,
273 struct radeon_bo_metadata *metadata)
274 {
275 struct radeon_surf *surface = &rtex->surface;
276
277 memset(metadata, 0, sizeof(*metadata));
278
279 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
280 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
281 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
282 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
283 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
284 metadata->u.legacy.bankw = surface->u.legacy.bankw;
285 metadata->u.legacy.bankh = surface->u.legacy.bankh;
286 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
287 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
288 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
289 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
290 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
291 }
292
293 static void r600_surface_import_metadata(struct r600_common_screen *rscreen,
294 struct radeon_surf *surf,
295 struct radeon_bo_metadata *metadata,
296 enum radeon_surf_mode *array_mode,
297 bool *is_scanout)
298 {
299 surf->u.legacy.pipe_config = metadata->u.legacy.pipe_config;
300 surf->u.legacy.bankw = metadata->u.legacy.bankw;
301 surf->u.legacy.bankh = metadata->u.legacy.bankh;
302 surf->u.legacy.tile_split = metadata->u.legacy.tile_split;
303 surf->u.legacy.mtilea = metadata->u.legacy.mtilea;
304 surf->u.legacy.num_banks = metadata->u.legacy.num_banks;
305
306 if (metadata->u.legacy.macrotile == RADEON_LAYOUT_TILED)
307 *array_mode = RADEON_SURF_MODE_2D;
308 else if (metadata->u.legacy.microtile == RADEON_LAYOUT_TILED)
309 *array_mode = RADEON_SURF_MODE_1D;
310 else
311 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
312
313 *is_scanout = metadata->u.legacy.scanout;
314 }
315
316 static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
317 struct r600_texture *rtex)
318 {
319 struct r600_common_screen *rscreen = rctx->screen;
320 struct pipe_context *ctx = &rctx->b;
321
322 if (ctx == rscreen->aux_context)
323 mtx_lock(&rscreen->aux_context_lock);
324
325 ctx->flush_resource(ctx, &rtex->resource.b.b);
326 ctx->flush(ctx, NULL, 0);
327
328 if (ctx == rscreen->aux_context)
329 mtx_unlock(&rscreen->aux_context_lock);
330 }
331
332 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
333 struct r600_texture *rtex)
334 {
335 if (!rtex->cmask.size)
336 return;
337
338 assert(rtex->resource.b.b.nr_samples <= 1);
339
340 /* Disable CMASK. */
341 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
342 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
343 rtex->dirty_level_mask = 0;
344
345 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
346
347 if (rtex->cmask_buffer != &rtex->resource)
348 r600_resource_reference(&rtex->cmask_buffer, NULL);
349
350 /* Notify all contexts about the change. */
351 p_atomic_inc(&rscreen->dirty_tex_counter);
352 p_atomic_inc(&rscreen->compressed_colortex_counter);
353 }
354
355 static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
356 struct r600_texture *rtex,
357 unsigned new_bind_flag,
358 bool invalidate_storage)
359 {
360 struct pipe_screen *screen = rctx->b.screen;
361 struct r600_texture *new_tex;
362 struct pipe_resource templ = rtex->resource.b.b;
363 unsigned i;
364
365 templ.bind |= new_bind_flag;
366
367 /* r600g doesn't react to dirty_tex_descriptor_counter */
368 if (rctx->chip_class < GFX6)
369 return;
370
371 if (rtex->resource.b.is_shared)
372 return;
373
374 if (new_bind_flag == PIPE_BIND_LINEAR) {
375 if (rtex->surface.is_linear)
376 return;
377
378 /* This fails with MSAA, depth, and compressed textures. */
379 if (r600_choose_tiling(rctx->screen, &templ) !=
380 RADEON_SURF_MODE_LINEAR_ALIGNED)
381 return;
382 }
383
384 new_tex = (struct r600_texture*)screen->resource_create(screen, &templ);
385 if (!new_tex)
386 return;
387
388 /* Copy the pixels to the new texture. */
389 if (!invalidate_storage) {
390 for (i = 0; i <= templ.last_level; i++) {
391 struct pipe_box box;
392
393 u_box_3d(0, 0, 0,
394 u_minify(templ.width0, i), u_minify(templ.height0, i),
395 util_num_layers(&templ, i), &box);
396
397 rctx->dma_copy(&rctx->b, &new_tex->resource.b.b, i, 0, 0, 0,
398 &rtex->resource.b.b, i, &box);
399 }
400 }
401
402 if (new_bind_flag == PIPE_BIND_LINEAR) {
403 r600_texture_discard_cmask(rctx->screen, rtex);
404 }
405
406 /* Replace the structure fields of rtex. */
407 rtex->resource.b.b.bind = templ.bind;
408 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
409 rtex->resource.gpu_address = new_tex->resource.gpu_address;
410 rtex->resource.vram_usage = new_tex->resource.vram_usage;
411 rtex->resource.gart_usage = new_tex->resource.gart_usage;
412 rtex->resource.bo_size = new_tex->resource.bo_size;
413 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
414 rtex->resource.domains = new_tex->resource.domains;
415 rtex->resource.flags = new_tex->resource.flags;
416 rtex->size = new_tex->size;
417 rtex->db_render_format = new_tex->db_render_format;
418 rtex->db_compatible = new_tex->db_compatible;
419 rtex->can_sample_z = new_tex->can_sample_z;
420 rtex->can_sample_s = new_tex->can_sample_s;
421 rtex->surface = new_tex->surface;
422 rtex->fmask = new_tex->fmask;
423 rtex->cmask = new_tex->cmask;
424 rtex->cb_color_info = new_tex->cb_color_info;
425 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
426 rtex->htile_offset = new_tex->htile_offset;
427 rtex->depth_cleared = new_tex->depth_cleared;
428 rtex->stencil_cleared = new_tex->stencil_cleared;
429 rtex->non_disp_tiling = new_tex->non_disp_tiling;
430 rtex->framebuffers_bound = new_tex->framebuffers_bound;
431
432 if (new_bind_flag == PIPE_BIND_LINEAR) {
433 assert(!rtex->htile_offset);
434 assert(!rtex->cmask.size);
435 assert(!rtex->fmask.size);
436 assert(!rtex->is_depth);
437 }
438
439 r600_texture_reference(&new_tex, NULL);
440
441 p_atomic_inc(&rctx->screen->dirty_tex_counter);
442 }
443
444 static void r600_texture_get_info(struct pipe_screen* screen,
445 struct pipe_resource *resource,
446 unsigned *pstride,
447 unsigned *poffset)
448 {
449 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
450 struct r600_texture *rtex = (struct r600_texture*)resource;
451 unsigned stride = 0;
452 unsigned offset = 0;
453
454 if (!rscreen || !rtex)
455 return;
456
457 if (resource->target != PIPE_BUFFER) {
458 offset = rtex->surface.u.legacy.level[0].offset;
459 stride = rtex->surface.u.legacy.level[0].nblk_x *
460 rtex->surface.bpe;
461 }
462
463 if (pstride)
464 *pstride = stride;
465
466 if (poffset)
467 *poffset = offset;
468 }
469
470 static bool r600_texture_get_handle(struct pipe_screen* screen,
471 struct pipe_context *ctx,
472 struct pipe_resource *resource,
473 struct winsys_handle *whandle,
474 unsigned usage)
475 {
476 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
477 struct r600_common_context *rctx;
478 struct r600_resource *res = (struct r600_resource*)resource;
479 struct r600_texture *rtex = (struct r600_texture*)resource;
480 struct radeon_bo_metadata metadata;
481 bool update_metadata = false;
482 unsigned stride, offset, slice_size;
483
484 ctx = threaded_context_unwrap_sync(ctx);
485 rctx = (struct r600_common_context*)(ctx ? ctx : rscreen->aux_context);
486
487 if (resource->target != PIPE_BUFFER) {
488 /* This is not supported now, but it might be required for OpenCL
489 * interop in the future.
490 */
491 if (resource->nr_samples > 1 || rtex->is_depth)
492 return false;
493
494 /* Move a suballocated texture into a non-suballocated allocation. */
495 if (rscreen->ws->buffer_is_suballocated(res->buf) ||
496 rtex->surface.tile_swizzle) {
497 assert(!res->b.is_shared);
498 r600_reallocate_texture_inplace(rctx, rtex,
499 PIPE_BIND_SHARED, false);
500 rctx->b.flush(&rctx->b, NULL, 0);
501 assert(res->b.b.bind & PIPE_BIND_SHARED);
502 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
503 assert(rtex->surface.tile_swizzle == 0);
504 }
505
506 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
507 rtex->cmask.size) {
508 /* Eliminate fast clear (CMASK) */
509 r600_eliminate_fast_color_clear(rctx, rtex);
510
511 /* Disable CMASK if flush_resource isn't going
512 * to be called.
513 */
514 if (rtex->cmask.size)
515 r600_texture_discard_cmask(rscreen, rtex);
516 }
517
518 /* Set metadata. */
519 if (!res->b.is_shared || update_metadata) {
520 r600_texture_init_metadata(rscreen, rtex, &metadata);
521
522 rscreen->ws->buffer_set_metadata(res->buf, &metadata, NULL);
523 }
524
525 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
526 } else {
527 /* Move a suballocated buffer into a non-suballocated allocation. */
528 if (rscreen->ws->buffer_is_suballocated(res->buf)) {
529 assert(!res->b.is_shared);
530
531 /* Allocate a new buffer with PIPE_BIND_SHARED. */
532 struct pipe_resource templ = res->b.b;
533 templ.bind |= PIPE_BIND_SHARED;
534
535 struct pipe_resource *newb =
536 screen->resource_create(screen, &templ);
537 if (!newb)
538 return false;
539
540 /* Copy the old buffer contents to the new one. */
541 struct pipe_box box;
542 u_box_1d(0, newb->width0, &box);
543 rctx->b.resource_copy_region(&rctx->b, newb, 0, 0, 0, 0,
544 &res->b.b, 0, &box);
545 /* Move the new buffer storage to the old pipe_resource. */
546 r600_replace_buffer_storage(&rctx->b, &res->b.b, newb);
547 pipe_resource_reference(&newb, NULL);
548
549 assert(res->b.b.bind & PIPE_BIND_SHARED);
550 assert(res->flags & RADEON_FLAG_NO_SUBALLOC);
551 }
552
553 /* Buffers */
554 slice_size = 0;
555 }
556
557 r600_texture_get_info(screen, resource, &stride, &offset);
558
559 if (res->b.is_shared) {
560 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
561 * doesn't set it.
562 */
563 res->external_usage |= usage & ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
564 if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
565 res->external_usage &= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH;
566 } else {
567 res->b.is_shared = true;
568 res->external_usage = usage;
569 }
570
571 whandle->stride = stride;
572 whandle->offset = offset + slice_size * whandle->layer;
573
574 return rscreen->ws->buffer_get_handle(rscreen->ws, res->buf, whandle);
575 }
576
577 static void r600_texture_destroy(struct pipe_screen *screen,
578 struct pipe_resource *ptex)
579 {
580 struct r600_texture *rtex = (struct r600_texture*)ptex;
581 struct r600_resource *resource = &rtex->resource;
582
583 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
584 pipe_resource_reference((struct pipe_resource**)&resource->immed_buffer, NULL);
585
586 if (rtex->cmask_buffer != &rtex->resource) {
587 r600_resource_reference(&rtex->cmask_buffer, NULL);
588 }
589 pb_reference(&resource->buf, NULL);
590 FREE(rtex);
591 }
592
593 static const struct u_resource_vtbl r600_texture_vtbl;
594
595 /* The number of samples can be specified independently of the texture. */
596 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
597 struct r600_texture *rtex,
598 unsigned nr_samples,
599 struct r600_fmask_info *out)
600 {
601 /* FMASK is allocated like an ordinary texture. */
602 struct pipe_resource templ = rtex->resource.b.b;
603 struct radeon_surf fmask = {};
604 unsigned flags, bpe;
605
606 memset(out, 0, sizeof(*out));
607
608 templ.nr_samples = 1;
609 flags = rtex->surface.flags | RADEON_SURF_FMASK;
610
611 /* Use the same parameters and tile mode. */
612 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
613 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
614 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
615 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
616
617 if (nr_samples <= 4)
618 fmask.u.legacy.bankh = 4;
619
620 switch (nr_samples) {
621 case 2:
622 case 4:
623 bpe = 1;
624 break;
625 case 8:
626 bpe = 4;
627 break;
628 default:
629 R600_ERR("Invalid sample count for FMASK allocation.\n");
630 return;
631 }
632
633 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
634 * This can be fixed by writing a separate FMASK allocator specifically
635 * for R600-R700 asics. */
636 if (rscreen->chip_class <= R700) {
637 bpe *= 2;
638 }
639
640 if (rscreen->ws->surface_init(rscreen->ws, &templ,
641 flags, bpe, RADEON_SURF_MODE_2D, &fmask)) {
642 R600_ERR("Got error in surface_init while allocating FMASK.\n");
643 return;
644 }
645
646 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
647
648 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
649 if (out->slice_tile_max)
650 out->slice_tile_max -= 1;
651
652 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
653 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
654 out->bank_height = fmask.u.legacy.bankh;
655 out->tile_swizzle = fmask.tile_swizzle;
656 out->alignment = MAX2(256, fmask.surf_alignment);
657 out->size = fmask.surf_size;
658 }
659
660 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
661 struct r600_texture *rtex)
662 {
663 r600_texture_get_fmask_info(rscreen, rtex,
664 rtex->resource.b.b.nr_samples, &rtex->fmask);
665
666 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
667 rtex->size = rtex->fmask.offset + rtex->fmask.size;
668 }
669
670 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
671 struct r600_texture *rtex,
672 struct r600_cmask_info *out)
673 {
674 unsigned cmask_tile_width = 8;
675 unsigned cmask_tile_height = 8;
676 unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height;
677 unsigned element_bits = 4;
678 unsigned cmask_cache_bits = 1024;
679 unsigned num_pipes = rscreen->info.num_tile_pipes;
680 unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
681
682 unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
683 unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
684 unsigned sqrt_pixels_per_macro_tile = sqrt(pixels_per_macro_tile);
685 unsigned macro_tile_width = util_next_power_of_two(sqrt_pixels_per_macro_tile);
686 unsigned macro_tile_height = pixels_per_macro_tile / macro_tile_width;
687
688 unsigned pitch_elements = align(rtex->resource.b.b.width0, macro_tile_width);
689 unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
690
691 unsigned base_align = num_pipes * pipe_interleave_bytes;
692 unsigned slice_bytes =
693 ((pitch_elements * height * element_bits + 7) / 8) / cmask_tile_elements;
694
695 assert(macro_tile_width % 128 == 0);
696 assert(macro_tile_height % 128 == 0);
697
698 out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
699 out->alignment = MAX2(256, base_align);
700 out->size = util_num_layers(&rtex->resource.b.b, 0) *
701 align(slice_bytes, base_align);
702 }
703
704 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
705 struct r600_texture *rtex)
706 {
707 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
708
709 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
710 rtex->size = rtex->cmask.offset + rtex->cmask.size;
711
712 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
713 }
714
715 static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
716 struct r600_texture *rtex)
717 {
718 if (rtex->cmask_buffer)
719 return;
720
721 assert(rtex->cmask.size == 0);
722
723 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
724
725 rtex->cmask_buffer = (struct r600_resource *)
726 r600_aligned_buffer_create(&rscreen->b,
727 R600_RESOURCE_FLAG_UNMAPPABLE,
728 PIPE_USAGE_DEFAULT,
729 rtex->cmask.size,
730 rtex->cmask.alignment);
731 if (rtex->cmask_buffer == NULL) {
732 rtex->cmask.size = 0;
733 return;
734 }
735
736 /* update colorbuffer state bits */
737 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
738
739 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
740
741 p_atomic_inc(&rscreen->compressed_colortex_counter);
742 }
743
744 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
745 struct r600_resource *res,
746 unsigned immed_size)
747 {
748 res->immed_buffer = (struct r600_resource *)
749 pipe_buffer_create(&rscreen->b, PIPE_BIND_CUSTOM,
750 PIPE_USAGE_DEFAULT, immed_size);
751 }
752
753 static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
754 struct r600_texture *rtex)
755 {
756 unsigned cl_width, cl_height, width, height;
757 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
758 unsigned num_pipes = rscreen->info.num_tile_pipes;
759
760 rtex->surface.htile_size = 0;
761
762 if (rscreen->chip_class <= EVERGREEN &&
763 rscreen->info.drm_minor < 26)
764 return;
765
766 /* HW bug on R6xx. */
767 if (rscreen->chip_class == R600 &&
768 (rtex->resource.b.b.width0 > 7680 ||
769 rtex->resource.b.b.height0 > 7680))
770 return;
771
772 switch (num_pipes) {
773 case 1:
774 cl_width = 32;
775 cl_height = 16;
776 break;
777 case 2:
778 cl_width = 32;
779 cl_height = 32;
780 break;
781 case 4:
782 cl_width = 64;
783 cl_height = 32;
784 break;
785 case 8:
786 cl_width = 64;
787 cl_height = 64;
788 break;
789 case 16:
790 cl_width = 128;
791 cl_height = 64;
792 break;
793 default:
794 assert(0);
795 return;
796 }
797
798 width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
799 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
800
801 slice_elements = (width * height) / (8 * 8);
802 slice_bytes = slice_elements * 4;
803
804 pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
805 base_align = num_pipes * pipe_interleave_bytes;
806
807 rtex->surface.htile_alignment = base_align;
808 rtex->surface.htile_size =
809 util_num_layers(&rtex->resource.b.b, 0) *
810 align(slice_bytes, base_align);
811 }
812
813 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
814 struct r600_texture *rtex)
815 {
816 r600_texture_get_htile_size(rscreen, rtex);
817
818 if (!rtex->surface.htile_size)
819 return;
820
821 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
822 rtex->size = rtex->htile_offset + rtex->surface.htile_size;
823 }
824
825 void r600_print_texture_info(struct r600_common_screen *rscreen,
826 struct r600_texture *rtex, struct u_log_context *log)
827 {
828 int i;
829
830 /* Common parameters. */
831 u_log_printf(log, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
832 "blk_h=%u, array_size=%u, last_level=%u, "
833 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
834 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
835 rtex->resource.b.b.depth0, rtex->surface.blk_w,
836 rtex->surface.blk_h,
837 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
838 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
839 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
840
841 u_log_printf(log, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
842 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
843 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
844 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
845 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
846 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
847
848 if (rtex->fmask.size)
849 u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
850 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
851 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
852 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
853 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
854
855 if (rtex->cmask.size)
856 u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
857 "slice_tile_max=%u\n",
858 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
859 rtex->cmask.slice_tile_max);
860
861 if (rtex->htile_offset)
862 u_log_printf(log, " HTile: offset=%"PRIu64", size=%u "
863 "alignment=%u\n",
864 rtex->htile_offset, rtex->surface.htile_size,
865 rtex->surface.htile_alignment);
866
867 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
868 u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
869 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
870 "mode=%u, tiling_index = %u\n",
871 i, rtex->surface.u.legacy.level[i].offset,
872 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
873 u_minify(rtex->resource.b.b.width0, i),
874 u_minify(rtex->resource.b.b.height0, i),
875 u_minify(rtex->resource.b.b.depth0, i),
876 rtex->surface.u.legacy.level[i].nblk_x,
877 rtex->surface.u.legacy.level[i].nblk_y,
878 rtex->surface.u.legacy.level[i].mode,
879 rtex->surface.u.legacy.tiling_index[i]);
880
881 if (rtex->surface.has_stencil) {
882 u_log_printf(log, " StencilLayout: tilesplit=%u\n",
883 rtex->surface.u.legacy.stencil_tile_split);
884 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
885 u_log_printf(log, " StencilLevel[%i]: offset=%"PRIu64", "
886 "slice_size=%"PRIu64", npix_x=%u, "
887 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
888 "mode=%u, tiling_index = %u\n",
889 i, rtex->surface.u.legacy.stencil_level[i].offset,
890 (uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4,
891 u_minify(rtex->resource.b.b.width0, i),
892 u_minify(rtex->resource.b.b.height0, i),
893 u_minify(rtex->resource.b.b.depth0, i),
894 rtex->surface.u.legacy.stencil_level[i].nblk_x,
895 rtex->surface.u.legacy.stencil_level[i].nblk_y,
896 rtex->surface.u.legacy.stencil_level[i].mode,
897 rtex->surface.u.legacy.stencil_tiling_index[i]);
898 }
899 }
900 }
901
902 /* Common processing for r600_texture_create and r600_texture_from_handle */
903 static struct r600_texture *
904 r600_texture_create_object(struct pipe_screen *screen,
905 const struct pipe_resource *base,
906 struct pb_buffer *buf,
907 struct radeon_surf *surface)
908 {
909 struct r600_texture *rtex;
910 struct r600_resource *resource;
911 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
912
913 rtex = CALLOC_STRUCT(r600_texture);
914 if (!rtex)
915 return NULL;
916
917 resource = &rtex->resource;
918 resource->b.b = *base;
919 resource->b.vtbl = &r600_texture_vtbl;
920 pipe_reference_init(&resource->b.b.reference, 1);
921 resource->b.b.screen = screen;
922
923 /* don't include stencil-only formats which we don't support for rendering */
924 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
925
926 rtex->surface = *surface;
927 rtex->size = rtex->surface.surf_size;
928 rtex->db_render_format = base->format;
929
930 /* Tiled depth textures utilize the non-displayable tile order.
931 * This must be done after r600_setup_surface.
932 * Applies to R600-Cayman. */
933 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
934 /* Applies to GCN. */
935 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
936
937 if (rtex->is_depth) {
938 if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
939 R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
940 rscreen->chip_class >= EVERGREEN) {
941 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
942 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
943 } else {
944 if (rtex->resource.b.b.nr_samples <= 1 &&
945 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
946 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT))
947 rtex->can_sample_z = true;
948 }
949
950 if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
951 R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
952 rtex->db_compatible = true;
953
954 if (!(rscreen->debug_flags & DBG_NO_HYPERZ))
955 r600_texture_allocate_htile(rscreen, rtex);
956 }
957 } else {
958 if (base->nr_samples > 1) {
959 if (!buf) {
960 r600_texture_allocate_fmask(rscreen, rtex);
961 r600_texture_allocate_cmask(rscreen, rtex);
962 rtex->cmask_buffer = &rtex->resource;
963 }
964 if (!rtex->fmask.size || !rtex->cmask.size) {
965 FREE(rtex);
966 return NULL;
967 }
968 }
969 }
970
971 /* Now create the backing buffer. */
972 if (!buf) {
973 r600_init_resource_fields(rscreen, resource, rtex->size,
974 rtex->surface.surf_alignment);
975
976 if (!r600_alloc_resource(rscreen, resource)) {
977 FREE(rtex);
978 return NULL;
979 }
980 } else {
981 resource->buf = buf;
982 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf);
983 resource->bo_size = buf->size;
984 resource->bo_alignment = buf->alignment;
985 resource->domains = rscreen->ws->buffer_get_initial_domain(resource->buf);
986 if (resource->domains & RADEON_DOMAIN_VRAM)
987 resource->vram_usage = buf->size;
988 else if (resource->domains & RADEON_DOMAIN_GTT)
989 resource->gart_usage = buf->size;
990 }
991
992 if (rtex->cmask.size) {
993 /* Initialize the cmask to 0xCC (= compressed state). */
994 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
995 rtex->cmask.offset, rtex->cmask.size,
996 0xCCCCCCCC);
997 }
998 if (rtex->htile_offset) {
999 uint32_t clear_value = 0;
1000
1001 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
1002 rtex->htile_offset,
1003 rtex->surface.htile_size,
1004 clear_value);
1005 }
1006
1007 /* Initialize the CMASK base register value. */
1008 rtex->cmask.base_address_reg =
1009 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1010
1011 if (rscreen->debug_flags & DBG_VM) {
1012 fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1013 rtex->resource.gpu_address,
1014 rtex->resource.gpu_address + rtex->resource.buf->size,
1015 base->width0, base->height0, util_num_layers(base, 0), base->last_level+1,
1016 base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
1017 }
1018
1019 if (rscreen->debug_flags & DBG_TEX) {
1020 puts("Texture:");
1021 struct u_log_context log;
1022 u_log_context_init(&log);
1023 r600_print_texture_info(rscreen, rtex, &log);
1024 u_log_new_page_print(&log, stdout);
1025 fflush(stdout);
1026 u_log_context_destroy(&log);
1027 }
1028
1029 return rtex;
1030 }
1031
1032 static enum radeon_surf_mode
1033 r600_choose_tiling(struct r600_common_screen *rscreen,
1034 const struct pipe_resource *templ)
1035 {
1036 const struct util_format_description *desc = util_format_description(templ->format);
1037 bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
1038 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1039 !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
1040
1041 /* MSAA resources must be 2D tiled. */
1042 if (templ->nr_samples > 1)
1043 return RADEON_SURF_MODE_2D;
1044
1045 /* Transfer resources should be linear. */
1046 if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
1047 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1048
1049 /* r600g: force tiling on TEXTURE_2D and TEXTURE_3D compute resources. */
1050 if (rscreen->chip_class >= R600 && rscreen->chip_class <= CAYMAN &&
1051 (templ->bind & PIPE_BIND_COMPUTE_RESOURCE) &&
1052 (templ->target == PIPE_TEXTURE_2D ||
1053 templ->target == PIPE_TEXTURE_3D))
1054 force_tiling = true;
1055
1056 /* Handle common candidates for the linear mode.
1057 * Compressed textures and DB surfaces must always be tiled.
1058 */
1059 if (!force_tiling &&
1060 !is_depth_stencil &&
1061 !util_format_is_compressed(templ->format)) {
1062 if (rscreen->debug_flags & DBG_NO_TILING)
1063 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1064
1065 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats on R600+. */
1066 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED)
1067 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1068
1069 if (templ->bind & PIPE_BIND_LINEAR)
1070 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1071
1072 /* 1D textures should be linear - fixes image operations on 1d */
1073 if (templ->target == PIPE_TEXTURE_1D ||
1074 templ->target == PIPE_TEXTURE_1D_ARRAY)
1075 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1076
1077 /* Textures likely to be mapped often. */
1078 if (templ->usage == PIPE_USAGE_STAGING ||
1079 templ->usage == PIPE_USAGE_STREAM)
1080 return RADEON_SURF_MODE_LINEAR_ALIGNED;
1081 }
1082
1083 /* Make small textures 1D tiled. */
1084 if (templ->width0 <= 16 || templ->height0 <= 16 ||
1085 (rscreen->debug_flags & DBG_NO_2D_TILING))
1086 return RADEON_SURF_MODE_1D;
1087
1088 /* The allocator will switch to 1D if needed. */
1089 return RADEON_SURF_MODE_2D;
1090 }
1091
1092 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
1093 const struct pipe_resource *templ)
1094 {
1095 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1096 struct radeon_surf surface = {0};
1097 bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1098 int r;
1099
1100 r = r600_init_surface(rscreen, &surface, templ,
1101 r600_choose_tiling(rscreen, templ), 0, 0,
1102 false, false, is_flushed_depth);
1103 if (r) {
1104 return NULL;
1105 }
1106
1107 return (struct pipe_resource *)
1108 r600_texture_create_object(screen, templ, NULL, &surface);
1109 }
1110
1111 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
1112 const struct pipe_resource *templ,
1113 struct winsys_handle *whandle,
1114 unsigned usage)
1115 {
1116 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1117 struct pb_buffer *buf = NULL;
1118 enum radeon_surf_mode array_mode;
1119 struct radeon_surf surface = {};
1120 int r;
1121 struct radeon_bo_metadata metadata = {};
1122 struct r600_texture *rtex;
1123 bool is_scanout;
1124
1125 /* Support only 2D textures without mipmaps */
1126 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
1127 templ->depth0 != 1 || templ->last_level != 0)
1128 return NULL;
1129
1130 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1131 rscreen->info.max_alignment);
1132 if (!buf)
1133 return NULL;
1134
1135 rscreen->ws->buffer_get_metadata(buf, &metadata, NULL);
1136 r600_surface_import_metadata(rscreen, &surface, &metadata,
1137 &array_mode, &is_scanout);
1138
1139 r = r600_init_surface(rscreen, &surface, templ, array_mode,
1140 whandle->stride, whandle->offset,
1141 true, is_scanout, false);
1142 if (r) {
1143 return NULL;
1144 }
1145
1146 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1147 if (!rtex)
1148 return NULL;
1149
1150 rtex->resource.b.is_shared = true;
1151 rtex->resource.external_usage = usage;
1152
1153 assert(rtex->surface.tile_swizzle == 0);
1154 return &rtex->resource.b.b;
1155 }
1156
1157 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
1158 struct pipe_resource *texture,
1159 struct r600_texture **staging)
1160 {
1161 struct r600_texture *rtex = (struct r600_texture*)texture;
1162 struct pipe_resource resource;
1163 struct r600_texture **flushed_depth_texture = staging ?
1164 staging : &rtex->flushed_depth_texture;
1165 enum pipe_format pipe_format = texture->format;
1166
1167 if (!staging) {
1168 if (rtex->flushed_depth_texture)
1169 return true; /* it's ready */
1170
1171 if (!rtex->can_sample_z && rtex->can_sample_s) {
1172 switch (pipe_format) {
1173 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1174 /* Save memory by not allocating the S plane. */
1175 pipe_format = PIPE_FORMAT_Z32_FLOAT;
1176 break;
1177 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1178 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1179 /* Save memory bandwidth by not copying the
1180 * stencil part during flush.
1181 *
1182 * This potentially increases memory bandwidth
1183 * if an application uses both Z and S texturing
1184 * simultaneously (a flushed Z24S8 texture
1185 * would be stored compactly), but how often
1186 * does that really happen?
1187 */
1188 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
1189 break;
1190 default:;
1191 }
1192 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1193 assert(util_format_has_stencil(util_format_description(pipe_format)));
1194
1195 /* DB->CB copies to an 8bpp surface don't work. */
1196 pipe_format = PIPE_FORMAT_X24S8_UINT;
1197 }
1198 }
1199
1200 memset(&resource, 0, sizeof(resource));
1201 resource.target = texture->target;
1202 resource.format = pipe_format;
1203 resource.width0 = texture->width0;
1204 resource.height0 = texture->height0;
1205 resource.depth0 = texture->depth0;
1206 resource.array_size = texture->array_size;
1207 resource.last_level = texture->last_level;
1208 resource.nr_samples = texture->nr_samples;
1209 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1210 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
1211 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
1212
1213 if (staging)
1214 resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
1215
1216 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
1217 if (*flushed_depth_texture == NULL) {
1218 R600_ERR("failed to create temporary texture to hold flushed depth\n");
1219 return false;
1220 }
1221
1222 (*flushed_depth_texture)->non_disp_tiling = false;
1223 return true;
1224 }
1225
1226 /**
1227 * Initialize the pipe_resource descriptor to be of the same size as the box,
1228 * which is supposed to hold a subregion of the texture "orig" at the given
1229 * mipmap level.
1230 */
1231 static void r600_init_temp_resource_from_box(struct pipe_resource *res,
1232 struct pipe_resource *orig,
1233 const struct pipe_box *box,
1234 unsigned level, unsigned flags)
1235 {
1236 memset(res, 0, sizeof(*res));
1237 res->format = orig->format;
1238 res->width0 = box->width;
1239 res->height0 = box->height;
1240 res->depth0 = 1;
1241 res->array_size = 1;
1242 res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
1243 res->flags = flags;
1244
1245 /* We must set the correct texture target and dimensions for a 3D box. */
1246 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1247 res->target = PIPE_TEXTURE_2D_ARRAY;
1248 res->array_size = box->depth;
1249 } else {
1250 res->target = PIPE_TEXTURE_2D;
1251 }
1252 }
1253
1254 static bool r600_can_invalidate_texture(struct r600_common_screen *rscreen,
1255 struct r600_texture *rtex,
1256 unsigned transfer_usage,
1257 const struct pipe_box *box)
1258 {
1259 /* r600g doesn't react to dirty_tex_descriptor_counter */
1260 return rscreen->chip_class >= GFX6 &&
1261 !rtex->resource.b.is_shared &&
1262 !(transfer_usage & PIPE_TRANSFER_READ) &&
1263 rtex->resource.b.b.last_level == 0 &&
1264 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1265 box->x, box->y, box->z,
1266 box->width, box->height,
1267 box->depth);
1268 }
1269
1270 static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
1271 struct r600_texture *rtex)
1272 {
1273 struct r600_common_screen *rscreen = rctx->screen;
1274
1275 /* There is no point in discarding depth and tiled buffers. */
1276 assert(!rtex->is_depth);
1277 assert(rtex->surface.is_linear);
1278
1279 /* Reallocate the buffer in the same pipe_resource. */
1280 r600_alloc_resource(rscreen, &rtex->resource);
1281
1282 /* Initialize the CMASK base address (needed even without CMASK). */
1283 rtex->cmask.base_address_reg =
1284 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1285
1286 p_atomic_inc(&rscreen->dirty_tex_counter);
1287
1288 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1289 }
1290
1291 static void *r600_texture_transfer_map(struct pipe_context *ctx,
1292 struct pipe_resource *texture,
1293 unsigned level,
1294 unsigned usage,
1295 const struct pipe_box *box,
1296 struct pipe_transfer **ptransfer)
1297 {
1298 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1299 struct r600_texture *rtex = (struct r600_texture*)texture;
1300 struct r600_transfer *trans;
1301 struct r600_resource *buf;
1302 unsigned offset = 0;
1303 char *map;
1304 bool use_staging_texture = false;
1305
1306 assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
1307 assert(box->width && box->height && box->depth);
1308
1309 /* Depth textures use staging unconditionally. */
1310 if (!rtex->is_depth) {
1311 /* Degrade the tile mode if we get too many transfers on APUs.
1312 * On dGPUs, the staging texture is always faster.
1313 * Only count uploads that are at least 4x4 pixels large.
1314 */
1315 if (!rctx->screen->info.has_dedicated_vram &&
1316 level == 0 &&
1317 box->width >= 4 && box->height >= 4 &&
1318 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1319 bool can_invalidate =
1320 r600_can_invalidate_texture(rctx->screen, rtex,
1321 usage, box);
1322
1323 r600_reallocate_texture_inplace(rctx, rtex,
1324 PIPE_BIND_LINEAR,
1325 can_invalidate);
1326 }
1327
1328 /* Tiled textures need to be converted into a linear texture for CPU
1329 * access. The staging texture is always linear and is placed in GART.
1330 *
1331 * Reading from VRAM or GTT WC is slow, always use the staging
1332 * texture in this case.
1333 *
1334 * Use the staging texture for uploads if the underlying BO
1335 * is busy.
1336 */
1337 if (!rtex->surface.is_linear)
1338 use_staging_texture = true;
1339 else if (usage & PIPE_TRANSFER_READ)
1340 use_staging_texture =
1341 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1342 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1343 /* Write & linear only: */
1344 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1345 RADEON_USAGE_READWRITE) ||
1346 !rctx->ws->buffer_wait(rtex->resource.buf, 0,
1347 RADEON_USAGE_READWRITE)) {
1348 /* It's busy. */
1349 if (r600_can_invalidate_texture(rctx->screen, rtex,
1350 usage, box))
1351 r600_texture_invalidate_storage(rctx, rtex);
1352 else
1353 use_staging_texture = true;
1354 }
1355 }
1356
1357 trans = CALLOC_STRUCT(r600_transfer);
1358 if (!trans)
1359 return NULL;
1360 pipe_resource_reference(&trans->b.b.resource, texture);
1361 trans->b.b.level = level;
1362 trans->b.b.usage = usage;
1363 trans->b.b.box = *box;
1364
1365 if (rtex->is_depth) {
1366 struct r600_texture *staging_depth;
1367
1368 if (rtex->resource.b.b.nr_samples > 1) {
1369 /* MSAA depth buffers need to be converted to single sample buffers.
1370 *
1371 * Mapping MSAA depth buffers can occur if ReadPixels is called
1372 * with a multisample GLX visual.
1373 *
1374 * First downsample the depth buffer to a temporary texture,
1375 * then decompress the temporary one to staging.
1376 *
1377 * Only the region being mapped is transfered.
1378 */
1379 struct pipe_resource resource;
1380
1381 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1382
1383 if (!r600_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
1384 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1385 FREE(trans);
1386 return NULL;
1387 }
1388
1389 if (usage & PIPE_TRANSFER_READ) {
1390 struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
1391 if (!temp) {
1392 R600_ERR("failed to create a temporary depth texture\n");
1393 FREE(trans);
1394 return NULL;
1395 }
1396
1397 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1398 rctx->blit_decompress_depth(ctx, (struct r600_texture*)temp, staging_depth,
1399 0, 0, 0, box->depth, 0, 0);
1400 pipe_resource_reference(&temp, NULL);
1401 }
1402
1403 /* Just get the strides. */
1404 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1405 &trans->b.b.stride,
1406 &trans->b.b.layer_stride);
1407 } else {
1408 /* XXX: only readback the rectangle which is being mapped? */
1409 /* XXX: when discard is true, no need to read back from depth texture */
1410 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
1411 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1412 FREE(trans);
1413 return NULL;
1414 }
1415
1416 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1417 level, level,
1418 box->z, box->z + box->depth - 1,
1419 0, 0);
1420
1421 offset = r600_texture_get_offset(rctx->screen, staging_depth,
1422 level, box,
1423 &trans->b.b.stride,
1424 &trans->b.b.layer_stride);
1425 }
1426
1427 trans->staging = (struct r600_resource*)staging_depth;
1428 buf = trans->staging;
1429 } else if (use_staging_texture) {
1430 struct pipe_resource resource;
1431 struct r600_texture *staging;
1432
1433 r600_init_temp_resource_from_box(&resource, texture, box, level,
1434 R600_RESOURCE_FLAG_TRANSFER);
1435 resource.usage = (usage & PIPE_TRANSFER_READ) ?
1436 PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
1437
1438 /* Create the temporary texture. */
1439 staging = (struct r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
1440 if (!staging) {
1441 R600_ERR("failed to create temporary texture to hold untiled copy\n");
1442 FREE(trans);
1443 return NULL;
1444 }
1445 trans->staging = &staging->resource;
1446
1447 /* Just get the strides. */
1448 r600_texture_get_offset(rctx->screen, staging, 0, NULL,
1449 &trans->b.b.stride,
1450 &trans->b.b.layer_stride);
1451
1452 if (usage & PIPE_TRANSFER_READ)
1453 r600_copy_to_staging_texture(ctx, trans);
1454 else
1455 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
1456
1457 buf = trans->staging;
1458 } else {
1459 /* the resource is mapped directly */
1460 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1461 &trans->b.b.stride,
1462 &trans->b.b.layer_stride);
1463 buf = &rtex->resource;
1464 }
1465
1466 if (!(map = r600_buffer_map_sync_with_rings(rctx, buf, usage))) {
1467 r600_resource_reference(&trans->staging, NULL);
1468 FREE(trans);
1469 return NULL;
1470 }
1471
1472 *ptransfer = &trans->b.b;
1473 return map + offset;
1474 }
1475
1476 static void r600_texture_transfer_unmap(struct pipe_context *ctx,
1477 struct pipe_transfer* transfer)
1478 {
1479 struct r600_common_context *rctx = (struct r600_common_context*)ctx;
1480 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
1481 struct pipe_resource *texture = transfer->resource;
1482 struct r600_texture *rtex = (struct r600_texture*)texture;
1483
1484 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
1485 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1486 ctx->resource_copy_region(ctx, texture, transfer->level,
1487 transfer->box.x, transfer->box.y, transfer->box.z,
1488 &rtransfer->staging->b.b, transfer->level,
1489 &transfer->box);
1490 } else {
1491 r600_copy_from_staging_texture(ctx, rtransfer);
1492 }
1493 }
1494
1495 if (rtransfer->staging) {
1496 rctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
1497 r600_resource_reference(&rtransfer->staging, NULL);
1498 }
1499
1500 /* Heuristic for {upload, draw, upload, draw, ..}:
1501 *
1502 * Flush the gfx IB if we've allocated too much texture storage.
1503 *
1504 * The idea is that we don't want to build IBs that use too much
1505 * memory and put pressure on the kernel memory manager and we also
1506 * want to make temporary and invalidated buffers go idle ASAP to
1507 * decrease the total memory usage or make them reusable. The memory
1508 * usage will be slightly higher than given here because of the buffer
1509 * cache in the winsys.
1510 *
1511 * The result is that the kernel memory manager is never a bottleneck.
1512 */
1513 if (rctx->num_alloc_tex_transfer_bytes > rctx->screen->info.gart_size / 4) {
1514 rctx->gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
1515 rctx->num_alloc_tex_transfer_bytes = 0;
1516 }
1517
1518 pipe_resource_reference(&transfer->resource, NULL);
1519 FREE(transfer);
1520 }
1521
1522 static const struct u_resource_vtbl r600_texture_vtbl =
1523 {
1524 NULL, /* get_handle */
1525 r600_texture_destroy, /* resource_destroy */
1526 r600_texture_transfer_map, /* transfer_map */
1527 u_default_transfer_flush_region, /* transfer_flush_region */
1528 r600_texture_transfer_unmap, /* transfer_unmap */
1529 };
1530
1531 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
1532 struct pipe_resource *texture,
1533 const struct pipe_surface *templ,
1534 unsigned width0, unsigned height0,
1535 unsigned width, unsigned height)
1536 {
1537 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
1538
1539 if (!surface)
1540 return NULL;
1541
1542 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1543 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1544
1545 pipe_reference_init(&surface->base.reference, 1);
1546 pipe_resource_reference(&surface->base.texture, texture);
1547 surface->base.context = pipe;
1548 surface->base.format = templ->format;
1549 surface->base.width = width;
1550 surface->base.height = height;
1551 surface->base.u = templ->u;
1552
1553 surface->width0 = width0;
1554 surface->height0 = height0;
1555
1556 return &surface->base;
1557 }
1558
1559 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
1560 struct pipe_resource *tex,
1561 const struct pipe_surface *templ)
1562 {
1563 unsigned level = templ->u.tex.level;
1564 unsigned width = u_minify(tex->width0, level);
1565 unsigned height = u_minify(tex->height0, level);
1566 unsigned width0 = tex->width0;
1567 unsigned height0 = tex->height0;
1568
1569 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
1570 const struct util_format_description *tex_desc
1571 = util_format_description(tex->format);
1572 const struct util_format_description *templ_desc
1573 = util_format_description(templ->format);
1574
1575 assert(tex_desc->block.bits == templ_desc->block.bits);
1576
1577 /* Adjust size of surface if and only if the block width or
1578 * height is changed. */
1579 if (tex_desc->block.width != templ_desc->block.width ||
1580 tex_desc->block.height != templ_desc->block.height) {
1581 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
1582 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
1583
1584 width = nblks_x * templ_desc->block.width;
1585 height = nblks_y * templ_desc->block.height;
1586
1587 width0 = util_format_get_nblocksx(tex->format, width0);
1588 height0 = util_format_get_nblocksy(tex->format, height0);
1589 }
1590 }
1591
1592 return r600_create_surface_custom(pipe, tex, templ,
1593 width0, height0,
1594 width, height);
1595 }
1596
1597 static void r600_surface_destroy(struct pipe_context *pipe,
1598 struct pipe_surface *surface)
1599 {
1600 struct r600_surface *surf = (struct r600_surface*)surface;
1601 r600_resource_reference(&surf->cb_buffer_fmask, NULL);
1602 r600_resource_reference(&surf->cb_buffer_cmask, NULL);
1603 pipe_resource_reference(&surface->texture, NULL);
1604 FREE(surface);
1605 }
1606
1607 static void r600_clear_texture(struct pipe_context *pipe,
1608 struct pipe_resource *tex,
1609 unsigned level,
1610 const struct pipe_box *box,
1611 const void *data)
1612 {
1613 struct pipe_screen *screen = pipe->screen;
1614 struct r600_texture *rtex = (struct r600_texture*)tex;
1615 struct pipe_surface tmpl = {{0}};
1616 struct pipe_surface *sf;
1617
1618 tmpl.format = tex->format;
1619 tmpl.u.tex.first_layer = box->z;
1620 tmpl.u.tex.last_layer = box->z + box->depth - 1;
1621 tmpl.u.tex.level = level;
1622 sf = pipe->create_surface(pipe, tex, &tmpl);
1623 if (!sf)
1624 return;
1625
1626 if (rtex->is_depth) {
1627 unsigned clear;
1628 float depth;
1629 uint8_t stencil = 0;
1630
1631 /* Depth is always present. */
1632 clear = PIPE_CLEAR_DEPTH;
1633 util_format_unpack_z_float(tex->format, &depth, data, 1);
1634
1635 if (rtex->surface.has_stencil) {
1636 clear |= PIPE_CLEAR_STENCIL;
1637 util_format_unpack_s_8uint(tex->format, &stencil, data, 1);
1638 }
1639
1640 pipe->clear_depth_stencil(pipe, sf, clear, depth, stencil,
1641 box->x, box->y,
1642 box->width, box->height, false);
1643 } else {
1644 union pipe_color_union color;
1645
1646 util_format_unpack_rgba(tex->format, color.ui, data, 1);
1647
1648 if (screen->is_format_supported(screen, tex->format,
1649 tex->target, 0, 0,
1650 PIPE_BIND_RENDER_TARGET)) {
1651 pipe->clear_render_target(pipe, sf, &color,
1652 box->x, box->y,
1653 box->width, box->height, false);
1654 } else {
1655 /* Software fallback - just for R9G9B9E5_FLOAT */
1656 util_clear_render_target(pipe, sf, &color,
1657 box->x, box->y,
1658 box->width, box->height);
1659 }
1660 }
1661 pipe_surface_reference(&sf, NULL);
1662 }
1663
1664 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
1665 {
1666 const struct util_format_description *desc = util_format_description(format);
1667
1668 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1669
1670 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1671 return V_0280A0_SWAP_STD;
1672
1673 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1674 return ~0U;
1675
1676 switch (desc->nr_channels) {
1677 case 1:
1678 if (HAS_SWIZZLE(0,X))
1679 return V_0280A0_SWAP_STD; /* X___ */
1680 else if (HAS_SWIZZLE(3,X))
1681 return V_0280A0_SWAP_ALT_REV; /* ___X */
1682 break;
1683 case 2:
1684 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
1685 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
1686 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
1687 return V_0280A0_SWAP_STD; /* XY__ */
1688 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
1689 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
1690 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
1691 /* YX__ */
1692 return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
1693 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
1694 return V_0280A0_SWAP_ALT; /* X__Y */
1695 else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
1696 return V_0280A0_SWAP_ALT_REV; /* Y__X */
1697 break;
1698 case 3:
1699 if (HAS_SWIZZLE(0,X))
1700 return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
1701 else if (HAS_SWIZZLE(0,Z))
1702 return V_0280A0_SWAP_STD_REV; /* ZYX */
1703 break;
1704 case 4:
1705 /* check the middle channels, the 1st and 4th channel can be NONE */
1706 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
1707 return V_0280A0_SWAP_STD; /* XYZW */
1708 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
1709 return V_0280A0_SWAP_STD_REV; /* WZYX */
1710 } else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
1711 return V_0280A0_SWAP_ALT; /* ZYXW */
1712 } else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
1713 /* YZWX */
1714 if (desc->is_array)
1715 return V_0280A0_SWAP_ALT_REV;
1716 else
1717 return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
1718 }
1719 break;
1720 }
1721 return ~0U;
1722 }
1723
1724 /* FAST COLOR CLEAR */
1725
1726 static void evergreen_set_clear_color(struct r600_texture *rtex,
1727 enum pipe_format surface_format,
1728 const union pipe_color_union *color)
1729 {
1730 union util_color uc;
1731
1732 memset(&uc, 0, sizeof(uc));
1733
1734 if (rtex->surface.bpe == 16) {
1735 /* DCC fast clear only:
1736 * CLEAR_WORD0 = R = G = B
1737 * CLEAR_WORD1 = A
1738 */
1739 assert(color->ui[0] == color->ui[1] &&
1740 color->ui[0] == color->ui[2]);
1741 uc.ui[0] = color->ui[0];
1742 uc.ui[1] = color->ui[3];
1743 } else {
1744 util_pack_color_union(surface_format, &uc, color);
1745 }
1746
1747 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1748 }
1749
1750 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
1751 struct pipe_framebuffer_state *fb,
1752 struct r600_atom *fb_state,
1753 unsigned *buffers, ubyte *dirty_cbufs,
1754 const union pipe_color_union *color)
1755 {
1756 int i;
1757
1758 /* This function is broken in BE, so just disable this path for now */
1759 #if UTIL_ARCH_BIG_ENDIAN
1760 return;
1761 #endif
1762
1763 if (rctx->render_cond)
1764 return;
1765
1766 for (i = 0; i < fb->nr_cbufs; i++) {
1767 struct r600_texture *tex;
1768 unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
1769
1770 if (!fb->cbufs[i])
1771 continue;
1772
1773 /* if this colorbuffer is not being cleared */
1774 if (!(*buffers & clear_bit))
1775 continue;
1776
1777 tex = (struct r600_texture *)fb->cbufs[i]->texture;
1778
1779 /* the clear is allowed if all layers are bound */
1780 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
1781 fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->resource.b.b, 0)) {
1782 continue;
1783 }
1784
1785 /* cannot clear mipmapped textures */
1786 if (fb->cbufs[i]->texture->last_level != 0) {
1787 continue;
1788 }
1789
1790 /* only supported on tiled surfaces */
1791 if (tex->surface.is_linear) {
1792 continue;
1793 }
1794
1795 /* shared textures can't use fast clear without an explicit flush,
1796 * because there is no way to communicate the clear color among
1797 * all clients
1798 */
1799 if (tex->resource.b.is_shared &&
1800 !(tex->resource.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
1801 continue;
1802
1803 /* Use a slow clear for small surfaces where the cost of
1804 * the eliminate pass can be higher than the benefit of fast
1805 * clear. AMDGPU-pro does this, but the numbers may differ.
1806 *
1807 * This helps on both dGPUs and APUs, even small ones.
1808 */
1809 if (tex->resource.b.b.nr_samples <= 1 &&
1810 tex->resource.b.b.width0 * tex->resource.b.b.height0 <= 300 * 300)
1811 continue;
1812
1813 {
1814 /* 128-bit formats are unusupported */
1815 if (tex->surface.bpe > 8) {
1816 continue;
1817 }
1818
1819 /* ensure CMASK is enabled */
1820 r600_texture_alloc_cmask_separate(rctx->screen, tex);
1821 if (tex->cmask.size == 0) {
1822 continue;
1823 }
1824
1825 /* Do the fast clear. */
1826 rctx->clear_buffer(&rctx->b, &tex->cmask_buffer->b.b,
1827 tex->cmask.offset, tex->cmask.size, 0,
1828 R600_COHERENCY_CB_META);
1829
1830 bool need_compressed_update = !tex->dirty_level_mask;
1831
1832 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;
1833
1834 if (need_compressed_update)
1835 p_atomic_inc(&rctx->screen->compressed_colortex_counter);
1836 }
1837
1838 evergreen_set_clear_color(tex, fb->cbufs[i]->format, color);
1839
1840 if (dirty_cbufs)
1841 *dirty_cbufs |= 1 << i;
1842 rctx->set_atom_dirty(rctx, fb_state, true);
1843 *buffers &= ~clear_bit;
1844 }
1845 }
1846
1847 static struct pipe_memory_object *
1848 r600_memobj_from_handle(struct pipe_screen *screen,
1849 struct winsys_handle *whandle,
1850 bool dedicated)
1851 {
1852 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1853 struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
1854 struct pb_buffer *buf = NULL;
1855
1856 if (!memobj)
1857 return NULL;
1858
1859 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
1860 rscreen->info.max_alignment);
1861 if (!buf) {
1862 free(memobj);
1863 return NULL;
1864 }
1865
1866 memobj->b.dedicated = dedicated;
1867 memobj->buf = buf;
1868 memobj->stride = whandle->stride;
1869 memobj->offset = whandle->offset;
1870
1871 return (struct pipe_memory_object *)memobj;
1872
1873 }
1874
1875 static void
1876 r600_memobj_destroy(struct pipe_screen *screen,
1877 struct pipe_memory_object *_memobj)
1878 {
1879 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1880
1881 pb_reference(&memobj->buf, NULL);
1882 free(memobj);
1883 }
1884
1885 static struct pipe_resource *
1886 r600_texture_from_memobj(struct pipe_screen *screen,
1887 const struct pipe_resource *templ,
1888 struct pipe_memory_object *_memobj,
1889 uint64_t offset)
1890 {
1891 int r;
1892 struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
1893 struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
1894 struct r600_texture *rtex;
1895 struct radeon_surf surface = {};
1896 struct radeon_bo_metadata metadata = {};
1897 enum radeon_surf_mode array_mode;
1898 bool is_scanout;
1899 struct pb_buffer *buf = NULL;
1900
1901 if (memobj->b.dedicated) {
1902 rscreen->ws->buffer_get_metadata(memobj->buf, &metadata, NULL);
1903 r600_surface_import_metadata(rscreen, &surface, &metadata,
1904 &array_mode, &is_scanout);
1905 } else {
1906 /**
1907 * The bo metadata is unset for un-dedicated images. So we fall
1908 * back to linear. See answer to question 5 of the
1909 * VK_KHX_external_memory spec for some details.
1910 *
1911 * It is possible that this case isn't going to work if the
1912 * surface pitch isn't correctly aligned by default.
1913 *
1914 * In order to support it correctly we require multi-image
1915 * metadata to be syncrhonized between radv and radeonsi. The
1916 * semantics of associating multiple image metadata to a memory
1917 * object on the vulkan export side are not concretely defined
1918 * either.
1919 *
1920 * All the use cases we are aware of at the moment for memory
1921 * objects use dedicated allocations. So lets keep the initial
1922 * implementation simple.
1923 *
1924 * A possible alternative is to attempt to reconstruct the
1925 * tiling information when the TexParameter TEXTURE_TILING_EXT
1926 * is set.
1927 */
1928 array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1929 is_scanout = false;
1930
1931 }
1932
1933 r = r600_init_surface(rscreen, &surface, templ,
1934 array_mode, memobj->stride,
1935 offset, true, is_scanout,
1936 false);
1937 if (r)
1938 return NULL;
1939
1940 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
1941 if (!rtex)
1942 return NULL;
1943
1944 /* r600_texture_create_object doesn't increment refcount of
1945 * memobj->buf, so increment it here.
1946 */
1947 pb_reference(&buf, memobj->buf);
1948
1949 rtex->resource.b.is_shared = true;
1950 rtex->resource.external_usage = PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE;
1951
1952 return &rtex->resource.b.b;
1953 }
1954
1955 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen)
1956 {
1957 rscreen->b.resource_from_handle = r600_texture_from_handle;
1958 rscreen->b.resource_get_handle = r600_texture_get_handle;
1959 rscreen->b.resource_get_info = r600_texture_get_info;
1960 rscreen->b.resource_from_memobj = r600_texture_from_memobj;
1961 rscreen->b.memobj_create_from_handle = r600_memobj_from_handle;
1962 rscreen->b.memobj_destroy = r600_memobj_destroy;
1963 }
1964
1965 void r600_init_context_texture_functions(struct r600_common_context *rctx)
1966 {
1967 rctx->b.create_surface = r600_create_surface;
1968 rctx->b.surface_destroy = r600_surface_destroy;
1969 rctx->b.clear_texture = r600_clear_texture;
1970 }