src/gallium/drivers/r600/radeon.h

   1 /*
   2  * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * This file is free software; you can redistribute it and/or modify
   5  * it under the terms of version 2 of the GNU General Public License
   6  * as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software Foundation,
  15  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  16  */
  17 #ifndef RADEON_H
  18 #define RADEON_H
  19
  20 #define RADEON_CTX_MAX_PM4      (64 * 1024 / 4)
  21
  22 #include <stdint.h>
  23
  24 typedef uint64_t                u64;
  25 typedef uint32_t                u32;
  26 typedef uint16_t                u16;
  27 typedef uint8_t                 u8;
  28
  29 struct radeon;
  30
  31 enum radeon_family {
  32         CHIP_UNKNOWN,
  33         CHIP_R100,
  34         CHIP_RV100,
  35         CHIP_RS100,
  36         CHIP_RV200,
  37         CHIP_RS200,
  38         CHIP_R200,
  39         CHIP_RV250,
  40         CHIP_RS300,
  41         CHIP_RV280,
  42         CHIP_R300,
  43         CHIP_R350,
  44         CHIP_RV350,
  45         CHIP_RV380,
  46         CHIP_R420,
  47         CHIP_R423,
  48         CHIP_RV410,
  49         CHIP_RS400,
  50         CHIP_RS480,
  51         CHIP_RS600,
  52         CHIP_RS690,
  53         CHIP_RS740,
  54         CHIP_RV515,
  55         CHIP_R520,
  56         CHIP_RV530,
  57         CHIP_RV560,
  58         CHIP_RV570,
  59         CHIP_R580,
  60         CHIP_R600,
  61         CHIP_RV610,
  62         CHIP_RV630,
  63         CHIP_RV670,
  64         CHIP_RV620,
  65         CHIP_RV635,
  66         CHIP_RS780,
  67         CHIP_RS880,
  68         CHIP_RV770,
  69         CHIP_RV730,
  70         CHIP_RV710,
  71         CHIP_RV740,
  72         CHIP_CEDAR,
  73         CHIP_REDWOOD,
  74         CHIP_JUNIPER,
  75         CHIP_CYPRESS,
  76         CHIP_HEMLOCK,
  77         CHIP_LAST,
  78 };
  79
  80 enum {
  81         R600_SHADER_PS = 1,
  82         R600_SHADER_VS,
  83         R600_SHADER_GS,
  84         R600_SHADER_FS,
  85         R600_SHADER_MAX = R600_SHADER_FS,
  86 };
  87
  88 enum radeon_family radeon_get_family(struct radeon *rw);
  89
  90 /*
  91  * radeon object functions
  92  */
  93 struct radeon_bo {
  94         unsigned                        refcount;
  95         unsigned                        handle;
  96         unsigned                        size;
  97         unsigned                        alignment;
  98         unsigned                        map_count;
  99         void                            *data;
 100 };
 101 struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
 102                         unsigned size, unsigned alignment, void *ptr);
 103 int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
 104 void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
 105 struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo);
 106 struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo);
 107 int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
 108
 109 struct radeon_stype_info;
 110 /*
 111  * states functions
 112  */
 113 struct radeon_state {
 114         struct radeon                   *radeon;
 115         unsigned                        refcount;
 116         struct radeon_stype_info        *stype;
 117         unsigned                        state_id;
 118         unsigned                        id;
 119         unsigned                        shader_index;
 120         unsigned                        nstates;
 121         u32                             states[64];
 122         unsigned                        npm4;
 123         unsigned                        cpm4;
 124         u32                             pm4_crc;
 125         u32                             pm4[128];
 126         unsigned                        nbo;
 127         struct radeon_bo                *bo[4];
 128         unsigned                        nreloc;
 129         unsigned                        reloc_pm4_id[8];
 130         unsigned                        reloc_bo_id[8];
 131         u32                             placement[8];
 132         unsigned                        bo_dirty[4];
 133 };
 134
 135 int radeon_state_init(struct radeon_state *rstate, struct radeon *radeon, u32 type, u32 id, u32 shader_class);
 136 void radeon_state_fini(struct radeon_state *state);
 137 int radeon_state_pm4(struct radeon_state *state);
 138 int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
 139
 140 /*
 141  * draw functions
 142  */
 143 struct radeon_draw {
 144         struct radeon                   *radeon;
 145         struct radeon_state             **state;
 146 };
 147
 148 int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon);
 149 void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state);
 150 void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state);
 151
 152 /*
 153  * radeon context functions
 154  */
 155 #pragma pack(1)
 156 struct radeon_cs_reloc {
 157         uint32_t        handle;
 158         uint32_t        read_domain;
 159         uint32_t        write_domain;
 160         uint32_t        flags;
 161 };
 162 #pragma pack()
 163
 164 struct radeon_ctx {
 165         struct radeon                   *radeon;
 166         u32                             *pm4;
 167         int                             cdwords;
 168         int                             ndwords;
 169         unsigned                        nreloc;
 170         struct radeon_cs_reloc          *reloc;
 171         unsigned                        nbo;
 172         struct radeon_bo                **bo;
 173 };
 174
 175 int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon);
 176 void radeon_ctx_fini(struct radeon_ctx *ctx);
 177 void radeon_ctx_clear(struct radeon_ctx *ctx);
 178 int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
 179 int radeon_ctx_submit(struct radeon_ctx *ctx);
 180 void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
 181 int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
 182
 183 /*
 184  * R600/R700
 185  */
 186
 187 enum r600_stype {
 188         R600_STATE_CONFIG,
 189         R600_STATE_CB_CNTL,
 190         R600_STATE_RASTERIZER,
 191         R600_STATE_VIEWPORT,
 192         R600_STATE_SCISSOR,
 193         R600_STATE_BLEND,
 194         R600_STATE_DSA,
 195         R600_STATE_SHADER,          /* has PS,VS,GS,FS variants */
 196         R600_STATE_CONSTANT,        /* has PS,VS,GS,FS variants */
 197         R600_STATE_RESOURCE,        /* has PS,VS,GS,FS variants */
 198         R600_STATE_SAMPLER,         /* has PS,VS,GS,FS variants */
 199         R600_STATE_SAMPLER_BORDER,  /* has PS,VS,GS,FS variants */
 200         R600_STATE_CB0,
 201         R600_STATE_CB1,
 202         R600_STATE_CB2,
 203         R600_STATE_CB3,
 204         R600_STATE_CB4,
 205         R600_STATE_CB5,
 206         R600_STATE_CB6,
 207         R600_STATE_CB7,
 208         R600_STATE_DB,
 209         R600_STATE_QUERY_BEGIN,
 210         R600_STATE_QUERY_END,
 211         R600_STATE_UCP,
 212         R600_STATE_VGT,
 213         R600_STATE_DRAW,
 214 };
 215
 216 /* R600_CONFIG */
 217 #define R600_CONFIG__SQ_CONFIG                  0
 218 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1                     1
 219 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2                     2
 220 #define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT                    3
 221 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1                   4
 222 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2                   5
 223 #define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ                       6
 224 #define R600_CONFIG__TA_CNTL_AUX                        7
 225 #define R600_CONFIG__VC_ENHANCE                 8
 226 #define R600_CONFIG__DB_DEBUG                   9
 227 #define R600_CONFIG__DB_WATERMARKS                      10
 228 #define R600_CONFIG__SX_MISC                    11
 229 #define R600_CONFIG__SPI_THREAD_GROUPING                        12
 230 #define R600_CONFIG__CB_SHADER_CONTROL                  13
 231 #define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE                      14
 232 #define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE                      15
 233 #define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE                     16
 234 #define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE                     17
 235 #define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE                     18
 236 #define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE                     19
 237 #define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE                      20
 238 #define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE                     21
 239 #define R600_CONFIG__SQ_GS_VERT_ITEMSIZE                        22
 240 #define R600_CONFIG__VGT_OUTPUT_PATH_CNTL                       23
 241 #define R600_CONFIG__VGT_HOS_CNTL                       24
 242 #define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL                     25
 243 #define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL                     26
 244 #define R600_CONFIG__VGT_HOS_REUSE_DEPTH                        27
 245 #define R600_CONFIG__VGT_GROUP_PRIM_TYPE                        28
 246 #define R600_CONFIG__VGT_GROUP_FIRST_DECR                       29
 247 #define R600_CONFIG__VGT_GROUP_DECR                     30
 248 #define R600_CONFIG__VGT_GROUP_VECT_0_CNTL                      31
 249 #define R600_CONFIG__VGT_GROUP_VECT_1_CNTL                      32
 250 #define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL                  33
 251 #define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL                  34
 252 #define R600_CONFIG__VGT_GS_MODE                        35
 253 #define R600_CONFIG__PA_SC_MODE_CNTL                    36
 254 #define R600_CONFIG__VGT_STRMOUT_EN                     37
 255 #define R600_CONFIG__VGT_REUSE_OFF                      38
 256 #define R600_CONFIG__VGT_VTX_CNT_EN                     39
 257 #define R600_CONFIG__VGT_STRMOUT_BUFFER_EN                      40
 258 #define R600_CONFIG_SIZE                                41
 259 #define R600_CONFIG_PM4                         128
 260 /* R600_CB_CNTL */
 261 #define R600_CB_CNTL__CB_CLEAR_RED                      0
 262 #define R600_CB_CNTL__CB_CLEAR_GREEN                    1
 263 #define R600_CB_CNTL__CB_CLEAR_BLUE                     2
 264 #define R600_CB_CNTL__CB_CLEAR_ALPHA                    3
 265 #define R600_CB_CNTL__CB_SHADER_MASK                    4
 266 #define R600_CB_CNTL__CB_TARGET_MASK                    5
 267 #define R600_CB_CNTL__CB_FOG_RED                        6
 268 #define R600_CB_CNTL__CB_FOG_GREEN                      7
 269 #define R600_CB_CNTL__CB_FOG_BLUE                       8
 270 #define R600_CB_CNTL__CB_COLOR_CONTROL                  9
 271 #define R600_CB_CNTL__PA_SC_AA_CONFIG                   10
 272 #define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX                 11
 273 #define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX                  12
 274 #define R600_CB_CNTL__CB_CLRCMP_CONTROL                 13
 275 #define R600_CB_CNTL__CB_CLRCMP_SRC                     14
 276 #define R600_CB_CNTL__CB_CLRCMP_DST                     15
 277 #define R600_CB_CNTL__CB_CLRCMP_MSK                     16
 278 #define R600_CB_CNTL__PA_SC_AA_MASK                     17
 279 #define R600_CB_CNTL_SIZE                               18
 280 #define R600_CB_CNTL_PM4                                128
 281 /* R600_RASTERIZER */
 282 #define R600_RASTERIZER__SPI_INTERP_CONTROL_0                   0
 283 #define R600_RASTERIZER__PA_CL_CLIP_CNTL                        1
 284 #define R600_RASTERIZER__PA_SU_SC_MODE_CNTL                     2
 285 #define R600_RASTERIZER__PA_CL_VS_OUT_CNTL                      3
 286 #define R600_RASTERIZER__PA_CL_NANINF_CNTL                      4
 287 #define R600_RASTERIZER__PA_SU_POINT_SIZE                       5
 288 #define R600_RASTERIZER__PA_SU_POINT_MINMAX                     6
 289 #define R600_RASTERIZER__PA_SU_LINE_CNTL                        7
 290 #define R600_RASTERIZER__PA_SC_LINE_STIPPLE                     8
 291 #define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL                    9
 292 #define R600_RASTERIZER__PA_SC_LINE_CNTL                        10
 293 #define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ                 11
 294 #define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ                 12
 295 #define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ                 13
 296 #define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ                 14
 297 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL                  15
 298 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP                        16
 299 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE                  17
 300 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET                 18
 301 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE                   19
 302 #define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET                  20
 303 #define R600_RASTERIZER_SIZE                            21
 304 #define R600_RASTERIZER_PM4                             128
 305 /* R600_VIEWPORT */
 306 #define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0                       0
 307 #define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0                       1
 308 #define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0                     2
 309 #define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0                     3
 310 #define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0                     4
 311 #define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0                    5
 312 #define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0                    6
 313 #define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0                    7
 314 #define R600_VIEWPORT__PA_CL_VTE_CNTL                   8
 315 #define R600_VIEWPORT_SIZE                              9
 316 #define R600_VIEWPORT_PM4                               128
 317 /* R600_SCISSOR */
 318 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL                   0
 319 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR                   1
 320 #define R600_SCISSOR__PA_SC_WINDOW_OFFSET                       2
 321 #define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL                   3
 322 #define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR                   4
 323 #define R600_SCISSOR__PA_SC_CLIPRECT_RULE                       5
 324 #define R600_SCISSOR__PA_SC_CLIPRECT_0_TL                       6
 325 #define R600_SCISSOR__PA_SC_CLIPRECT_0_BR                       7
 326 #define R600_SCISSOR__PA_SC_CLIPRECT_1_TL                       8
 327 #define R600_SCISSOR__PA_SC_CLIPRECT_1_BR                       9
 328 #define R600_SCISSOR__PA_SC_CLIPRECT_2_TL                       10
 329 #define R600_SCISSOR__PA_SC_CLIPRECT_2_BR                       11
 330 #define R600_SCISSOR__PA_SC_CLIPRECT_3_TL                       12
 331 #define R600_SCISSOR__PA_SC_CLIPRECT_3_BR                       13
 332 #define R600_SCISSOR__PA_SC_EDGERULE                    14
 333 #define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL                  15
 334 #define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR                  16
 335 #define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL                  17
 336 #define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR                  18
 337 #define R600_SCISSOR_SIZE                               19
 338 #define R600_SCISSOR_PM4                                128
 339 /* R600_BLEND */
 340 #define R600_BLEND__CB_BLEND_RED                        0
 341 #define R600_BLEND__CB_BLEND_GREEN                      1
 342 #define R600_BLEND__CB_BLEND_BLUE                       2
 343 #define R600_BLEND__CB_BLEND_ALPHA                      3
 344 #define R600_BLEND__CB_BLEND0_CONTROL                   4
 345 #define R600_BLEND__CB_BLEND1_CONTROL                   5
 346 #define R600_BLEND__CB_BLEND2_CONTROL                   6
 347 #define R600_BLEND__CB_BLEND3_CONTROL                   7
 348 #define R600_BLEND__CB_BLEND4_CONTROL                   8
 349 #define R600_BLEND__CB_BLEND5_CONTROL                   9
 350 #define R600_BLEND__CB_BLEND6_CONTROL                   10
 351 #define R600_BLEND__CB_BLEND7_CONTROL                   11
 352 #define R600_BLEND__CB_BLEND_CONTROL                    12
 353 #define R600_BLEND_SIZE                         13
 354 #define R600_BLEND_PM4                          128
 355 /* R600_DSA */
 356 #define R600_DSA__DB_STENCIL_CLEAR                      0
 357 #define R600_DSA__DB_DEPTH_CLEAR                        1
 358 #define R600_DSA__SX_ALPHA_TEST_CONTROL                 2
 359 #define R600_DSA__DB_STENCILREFMASK                     3
 360 #define R600_DSA__DB_STENCILREFMASK_BF                  4
 361 #define R600_DSA__SX_ALPHA_REF                  5
 362 #define R600_DSA__SPI_FOG_FUNC_SCALE                    6
 363 #define R600_DSA__SPI_FOG_FUNC_BIAS                     7
 364 #define R600_DSA__SPI_FOG_CNTL                  8
 365 #define R600_DSA__DB_DEPTH_CONTROL                      9
 366 #define R600_DSA__DB_SHADER_CONTROL                     10
 367 #define R600_DSA__DB_RENDER_CONTROL                     11
 368 #define R600_DSA__DB_RENDER_OVERRIDE                    12
 369 #define R600_DSA__DB_SRESULTS_COMPARE_STATE1                    13
 370 #define R600_DSA__DB_PRELOAD_CONTROL                    14
 371 #define R600_DSA__DB_ALPHA_TO_MASK                      15
 372 #define R600_DSA_SIZE                           16
 373 #define R600_DSA_PM4                            128
 374 /* R600_VS_SHADER */
 375 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_0                       0
 376 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_1                       1
 377 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_2                       2
 378 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_3                       3
 379 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_4                       4
 380 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_5                       5
 381 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_6                       6
 382 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_7                       7
 383 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_8                       8
 384 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_9                       9
 385 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_10                      10
 386 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_11                      11
 387 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_12                      12
 388 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_13                      13
 389 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_14                      14
 390 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_15                      15
 391 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_16                      16
 392 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_17                      17
 393 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_18                      18
 394 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_19                      19
 395 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_20                      20
 396 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_21                      21
 397 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_22                      22
 398 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_23                      23
 399 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_24                      24
 400 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_25                      25
 401 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_26                      26
 402 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_27                      27
 403 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_28                      28
 404 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_29                      29
 405 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_30                      30
 406 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_31                      31
 407 #define R600_VS_SHADER__SPI_VS_OUT_ID_0                 32
 408 #define R600_VS_SHADER__SPI_VS_OUT_ID_1                 33
 409 #define R600_VS_SHADER__SPI_VS_OUT_ID_2                 34
 410 #define R600_VS_SHADER__SPI_VS_OUT_ID_3                 35
 411 #define R600_VS_SHADER__SPI_VS_OUT_ID_4                 36
 412 #define R600_VS_SHADER__SPI_VS_OUT_ID_5                 37
 413 #define R600_VS_SHADER__SPI_VS_OUT_ID_6                 38
 414 #define R600_VS_SHADER__SPI_VS_OUT_ID_7                 39
 415 #define R600_VS_SHADER__SPI_VS_OUT_ID_8                 40
 416 #define R600_VS_SHADER__SPI_VS_OUT_ID_9                 41
 417 #define R600_VS_SHADER__SPI_VS_OUT_CONFIG                       42
 418 #define R600_VS_SHADER__SQ_PGM_START_VS                 43
 419 #define R600_VS_SHADER__SQ_PGM_RESOURCES_VS                     44
 420 #define R600_VS_SHADER__SQ_PGM_START_FS                 45
 421 #define R600_VS_SHADER__SQ_PGM_RESOURCES_FS                     46
 422 #define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS                     47
 423 #define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS                     48
 424 #define R600_VS_SHADER_SIZE                             49
 425 #define R600_VS_SHADER_PM4                              128
 426 /* R600_PS_SHADER */
 427 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0                     0
 428 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1                     1
 429 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2                     2
 430 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3                     3
 431 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4                     4
 432 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5                     5
 433 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6                     6
 434 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7                     7
 435 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8                     8
 436 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9                     9
 437 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10                    10
 438 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11                    11
 439 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12                    12
 440 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13                    13
 441 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14                    14
 442 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15                    15
 443 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16                    16
 444 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17                    17
 445 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18                    18
 446 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19                    19
 447 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20                    20
 448 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21                    21
 449 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22                    22
 450 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23                    23
 451 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24                    24
 452 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25                    25
 453 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26                    26
 454 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27                    27
 455 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28                    28
 456 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29                    29
 457 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30                    30
 458 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31                    31
 459 #define R600_PS_SHADER__SPI_PS_IN_CONTROL_0                     32
 460 #define R600_PS_SHADER__SPI_PS_IN_CONTROL_1                     33
 461 #define R600_PS_SHADER__SPI_INPUT_Z                     34
 462 #define R600_PS_SHADER__SQ_PGM_START_PS                 35
 463 #define R600_PS_SHADER__SQ_PGM_RESOURCES_PS                     36
 464 #define R600_PS_SHADER__SQ_PGM_EXPORTS_PS                       37
 465 #define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS                     38
 466 #define R600_PS_SHADER_SIZE                             39
 467 #define R600_PS_SHADER_PM4                              128
 468 /* R600_PS_CONSTANT */
 469 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0                    0
 470 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0                    1
 471 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0                    2
 472 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0                    3
 473 #define R600_PS_CONSTANT_SIZE                           4
 474 #define R600_PS_CONSTANT_PM4                            128
 475 /* R600_VS_CONSTANT */
 476 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256                  0
 477 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256                  1
 478 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256                  2
 479 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256                  3
 480 #define R600_VS_CONSTANT_SIZE                           4
 481 #define R600_VS_CONSTANT_PM4                            128
 482 /* R600_PS_RESOURCE */
 483 #define R600_PS_RESOURCE__RESOURCE0_WORD0                       0
 484 #define R600_PS_RESOURCE__RESOURCE0_WORD1                       1
 485 #define R600_PS_RESOURCE__RESOURCE0_WORD2                       2
 486 #define R600_PS_RESOURCE__RESOURCE0_WORD3                       3
 487 #define R600_PS_RESOURCE__RESOURCE0_WORD4                       4
 488 #define R600_PS_RESOURCE__RESOURCE0_WORD5                       5
 489 #define R600_PS_RESOURCE__RESOURCE0_WORD6                       6
 490 #define R600_PS_RESOURCE_SIZE                           7
 491 #define R600_PS_RESOURCE_PM4                            128
 492 /* R600_VS_RESOURCE */
 493 #define R600_VS_RESOURCE__RESOURCE160_WORD0                     0
 494 #define R600_VS_RESOURCE__RESOURCE160_WORD1                     1
 495 #define R600_VS_RESOURCE__RESOURCE160_WORD2                     2
 496 #define R600_VS_RESOURCE__RESOURCE160_WORD3                     3
 497 #define R600_VS_RESOURCE__RESOURCE160_WORD4                     4
 498 #define R600_VS_RESOURCE__RESOURCE160_WORD5                     5
 499 #define R600_VS_RESOURCE__RESOURCE160_WORD6                     6
 500 #define R600_VS_RESOURCE_SIZE                           7
 501 #define R600_VS_RESOURCE_PM4                            128
 502 /* R600_FS_RESOURCE */
 503 #define R600_FS_RESOURCE__RESOURCE320_WORD0                     0
 504 #define R600_FS_RESOURCE__RESOURCE320_WORD1                     1
 505 #define R600_FS_RESOURCE__RESOURCE320_WORD2                     2
 506 #define R600_FS_RESOURCE__RESOURCE320_WORD3                     3
 507 #define R600_FS_RESOURCE__RESOURCE320_WORD4                     4
 508 #define R600_FS_RESOURCE__RESOURCE320_WORD5                     5
 509 #define R600_FS_RESOURCE__RESOURCE320_WORD6                     6
 510 #define R600_FS_RESOURCE_SIZE                           7
 511 #define R600_FS_RESOURCE_PM4                            128
 512 /* R600_GS_RESOURCE */
 513 #define R600_GS_RESOURCE__RESOURCE336_WORD0                     0
 514 #define R600_GS_RESOURCE__RESOURCE336_WORD1                     1
 515 #define R600_GS_RESOURCE__RESOURCE336_WORD2                     2
 516 #define R600_GS_RESOURCE__RESOURCE336_WORD3                     3
 517 #define R600_GS_RESOURCE__RESOURCE336_WORD4                     4
 518 #define R600_GS_RESOURCE__RESOURCE336_WORD5                     5
 519 #define R600_GS_RESOURCE__RESOURCE336_WORD6                     6
 520 #define R600_GS_RESOURCE_SIZE                           7
 521 #define R600_GS_RESOURCE_PM4                            128
 522 /* R600_PS_SAMPLER */
 523 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0                 0
 524 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0                 1
 525 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0                 2
 526 #define R600_PS_SAMPLER_SIZE                            3
 527 #define R600_PS_SAMPLER_PM4                             128
 528 /* R600_VS_SAMPLER */
 529 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18                        0
 530 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18                        1
 531 #define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18                        2
 532 #define R600_VS_SAMPLER_SIZE                            3
 533 #define R600_VS_SAMPLER_PM4                             128
 534 /* R600_GS_SAMPLER */
 535 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36                        0
 536 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36                        1
 537 #define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36                        2
 538 #define R600_GS_SAMPLER_SIZE                            3
 539 #define R600_GS_SAMPLER_PM4                             128
 540 /* R600_PS_SAMPLER_BORDER */
 541 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED                       0
 542 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN                     1
 543 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE                      2
 544 #define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA                     3
 545 #define R600_PS_SAMPLER_BORDER_SIZE                             4
 546 #define R600_PS_SAMPLER_BORDER_PM4                              128
 547 /* R600_VS_SAMPLER_BORDER */
 548 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED                       0
 549 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN                     1
 550 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE                      2
 551 #define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA                     3
 552 #define R600_VS_SAMPLER_BORDER_SIZE                             4
 553 #define R600_VS_SAMPLER_BORDER_PM4                              128
 554 /* R600_GS_SAMPLER_BORDER */
 555 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED                       0
 556 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN                     1
 557 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE                      2
 558 #define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA                     3
 559 #define R600_GS_SAMPLER_BORDER_SIZE                             4
 560 #define R600_GS_SAMPLER_BORDER_PM4                              128
 561 /* R600_CB0 */
 562 #define R600_CB0__CB_COLOR0_BASE                        0
 563 #define R600_CB0__CB_COLOR0_INFO                        1
 564 #define R600_CB0__CB_COLOR0_SIZE                        2
 565 #define R600_CB0__CB_COLOR0_VIEW                        3
 566 #define R600_CB0__CB_COLOR0_FRAG                        4
 567 #define R600_CB0__CB_COLOR0_TILE                        5
 568 #define R600_CB0__CB_COLOR0_MASK                        6
 569 #define R600_CB0_SIZE                           7
 570 #define R600_CB0_PM4                            128
 571 /* R600_DB */
 572 #define R600_DB__DB_DEPTH_BASE                  0
 573 #define R600_DB__DB_DEPTH_SIZE                  1
 574 #define R600_DB__DB_DEPTH_VIEW                  2
 575 #define R600_DB__DB_DEPTH_INFO                  3
 576 #define R600_DB__DB_HTILE_SURFACE                       4
 577 #define R600_DB__DB_PREFETCH_LIMIT                      5
 578 #define R600_DB_SIZE                            6
 579 #define R600_DB_PM4                             128
 580 /* R600_VGT */
 581 #define R600_VGT__VGT_PRIMITIVE_TYPE                    0
 582 #define R600_VGT__VGT_MAX_VTX_INDX                      1
 583 #define R600_VGT__VGT_MIN_VTX_INDX                      2
 584 #define R600_VGT__VGT_INDX_OFFSET                       3
 585 #define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX                  4
 586 #define R600_VGT__VGT_DMA_INDEX_TYPE                    5
 587 #define R600_VGT__VGT_PRIMITIVEID_EN                    6
 588 #define R600_VGT__VGT_DMA_NUM_INSTANCES                 7
 589 #define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN                    8
 590 #define R600_VGT__VGT_INSTANCE_STEP_RATE_0                      9
 591 #define R600_VGT__VGT_INSTANCE_STEP_RATE_1                      10
 592 #define R600_VGT_SIZE                           11
 593 #define R600_VGT_PM4                            128
 594 /* R600_DRAW */
 595 #define R600_DRAW__VGT_NUM_INDICES                      0
 596 #define R600_DRAW__VGT_DMA_BASE_HI                      1
 597 #define R600_DRAW__VGT_DMA_BASE                         2
 598 #define R600_DRAW__VGT_DRAW_INITIATOR                   3
 599 #define R600_DRAW_SIZE                                  4
 600 #define R600_DRAW_PM4                                   128
 601 /* R600_CLIP */
 602 #define R600_CLIP__PA_CL_UCP_X_0                        0
 603 #define R600_CLIP__PA_CL_UCP_Y_0                        1
 604 #define R600_CLIP__PA_CL_UCP_Z_0                        2
 605 #define R600_CLIP__PA_CL_UCP_W_0                        3
 606 #define R600_CLIP__PA_CL_UCP_X_1                        4
 607 #define R600_CLIP__PA_CL_UCP_Y_1                        5
 608 #define R600_CLIP__PA_CL_UCP_Z_1                        6
 609 #define R600_CLIP__PA_CL_UCP_W_1                        7
 610 #define R600_CLIP__PA_CL_UCP_X_2                        8
 611 #define R600_CLIP__PA_CL_UCP_Y_2                        9
 612 #define R600_CLIP__PA_CL_UCP_Z_2                        10
 613 #define R600_CLIP__PA_CL_UCP_W_2                        11
 614 #define R600_CLIP__PA_CL_UCP_X_3                        12
 615 #define R600_CLIP__PA_CL_UCP_Y_3                        13
 616 #define R600_CLIP__PA_CL_UCP_Z_3                        14
 617 #define R600_CLIP__PA_CL_UCP_W_3                        15
 618 #define R600_CLIP__PA_CL_UCP_X_4                        16
 619 #define R600_CLIP__PA_CL_UCP_Y_4                        17
 620 #define R600_CLIP__PA_CL_UCP_Z_4                        18
 621 #define R600_CLIP__PA_CL_UCP_W_4                        19
 622 #define R600_CLIP__PA_CL_UCP_X_5                        20
 623 #define R600_CLIP__PA_CL_UCP_Y_5                        21
 624 #define R600_CLIP__PA_CL_UCP_Z_5                        22
 625 #define R600_CLIP__PA_CL_UCP_W_5                        23
 626 #define R600_CLIP_SIZE                                  24
 627 #define R600_CLIP_PM4                                   128
 628 /* R600 QUERY BEGIN/END */
 629 #define R600_QUERY__OFFSET                      0
 630 #define R600_QUERY_SIZE                         1
 631 #define R600_QUERY_PM4                          128
 632
 633 #endif