src/gallium/drivers/radeon/r600_cs.h

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Marek Olšák <maraeo@gmail.com>
  24  */
  25
  26 /**
  27  * This file contains helpers for writing commands to commands streams.
  28  */
  29
  30 #ifndef R600_CS_H
  31 #define R600_CS_H
  32
  33 #include "r600_pipe_common.h"
  34 #include "r600d_common.h"
  35
  36 /**
  37  * Return true if there is enough memory in VRAM and GTT for the buffers
  38  * added so far.
  39  *
  40  * \param vram      VRAM memory size not added to the buffer list yet
  41  * \param gtt       GTT memory size not added to the buffer list yet
  42  */
  43 static inline bool
  44 radeon_cs_memory_below_limit(struct r600_common_screen *screen,
  45                              struct radeon_winsys_cs *cs,
  46                              uint64_t vram, uint64_t gtt)
  47 {
  48         vram += cs->used_vram;
  49         gtt += cs->used_gart;
  50
  51         /* Anything that goes above the VRAM size should go to GTT. */
  52         if (vram > screen->info.vram_size)
  53                 gtt += vram - screen->info.vram_size;
  54
  55         /* Now we just need to check if we have enough GTT. */
  56         return gtt < screen->info.gart_size * 0.7;
  57 }
  58
  59 /**
  60  * Add a buffer to the buffer list for the given command stream (CS).
  61  *
  62  * All buffers used by a CS must be added to the list. This tells the kernel
  63  * driver which buffers are used by GPU commands. Other buffers can
  64  * be swapped out (not accessible) during execution.
  65  *
  66  * The buffer list becomes empty after every context flush and must be
  67  * rebuilt.
  68  */
  69 static inline unsigned radeon_add_to_buffer_list(struct r600_common_context *rctx,
  70                                                  struct r600_ring *ring,
  71                                                  struct r600_resource *rbo,
  72                                                  enum radeon_bo_usage usage,
  73                                                  enum radeon_bo_priority priority)
  74 {
  75         assert(usage);
  76         return rctx->ws->cs_add_buffer(ring->cs, rbo->buf, usage,
  77                                       rbo->domains, priority) * 4;
  78 }
  79
  80 /**
  81  * Same as above, but also checks memory usage and flushes the context
  82  * accordingly.
  83  *
  84  * When this SHOULD NOT be used:
  85  *
  86  * - if r600_context_add_resource_size has been called for the buffer
  87  *   followed by *_need_cs_space for checking the memory usage
  88  *
  89  * - if r600_need_dma_space has been called for the buffer
  90  *
  91  * - when emitting state packets and draw packets (because preceding packets
  92  *   can't be re-emitted at that point)
  93  *
  94  * - if shader resource "enabled_mask" is not up-to-date or there is
  95  *   a different constraint disallowing a context flush
  96  */
  97 static inline unsigned
  98 radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
  99                                     struct r600_ring *ring,
 100                                     struct r600_resource *rbo,
 101                                     enum radeon_bo_usage usage,
 102                                     enum radeon_bo_priority priority,
 103                                     bool check_mem)
 104 {
 105         if (check_mem &&
 106             !radeon_cs_memory_below_limit(rctx->screen, ring->cs,
 107                                           rctx->vram + rbo->vram_usage,
 108                                           rctx->gtt + rbo->gart_usage))
 109                 ring->flush(rctx, RADEON_FLUSH_ASYNC, NULL);
 110
 111         return radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
 112 }
 113
 114 static inline void r600_emit_reloc(struct r600_common_context *rctx,
 115                                    struct r600_ring *ring, struct r600_resource *rbo,
 116                                    enum radeon_bo_usage usage,
 117                                    enum radeon_bo_priority priority)
 118 {
 119         struct radeon_winsys_cs *cs = ring->cs;
 120         bool has_vm = ((struct r600_common_screen*)rctx->b.screen)->info.has_virtual_memory;
 121         unsigned reloc = radeon_add_to_buffer_list(rctx, ring, rbo, usage, priority);
 122
 123         if (!has_vm) {
 124                 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 125                 radeon_emit(cs, reloc);
 126         }
 127 }
 128
 129 static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 130 {
 131         assert(reg < R600_CONTEXT_REG_OFFSET);
 132         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 133         radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
 134         radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
 135 }
 136
 137 static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 138 {
 139         radeon_set_config_reg_seq(cs, reg, 1);
 140         radeon_emit(cs, value);
 141 }
 142
 143 static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 144 {
 145         assert(reg >= R600_CONTEXT_REG_OFFSET);
 146         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 147         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
 148         radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
 149 }
 150
 151 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 152 {
 153         radeon_set_context_reg_seq(cs, reg, 1);
 154         radeon_emit(cs, value);
 155 }
 156
 157 static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
 158                                               unsigned reg, unsigned idx,
 159                                               unsigned value)
 160 {
 161         assert(reg >= R600_CONTEXT_REG_OFFSET);
 162         assert(cs->current.cdw + 3 <= cs->current.max_dw);
 163         radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
 164         radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
 165         radeon_emit(cs, value);
 166 }
 167
 168 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 169 {
 170         assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
 171         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 172         radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
 173         radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
 174 }
 175
 176 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 177 {
 178         radeon_set_sh_reg_seq(cs, reg, 1);
 179         radeon_emit(cs, value);
 180 }
 181
 182 static inline void radeon_set_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 183 {
 184         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 185         assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
 186         radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, 0));
 187         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
 188 }
 189
 190 static inline void radeon_set_uconfig_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 191 {
 192         radeon_set_uconfig_reg_seq(cs, reg, 1);
 193         radeon_emit(cs, value);
 194 }
 195
 196 static inline void radeon_set_uconfig_reg_idx(struct radeon_winsys_cs *cs,
 197                                               unsigned reg, unsigned idx,
 198                                               unsigned value)
 199 {
 200         assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
 201         assert(cs->current.cdw + 3 <= cs->current.max_dw);
 202         radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0));
 203         radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
 204         radeon_emit(cs, value);
 205 }
 206
 207 #endif