2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors: Marek Olšák <maraeo@gmail.com>
27 #include "r600_pipe_common.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/list.h"
31 #include "util/u_draw_quad.h"
32 #include "util/u_memory.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_upload_mgr.h"
35 #include "os/os_time.h"
36 #include "vl/vl_decoder.h"
37 #include "vl/vl_video_buffer.h"
38 #include "radeon/radeon_video.h"
40 #include <sys/utsname.h>
46 struct r600_multi_fence
{
47 struct pipe_reference reference
;
48 struct pipe_fence_handle
*gfx
;
49 struct pipe_fence_handle
*sdma
;
51 /* If the context wasn't flushed at fence creation, this is non-NULL. */
53 struct r600_common_context
*ctx
;
59 * shader binary helpers.
61 void radeon_shader_binary_init(struct radeon_shader_binary
*b
)
63 memset(b
, 0, sizeof(*b
));
66 void radeon_shader_binary_clean(struct radeon_shader_binary
*b
)
73 FREE(b
->global_symbol_offsets
);
75 FREE(b
->disasm_string
);
76 FREE(b
->llvm_ir_string
);
83 void r600_draw_rectangle(struct blitter_context
*blitter
,
84 int x1
, int y1
, int x2
, int y2
, float depth
,
85 enum blitter_attrib_type type
,
86 const union pipe_color_union
*attrib
)
88 struct r600_common_context
*rctx
=
89 (struct r600_common_context
*)util_blitter_get_pipe(blitter
);
90 struct pipe_viewport_state viewport
;
91 struct pipe_resource
*buf
= NULL
;
95 if (type
== UTIL_BLITTER_ATTRIB_TEXCOORD
) {
96 util_blitter_draw_rectangle(blitter
, x1
, y1
, x2
, y2
, depth
, type
, attrib
);
100 /* Some operations (like color resolve on r6xx) don't work
101 * with the conventional primitive types.
102 * One that works is PT_RECTLIST, which we use here. */
105 viewport
.scale
[0] = 1.0f
;
106 viewport
.scale
[1] = 1.0f
;
107 viewport
.scale
[2] = 1.0f
;
108 viewport
.translate
[0] = 0.0f
;
109 viewport
.translate
[1] = 0.0f
;
110 viewport
.translate
[2] = 0.0f
;
111 rctx
->b
.set_viewport_states(&rctx
->b
, 0, 1, &viewport
);
113 /* Upload vertices. The hw rectangle has only 3 vertices,
114 * I guess the 4th one is derived from the first 3.
115 * The vertex specification should match u_blitter's vertex element state. */
116 u_upload_alloc(rctx
->uploader
, 0, sizeof(float) * 24, 256, &offset
, &buf
, (void**)&vb
);
136 memcpy(vb
+4, attrib
->f
, sizeof(float)*4);
137 memcpy(vb
+12, attrib
->f
, sizeof(float)*4);
138 memcpy(vb
+20, attrib
->f
, sizeof(float)*4);
142 util_draw_vertex_buffer(&rctx
->b
, NULL
, buf
, blitter
->vb_slot
, offset
,
143 R600_PRIM_RECTANGLE_LIST
, 3, 2);
144 pipe_resource_reference(&buf
, NULL
);
147 void r600_need_dma_space(struct r600_common_context
*ctx
, unsigned num_dw
,
148 struct r600_resource
*dst
, struct r600_resource
*src
)
150 uint64_t vram
= 0, gtt
= 0;
153 vram
+= dst
->vram_usage
;
154 gtt
+= dst
->gart_usage
;
157 vram
+= src
->vram_usage
;
158 gtt
+= src
->gart_usage
;
161 /* Flush the GFX IB if DMA depends on it. */
162 if (radeon_emitted(ctx
->gfx
.cs
, ctx
->initial_gfx_cs_size
) &&
164 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, dst
->buf
,
165 RADEON_USAGE_READWRITE
)) ||
167 ctx
->ws
->cs_is_buffer_referenced(ctx
->gfx
.cs
, src
->buf
,
168 RADEON_USAGE_WRITE
))))
169 ctx
->gfx
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
171 /* Flush if there's not enough space, or if the memory usage per IB
174 if (!ctx
->ws
->cs_check_space(ctx
->dma
.cs
, num_dw
) ||
175 !radeon_cs_memory_below_limit(ctx
->screen
, ctx
->dma
.cs
, vram
, gtt
)) {
176 ctx
->dma
.flush(ctx
, RADEON_FLUSH_ASYNC
, NULL
);
177 assert((num_dw
+ ctx
->dma
.cs
->current
.cdw
) <= ctx
->dma
.cs
->current
.max_dw
);
180 /* If GPUVM is not supported, the CS checker needs 2 entries
181 * in the buffer list per packet, which has to be done manually.
183 if (ctx
->screen
->info
.has_virtual_memory
) {
185 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, dst
,
187 RADEON_PRIO_SDMA_BUFFER
);
189 radeon_add_to_buffer_list(ctx
, &ctx
->dma
, src
,
191 RADEON_PRIO_SDMA_BUFFER
);
195 /* This is required to prevent read-after-write hazards. */
196 void r600_dma_emit_wait_idle(struct r600_common_context
*rctx
)
198 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
200 /* done at the end of DMA calls, so increment this. */
201 rctx
->num_dma_calls
++;
203 /* IBs using too little memory are limited by the IB submission overhead.
204 * IBs using too much memory are limited by the kernel/TTM overhead.
205 * Too long IBs create CPU-GPU pipeline bubbles and add latency.
207 * This heuristic makes sure that DMA requests are executed
208 * very soon after the call is made and lowers memory usage.
209 * It improves texture upload performance by keeping the DMA
210 * engine busy while uploads are being submitted.
212 if (cs
->used_vram
+ cs
->used_gart
> 64 * 1024 * 1024) {
213 rctx
->dma
.flush(rctx
, RADEON_FLUSH_ASYNC
, NULL
);
217 r600_need_dma_space(rctx
, 1, NULL
, NULL
);
219 if (!radeon_emitted(cs
, 0)) /* empty queue */
222 /* NOP waits for idle on Evergreen and later. */
223 if (rctx
->chip_class
>= CIK
)
224 radeon_emit(cs
, 0x00000000); /* NOP */
225 else if (rctx
->chip_class
>= EVERGREEN
)
226 radeon_emit(cs
, 0xf0000000); /* NOP */
228 /* TODO: R600-R700 should use the FENCE packet.
229 * CS checker support is required. */
233 static void r600_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
237 void r600_preflush_suspend_features(struct r600_common_context
*ctx
)
239 /* suspend queries */
240 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
241 r600_suspend_queries(ctx
);
243 ctx
->streamout
.suspended
= false;
244 if (ctx
->streamout
.begin_emitted
) {
245 r600_emit_streamout_end(ctx
);
246 ctx
->streamout
.suspended
= true;
250 void r600_postflush_resume_features(struct r600_common_context
*ctx
)
252 if (ctx
->streamout
.suspended
) {
253 ctx
->streamout
.append_bitmask
= ctx
->streamout
.enabled_mask
;
254 r600_streamout_buffers_dirty(ctx
);
258 if (!LIST_IS_EMPTY(&ctx
->active_queries
))
259 r600_resume_queries(ctx
);
262 static void r600_flush_from_st(struct pipe_context
*ctx
,
263 struct pipe_fence_handle
**fence
,
266 struct pipe_screen
*screen
= ctx
->screen
;
267 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
268 struct radeon_winsys
*ws
= rctx
->ws
;
270 struct pipe_fence_handle
*gfx_fence
= NULL
;
271 struct pipe_fence_handle
*sdma_fence
= NULL
;
272 bool deferred_fence
= false;
274 if (flags
& PIPE_FLUSH_END_OF_FRAME
)
275 rflags
|= RADEON_FLUSH_END_OF_FRAME
;
276 if (flags
& PIPE_FLUSH_DEFERRED
)
277 rflags
|= RADEON_FLUSH_ASYNC
;
280 rctx
->dma
.flush(rctx
, rflags
, fence
? &sdma_fence
: NULL
);
283 if (!radeon_emitted(rctx
->gfx
.cs
, rctx
->initial_gfx_cs_size
)) {
285 ws
->fence_reference(&gfx_fence
, rctx
->last_gfx_fence
);
286 if (!(rflags
& RADEON_FLUSH_ASYNC
))
287 ws
->cs_sync_flush(rctx
->gfx
.cs
);
289 /* Instead of flushing, create a deferred fence. Constraints:
290 * - The state tracker must allow a deferred flush.
291 * - The state tracker must request a fence.
292 * Thread safety in fence_finish must be ensured by the state tracker.
294 if (flags
& PIPE_FLUSH_DEFERRED
&& fence
) {
295 gfx_fence
= rctx
->ws
->cs_get_next_fence(rctx
->gfx
.cs
);
296 deferred_fence
= true;
298 rctx
->gfx
.flush(rctx
, rflags
, fence
? &gfx_fence
: NULL
);
302 /* Both engines can signal out of order, so we need to keep both fences. */
304 struct r600_multi_fence
*multi_fence
=
305 CALLOC_STRUCT(r600_multi_fence
);
309 multi_fence
->reference
.count
= 1;
310 /* If both fences are NULL, fence_finish will always return true. */
311 multi_fence
->gfx
= gfx_fence
;
312 multi_fence
->sdma
= sdma_fence
;
314 if (deferred_fence
) {
315 multi_fence
->gfx_unflushed
.ctx
= rctx
;
316 multi_fence
->gfx_unflushed
.ib_index
= rctx
->num_gfx_cs_flushes
;
319 screen
->fence_reference(screen
, fence
, NULL
);
320 *fence
= (struct pipe_fence_handle
*)multi_fence
;
324 static void r600_flush_dma_ring(void *ctx
, unsigned flags
,
325 struct pipe_fence_handle
**fence
)
327 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
328 struct radeon_winsys_cs
*cs
= rctx
->dma
.cs
;
329 struct radeon_saved_cs saved
;
331 (rctx
->screen
->debug_flags
& DBG_CHECK_VM
) &&
332 rctx
->check_vm_faults
;
334 if (!radeon_emitted(cs
, 0)) {
336 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
341 radeon_save_cs(rctx
->ws
, cs
, &saved
);
343 rctx
->ws
->cs_flush(cs
, flags
, &rctx
->last_sdma_fence
);
345 rctx
->ws
->fence_reference(fence
, rctx
->last_sdma_fence
);
348 /* Use conservative timeout 800ms, after which we won't wait any
349 * longer and assume the GPU is hung.
351 rctx
->ws
->fence_wait(rctx
->ws
, rctx
->last_sdma_fence
, 800*1000*1000);
353 rctx
->check_vm_faults(rctx
, &saved
, RING_DMA
);
354 radeon_clear_saved_cs(&saved
);
359 * Store a linearized copy of all chunks of \p cs together with the buffer
362 void radeon_save_cs(struct radeon_winsys
*ws
, struct radeon_winsys_cs
*cs
,
363 struct radeon_saved_cs
*saved
)
368 /* Save the IB chunks. */
369 saved
->num_dw
= cs
->prev_dw
+ cs
->current
.cdw
;
370 saved
->ib
= MALLOC(4 * saved
->num_dw
);
375 for (i
= 0; i
< cs
->num_prev
; ++i
) {
376 memcpy(buf
, cs
->prev
[i
].buf
, cs
->prev
[i
].cdw
* 4);
377 buf
+= cs
->prev
[i
].cdw
;
379 memcpy(buf
, cs
->current
.buf
, cs
->current
.cdw
* 4);
381 /* Save the buffer list. */
382 saved
->bo_count
= ws
->cs_get_buffer_list(cs
, NULL
);
383 saved
->bo_list
= CALLOC(saved
->bo_count
,
384 sizeof(saved
->bo_list
[0]));
385 if (!saved
->bo_list
) {
389 ws
->cs_get_buffer_list(cs
, saved
->bo_list
);
394 fprintf(stderr
, "%s: out of memory\n", __func__
);
395 memset(saved
, 0, sizeof(*saved
));
398 void radeon_clear_saved_cs(struct radeon_saved_cs
*saved
)
401 FREE(saved
->bo_list
);
403 memset(saved
, 0, sizeof(*saved
));
406 static enum pipe_reset_status
r600_get_reset_status(struct pipe_context
*ctx
)
408 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
409 unsigned latest
= rctx
->ws
->query_value(rctx
->ws
,
410 RADEON_GPU_RESET_COUNTER
);
412 if (rctx
->gpu_reset_counter
== latest
)
413 return PIPE_NO_RESET
;
415 rctx
->gpu_reset_counter
= latest
;
416 return PIPE_UNKNOWN_CONTEXT_RESET
;
419 static void r600_set_debug_callback(struct pipe_context
*ctx
,
420 const struct pipe_debug_callback
*cb
)
422 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
427 memset(&rctx
->debug
, 0, sizeof(rctx
->debug
));
430 bool r600_common_context_init(struct r600_common_context
*rctx
,
431 struct r600_common_screen
*rscreen
,
432 unsigned context_flags
)
434 util_slab_create(&rctx
->pool_transfers
,
435 sizeof(struct r600_transfer
), 64,
436 UTIL_SLAB_SINGLETHREADED
);
438 rctx
->screen
= rscreen
;
439 rctx
->ws
= rscreen
->ws
;
440 rctx
->family
= rscreen
->family
;
441 rctx
->chip_class
= rscreen
->chip_class
;
443 if (rscreen
->chip_class
>= CIK
)
444 rctx
->max_db
= MAX2(8, rscreen
->info
.num_render_backends
);
445 else if (rscreen
->chip_class
>= EVERGREEN
)
450 rctx
->b
.invalidate_resource
= r600_invalidate_resource
;
451 rctx
->b
.transfer_map
= u_transfer_map_vtbl
;
452 rctx
->b
.transfer_flush_region
= u_transfer_flush_region_vtbl
;
453 rctx
->b
.transfer_unmap
= u_transfer_unmap_vtbl
;
454 rctx
->b
.texture_subdata
= u_default_texture_subdata
;
455 rctx
->b
.memory_barrier
= r600_memory_barrier
;
456 rctx
->b
.flush
= r600_flush_from_st
;
457 rctx
->b
.set_debug_callback
= r600_set_debug_callback
;
459 /* evergreen_compute.c has a special codepath for global buffers.
460 * Everything else can use the direct path.
462 if ((rscreen
->chip_class
== EVERGREEN
|| rscreen
->chip_class
== CAYMAN
) &&
463 (context_flags
& PIPE_CONTEXT_COMPUTE_ONLY
))
464 rctx
->b
.buffer_subdata
= u_default_buffer_subdata
;
466 rctx
->b
.buffer_subdata
= r600_buffer_subdata
;
468 if (rscreen
->info
.drm_major
== 2 && rscreen
->info
.drm_minor
>= 43) {
469 rctx
->b
.get_device_reset_status
= r600_get_reset_status
;
470 rctx
->gpu_reset_counter
=
471 rctx
->ws
->query_value(rctx
->ws
,
472 RADEON_GPU_RESET_COUNTER
);
475 LIST_INITHEAD(&rctx
->texture_buffers
);
477 r600_init_context_texture_functions(rctx
);
478 r600_init_viewport_functions(rctx
);
479 r600_streamout_init(rctx
);
480 r600_query_init(rctx
);
481 cayman_init_msaa(&rctx
->b
);
483 rctx
->allocator_zeroed_memory
=
484 u_suballocator_create(&rctx
->b
, rscreen
->info
.gart_page_size
,
485 0, PIPE_USAGE_DEFAULT
, true);
486 if (!rctx
->allocator_zeroed_memory
)
489 rctx
->uploader
= u_upload_create(&rctx
->b
, 1024 * 1024,
490 PIPE_BIND_INDEX_BUFFER
|
491 PIPE_BIND_CONSTANT_BUFFER
, PIPE_USAGE_STREAM
);
495 rctx
->ctx
= rctx
->ws
->ctx_create(rctx
->ws
);
499 if (rscreen
->info
.has_sdma
&& !(rscreen
->debug_flags
& DBG_NO_ASYNC_DMA
)) {
500 rctx
->dma
.cs
= rctx
->ws
->cs_create(rctx
->ctx
, RING_DMA
,
503 rctx
->dma
.flush
= r600_flush_dma_ring
;
509 void r600_common_context_cleanup(struct r600_common_context
*rctx
)
513 /* Release DCC stats. */
514 for (i
= 0; i
< ARRAY_SIZE(rctx
->dcc_stats
); i
++) {
515 assert(!rctx
->dcc_stats
[i
].query_active
);
517 for (j
= 0; j
< ARRAY_SIZE(rctx
->dcc_stats
[i
].ps_stats
); j
++)
518 if (rctx
->dcc_stats
[i
].ps_stats
[j
])
519 rctx
->b
.destroy_query(&rctx
->b
,
520 rctx
->dcc_stats
[i
].ps_stats
[j
]);
522 r600_texture_reference(&rctx
->dcc_stats
[i
].tex
, NULL
);
526 rctx
->ws
->cs_destroy(rctx
->gfx
.cs
);
528 rctx
->ws
->cs_destroy(rctx
->dma
.cs
);
530 rctx
->ws
->ctx_destroy(rctx
->ctx
);
532 if (rctx
->uploader
) {
533 u_upload_destroy(rctx
->uploader
);
536 util_slab_destroy(&rctx
->pool_transfers
);
538 if (rctx
->allocator_zeroed_memory
) {
539 u_suballocator_destroy(rctx
->allocator_zeroed_memory
);
541 rctx
->ws
->fence_reference(&rctx
->last_gfx_fence
, NULL
);
542 rctx
->ws
->fence_reference(&rctx
->last_sdma_fence
, NULL
);
545 void r600_context_add_resource_size(struct pipe_context
*ctx
, struct pipe_resource
*r
)
547 struct r600_common_context
*rctx
= (struct r600_common_context
*)ctx
;
548 struct r600_resource
*rr
= (struct r600_resource
*)r
;
555 * The idea is to compute a gross estimate of memory requirement of
556 * each draw call. After each draw call, memory will be precisely
557 * accounted. So the uncertainty is only on the current draw call.
558 * In practice this gave very good estimate (+/- 10% of the target
561 rctx
->vram
+= rr
->vram_usage
;
562 rctx
->gtt
+= rr
->gart_usage
;
569 static const struct debug_named_value common_debug_options
[] = {
571 { "tex", DBG_TEX
, "Print texture info" },
572 { "compute", DBG_COMPUTE
, "Print compute info" },
573 { "vm", DBG_VM
, "Print virtual addresses when creating resources" },
574 { "info", DBG_INFO
, "Print driver information" },
577 { "fs", DBG_FS
, "Print fetch shaders" },
578 { "vs", DBG_VS
, "Print vertex shaders" },
579 { "gs", DBG_GS
, "Print geometry shaders" },
580 { "ps", DBG_PS
, "Print pixel shaders" },
581 { "cs", DBG_CS
, "Print compute shaders" },
582 { "tcs", DBG_TCS
, "Print tessellation control shaders" },
583 { "tes", DBG_TES
, "Print tessellation evaluation shaders" },
584 { "noir", DBG_NO_IR
, "Don't print the LLVM IR"},
585 { "notgsi", DBG_NO_TGSI
, "Don't print the TGSI"},
586 { "noasm", DBG_NO_ASM
, "Don't print disassembled shaders"},
587 { "preoptir", DBG_PREOPT_IR
, "Print the LLVM IR before initial optimizations" },
589 { "testdma", DBG_TEST_DMA
, "Invoke SDMA tests and exit." },
592 { "nodma", DBG_NO_ASYNC_DMA
, "Disable asynchronous DMA" },
593 { "nohyperz", DBG_NO_HYPERZ
, "Disable Hyper-Z" },
594 /* GL uses the word INVALIDATE, gallium uses the word DISCARD */
595 { "noinvalrange", DBG_NO_DISCARD_RANGE
, "Disable handling of INVALIDATE_RANGE map flags" },
596 { "no2d", DBG_NO_2D_TILING
, "Disable 2D tiling" },
597 { "notiling", DBG_NO_TILING
, "Disable tiling" },
598 { "switch_on_eop", DBG_SWITCH_ON_EOP
, "Program WD/IA to switch on end-of-packet." },
599 { "forcedma", DBG_FORCE_DMA
, "Use asynchronous DMA for all operations when possible." },
600 { "precompile", DBG_PRECOMPILE
, "Compile one shader variant at shader creation." },
601 { "nowc", DBG_NO_WC
, "Disable GTT write combining" },
602 { "check_vm", DBG_CHECK_VM
, "Check VM faults and dump debug info." },
603 { "nodcc", DBG_NO_DCC
, "Disable DCC." },
604 { "nodccclear", DBG_NO_DCC_CLEAR
, "Disable DCC fast clear." },
605 { "norbplus", DBG_NO_RB_PLUS
, "Disable RB+ on Stoney." },
606 { "sisched", DBG_SI_SCHED
, "Enable LLVM SI Machine Instruction Scheduler." },
607 { "mono", DBG_MONOLITHIC_SHADERS
, "Use old-style monolithic shaders compiled on demand" },
608 { "noce", DBG_NO_CE
, "Disable the constant engine"},
609 { "unsafemath", DBG_UNSAFE_MATH
, "Enable unsafe math shader optimizations" },
610 { "nodccfb", DBG_NO_DCC_FB
, "Disable separate DCC on the main framebuffer" },
612 DEBUG_NAMED_VALUE_END
/* must be last */
615 static const char* r600_get_vendor(struct pipe_screen
* pscreen
)
620 static const char* r600_get_device_vendor(struct pipe_screen
* pscreen
)
625 static const char* r600_get_chip_name(struct r600_common_screen
*rscreen
)
627 switch (rscreen
->info
.family
) {
628 case CHIP_R600
: return "AMD R600";
629 case CHIP_RV610
: return "AMD RV610";
630 case CHIP_RV630
: return "AMD RV630";
631 case CHIP_RV670
: return "AMD RV670";
632 case CHIP_RV620
: return "AMD RV620";
633 case CHIP_RV635
: return "AMD RV635";
634 case CHIP_RS780
: return "AMD RS780";
635 case CHIP_RS880
: return "AMD RS880";
636 case CHIP_RV770
: return "AMD RV770";
637 case CHIP_RV730
: return "AMD RV730";
638 case CHIP_RV710
: return "AMD RV710";
639 case CHIP_RV740
: return "AMD RV740";
640 case CHIP_CEDAR
: return "AMD CEDAR";
641 case CHIP_REDWOOD
: return "AMD REDWOOD";
642 case CHIP_JUNIPER
: return "AMD JUNIPER";
643 case CHIP_CYPRESS
: return "AMD CYPRESS";
644 case CHIP_HEMLOCK
: return "AMD HEMLOCK";
645 case CHIP_PALM
: return "AMD PALM";
646 case CHIP_SUMO
: return "AMD SUMO";
647 case CHIP_SUMO2
: return "AMD SUMO2";
648 case CHIP_BARTS
: return "AMD BARTS";
649 case CHIP_TURKS
: return "AMD TURKS";
650 case CHIP_CAICOS
: return "AMD CAICOS";
651 case CHIP_CAYMAN
: return "AMD CAYMAN";
652 case CHIP_ARUBA
: return "AMD ARUBA";
653 case CHIP_TAHITI
: return "AMD TAHITI";
654 case CHIP_PITCAIRN
: return "AMD PITCAIRN";
655 case CHIP_VERDE
: return "AMD CAPE VERDE";
656 case CHIP_OLAND
: return "AMD OLAND";
657 case CHIP_HAINAN
: return "AMD HAINAN";
658 case CHIP_BONAIRE
: return "AMD BONAIRE";
659 case CHIP_KAVERI
: return "AMD KAVERI";
660 case CHIP_KABINI
: return "AMD KABINI";
661 case CHIP_HAWAII
: return "AMD HAWAII";
662 case CHIP_MULLINS
: return "AMD MULLINS";
663 case CHIP_TONGA
: return "AMD TONGA";
664 case CHIP_ICELAND
: return "AMD ICELAND";
665 case CHIP_CARRIZO
: return "AMD CARRIZO";
666 case CHIP_FIJI
: return "AMD FIJI";
667 case CHIP_POLARIS10
: return "AMD POLARIS10";
668 case CHIP_POLARIS11
: return "AMD POLARIS11";
669 case CHIP_STONEY
: return "AMD STONEY";
670 default: return "AMD unknown";
674 static const char* r600_get_name(struct pipe_screen
* pscreen
)
676 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
678 return rscreen
->renderer_string
;
681 static float r600_get_paramf(struct pipe_screen
* pscreen
,
682 enum pipe_capf param
)
684 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)pscreen
;
687 case PIPE_CAPF_MAX_LINE_WIDTH
:
688 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
689 case PIPE_CAPF_MAX_POINT_WIDTH
:
690 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
691 if (rscreen
->family
>= CHIP_CEDAR
)
695 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
697 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
699 case PIPE_CAPF_GUARD_BAND_LEFT
:
700 case PIPE_CAPF_GUARD_BAND_TOP
:
701 case PIPE_CAPF_GUARD_BAND_RIGHT
:
702 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
708 static int r600_get_video_param(struct pipe_screen
*screen
,
709 enum pipe_video_profile profile
,
710 enum pipe_video_entrypoint entrypoint
,
711 enum pipe_video_cap param
)
714 case PIPE_VIDEO_CAP_SUPPORTED
:
715 return vl_profile_supported(screen
, profile
, entrypoint
);
716 case PIPE_VIDEO_CAP_NPOT_TEXTURES
:
718 case PIPE_VIDEO_CAP_MAX_WIDTH
:
719 case PIPE_VIDEO_CAP_MAX_HEIGHT
:
720 return vl_video_buffer_max_size(screen
);
721 case PIPE_VIDEO_CAP_PREFERED_FORMAT
:
722 return PIPE_FORMAT_NV12
;
723 case PIPE_VIDEO_CAP_PREFERS_INTERLACED
:
725 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED
:
727 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE
:
729 case PIPE_VIDEO_CAP_MAX_LEVEL
:
730 return vl_level_supported(screen
, profile
);
736 const char *r600_get_llvm_processor_name(enum radeon_family family
)
779 case CHIP_TAHITI
: return "tahiti";
780 case CHIP_PITCAIRN
: return "pitcairn";
781 case CHIP_VERDE
: return "verde";
782 case CHIP_OLAND
: return "oland";
783 case CHIP_HAINAN
: return "hainan";
784 case CHIP_BONAIRE
: return "bonaire";
785 case CHIP_KABINI
: return "kabini";
786 case CHIP_KAVERI
: return "kaveri";
787 case CHIP_HAWAII
: return "hawaii";
790 case CHIP_TONGA
: return "tonga";
791 case CHIP_ICELAND
: return "iceland";
792 case CHIP_CARRIZO
: return "carrizo";
793 #if HAVE_LLVM <= 0x0307
794 case CHIP_FIJI
: return "tonga";
795 case CHIP_STONEY
: return "carrizo";
797 case CHIP_FIJI
: return "fiji";
798 case CHIP_STONEY
: return "stoney";
800 #if HAVE_LLVM <= 0x0308
801 case CHIP_POLARIS10
: return "tonga";
802 case CHIP_POLARIS11
: return "tonga";
804 case CHIP_POLARIS10
: return "polaris10";
805 case CHIP_POLARIS11
: return "polaris11";
811 static int r600_get_compute_param(struct pipe_screen
*screen
,
812 enum pipe_shader_ir ir_type
,
813 enum pipe_compute_cap param
,
816 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
818 //TODO: select these params by asic
820 case PIPE_COMPUTE_CAP_IR_TARGET
: {
823 if (rscreen
->family
<= CHIP_ARUBA
) {
828 switch(rscreen
->family
) {
829 /* Clang < 3.6 is missing Hainan in its list of
830 * GPUs, so we need to use the name of a similar GPU.
833 gpu
= r600_get_llvm_processor_name(rscreen
->family
);
837 sprintf(ret
, "%s-%s", gpu
, triple
);
839 /* +2 for dash and terminating NIL byte */
840 return (strlen(triple
) + strlen(gpu
) + 2) * sizeof(char);
842 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
844 uint64_t *grid_dimension
= ret
;
845 grid_dimension
[0] = 3;
847 return 1 * sizeof(uint64_t);
849 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
851 uint64_t *grid_size
= ret
;
852 grid_size
[0] = 65535;
853 grid_size
[1] = 65535;
854 grid_size
[2] = 65535;
856 return 3 * sizeof(uint64_t) ;
858 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
860 uint64_t *block_size
= ret
;
861 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
862 ir_type
== PIPE_SHADER_IR_TGSI
) {
863 block_size
[0] = 2048;
864 block_size
[1] = 2048;
865 block_size
[2] = 2048;
872 return 3 * sizeof(uint64_t);
874 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
876 uint64_t *max_threads_per_block
= ret
;
877 if (rscreen
->chip_class
>= SI
&& HAVE_LLVM
>= 0x309 &&
878 ir_type
== PIPE_SHADER_IR_TGSI
)
879 *max_threads_per_block
= 2048;
881 *max_threads_per_block
= 256;
883 return sizeof(uint64_t);
884 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
886 uint32_t *address_bits
= ret
;
887 address_bits
[0] = 32;
888 if (rscreen
->chip_class
>= SI
)
889 address_bits
[0] = 64;
891 return 1 * sizeof(uint32_t);
893 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
895 uint64_t *max_global_size
= ret
;
896 uint64_t max_mem_alloc_size
;
898 r600_get_compute_param(screen
, ir_type
,
899 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
,
900 &max_mem_alloc_size
);
902 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
903 * 1/4 of the MAX_GLOBAL_SIZE. Since the
904 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
905 * make sure we never report more than
906 * 4 * MAX_MEM_ALLOC_SIZE.
908 *max_global_size
= MIN2(4 * max_mem_alloc_size
,
909 MAX2(rscreen
->info
.gart_size
,
910 rscreen
->info
.vram_size
));
912 return sizeof(uint64_t);
914 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
916 uint64_t *max_local_size
= ret
;
917 /* Value reported by the closed source driver. */
918 *max_local_size
= 32768;
920 return sizeof(uint64_t);
922 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
924 uint64_t *max_input_size
= ret
;
925 /* Value reported by the closed source driver. */
926 *max_input_size
= 1024;
928 return sizeof(uint64_t);
930 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
:
932 uint64_t *max_mem_alloc_size
= ret
;
934 *max_mem_alloc_size
= rscreen
->info
.max_alloc_size
;
936 return sizeof(uint64_t);
938 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
940 uint32_t *max_clock_frequency
= ret
;
941 *max_clock_frequency
= rscreen
->info
.max_shader_clock
;
943 return sizeof(uint32_t);
945 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
947 uint32_t *max_compute_units
= ret
;
948 *max_compute_units
= rscreen
->info
.num_good_compute_units
;
950 return sizeof(uint32_t);
952 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
954 uint32_t *images_supported
= ret
;
955 *images_supported
= 0;
957 return sizeof(uint32_t);
958 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
960 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
962 uint32_t *subgroup_size
= ret
;
963 *subgroup_size
= r600_wavefront_size(rscreen
->family
);
965 return sizeof(uint32_t);
968 fprintf(stderr
, "unknown PIPE_COMPUTE_CAP %d\n", param
);
972 static uint64_t r600_get_timestamp(struct pipe_screen
*screen
)
974 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
976 return 1000000 * rscreen
->ws
->query_value(rscreen
->ws
, RADEON_TIMESTAMP
) /
977 rscreen
->info
.clock_crystal_freq
;
980 static void r600_fence_reference(struct pipe_screen
*screen
,
981 struct pipe_fence_handle
**dst
,
982 struct pipe_fence_handle
*src
)
984 struct radeon_winsys
*ws
= ((struct r600_common_screen
*)screen
)->ws
;
985 struct r600_multi_fence
**rdst
= (struct r600_multi_fence
**)dst
;
986 struct r600_multi_fence
*rsrc
= (struct r600_multi_fence
*)src
;
988 if (pipe_reference(&(*rdst
)->reference
, &rsrc
->reference
)) {
989 ws
->fence_reference(&(*rdst
)->gfx
, NULL
);
990 ws
->fence_reference(&(*rdst
)->sdma
, NULL
);
996 static boolean
r600_fence_finish(struct pipe_screen
*screen
,
997 struct pipe_context
*ctx
,
998 struct pipe_fence_handle
*fence
,
1001 struct radeon_winsys
*rws
= ((struct r600_common_screen
*)screen
)->ws
;
1002 struct r600_multi_fence
*rfence
= (struct r600_multi_fence
*)fence
;
1003 struct r600_common_context
*rctx
=
1004 ctx
? (struct r600_common_context
*)ctx
: NULL
;
1005 int64_t abs_timeout
= os_time_get_absolute_timeout(timeout
);
1008 if (!rws
->fence_wait(rws
, rfence
->sdma
, timeout
))
1011 /* Recompute the timeout after waiting. */
1012 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1013 int64_t time
= os_time_get_nano();
1014 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1021 /* Flush the gfx IB if it hasn't been flushed yet. */
1023 rfence
->gfx_unflushed
.ctx
== rctx
&&
1024 rfence
->gfx_unflushed
.ib_index
== rctx
->num_gfx_cs_flushes
) {
1025 rctx
->gfx
.flush(rctx
, timeout
? 0 : RADEON_FLUSH_ASYNC
, NULL
);
1026 rfence
->gfx_unflushed
.ctx
= NULL
;
1031 /* Recompute the timeout after all that. */
1032 if (timeout
&& timeout
!= PIPE_TIMEOUT_INFINITE
) {
1033 int64_t time
= os_time_get_nano();
1034 timeout
= abs_timeout
> time
? abs_timeout
- time
: 0;
1038 return rws
->fence_wait(rws
, rfence
->gfx
, timeout
);
1041 static void r600_query_memory_info(struct pipe_screen
*screen
,
1042 struct pipe_memory_info
*info
)
1044 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1045 struct radeon_winsys
*ws
= rscreen
->ws
;
1046 unsigned vram_usage
, gtt_usage
;
1048 info
->total_device_memory
= rscreen
->info
.vram_size
/ 1024;
1049 info
->total_staging_memory
= rscreen
->info
.gart_size
/ 1024;
1051 /* The real TTM memory usage is somewhat random, because:
1053 * 1) TTM delays freeing memory, because it can only free it after
1056 * 2) The memory usage can be really low if big VRAM evictions are
1057 * taking place, but the real usage is well above the size of VRAM.
1059 * Instead, return statistics of this process.
1061 vram_usage
= ws
->query_value(ws
, RADEON_REQUESTED_VRAM_MEMORY
) / 1024;
1062 gtt_usage
= ws
->query_value(ws
, RADEON_REQUESTED_GTT_MEMORY
) / 1024;
1064 info
->avail_device_memory
=
1065 vram_usage
<= info
->total_device_memory
?
1066 info
->total_device_memory
- vram_usage
: 0;
1067 info
->avail_staging_memory
=
1068 gtt_usage
<= info
->total_staging_memory
?
1069 info
->total_staging_memory
- gtt_usage
: 0;
1071 info
->device_memory_evicted
=
1072 ws
->query_value(ws
, RADEON_NUM_BYTES_MOVED
) / 1024;
1073 /* Just return the number of evicted 64KB pages. */
1074 info
->nr_device_memory_evictions
= info
->device_memory_evicted
/ 64;
1077 struct pipe_resource
*r600_resource_create_common(struct pipe_screen
*screen
,
1078 const struct pipe_resource
*templ
)
1080 struct r600_common_screen
*rscreen
= (struct r600_common_screen
*)screen
;
1082 if (templ
->target
== PIPE_BUFFER
) {
1083 return r600_buffer_create(screen
, templ
,
1084 rscreen
->info
.gart_page_size
);
1086 return r600_texture_create(screen
, templ
);
1090 bool r600_common_screen_init(struct r600_common_screen
*rscreen
,
1091 struct radeon_winsys
*ws
)
1093 char llvm_string
[32] = {}, kernel_version
[128] = {};
1094 struct utsname uname_data
;
1096 ws
->query_info(ws
, &rscreen
->info
);
1098 if (uname(&uname_data
) == 0)
1099 snprintf(kernel_version
, sizeof(kernel_version
),
1100 " / %s", uname_data
.release
);
1103 snprintf(llvm_string
, sizeof(llvm_string
),
1104 ", LLVM %i.%i.%i", (HAVE_LLVM
>> 8) & 0xff,
1105 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
1108 snprintf(rscreen
->renderer_string
, sizeof(rscreen
->renderer_string
),
1109 "%s (DRM %i.%i.%i%s%s)",
1110 r600_get_chip_name(rscreen
), rscreen
->info
.drm_major
,
1111 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
,
1112 kernel_version
, llvm_string
);
1114 rscreen
->b
.get_name
= r600_get_name
;
1115 rscreen
->b
.get_vendor
= r600_get_vendor
;
1116 rscreen
->b
.get_device_vendor
= r600_get_device_vendor
;
1117 rscreen
->b
.get_compute_param
= r600_get_compute_param
;
1118 rscreen
->b
.get_paramf
= r600_get_paramf
;
1119 rscreen
->b
.get_timestamp
= r600_get_timestamp
;
1120 rscreen
->b
.fence_finish
= r600_fence_finish
;
1121 rscreen
->b
.fence_reference
= r600_fence_reference
;
1122 rscreen
->b
.resource_destroy
= u_resource_destroy_vtbl
;
1123 rscreen
->b
.resource_from_user_memory
= r600_buffer_from_user_memory
;
1124 rscreen
->b
.query_memory_info
= r600_query_memory_info
;
1126 if (rscreen
->info
.has_uvd
) {
1127 rscreen
->b
.get_video_param
= rvid_get_video_param
;
1128 rscreen
->b
.is_video_format_supported
= rvid_is_format_supported
;
1130 rscreen
->b
.get_video_param
= r600_get_video_param
;
1131 rscreen
->b
.is_video_format_supported
= vl_video_buffer_is_format_supported
;
1134 r600_init_screen_texture_functions(rscreen
);
1135 r600_init_screen_query_functions(rscreen
);
1138 rscreen
->family
= rscreen
->info
.family
;
1139 rscreen
->chip_class
= rscreen
->info
.chip_class
;
1140 rscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG", common_debug_options
, 0);
1142 rscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1143 if (rscreen
->force_aniso
>= 0) {
1144 printf("radeon: Forcing anisotropy filter to %ix\n",
1145 /* round down to a power of two */
1146 1 << util_logbase2(rscreen
->force_aniso
));
1149 util_format_s3tc_init();
1150 pipe_mutex_init(rscreen
->aux_context_lock
);
1151 pipe_mutex_init(rscreen
->gpu_load_mutex
);
1153 if (rscreen
->debug_flags
& DBG_INFO
) {
1154 printf("pci_id = 0x%x\n", rscreen
->info
.pci_id
);
1155 printf("family = %i (%s)\n", rscreen
->info
.family
,
1156 r600_get_chip_name(rscreen
));
1157 printf("chip_class = %i\n", rscreen
->info
.chip_class
);
1158 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.gart_size
, 1024*1024));
1159 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(rscreen
->info
.vram_size
, 1024*1024));
1160 printf("max_alloc_size = %i MB\n",
1161 (int)DIV_ROUND_UP(rscreen
->info
.max_alloc_size
, 1024*1024));
1162 printf("has_virtual_memory = %i\n", rscreen
->info
.has_virtual_memory
);
1163 printf("gfx_ib_pad_with_type2 = %i\n", rscreen
->info
.gfx_ib_pad_with_type2
);
1164 printf("has_sdma = %i\n", rscreen
->info
.has_sdma
);
1165 printf("has_uvd = %i\n", rscreen
->info
.has_uvd
);
1166 printf("me_fw_version = %i\n", rscreen
->info
.me_fw_version
);
1167 printf("pfp_fw_version = %i\n", rscreen
->info
.pfp_fw_version
);
1168 printf("ce_fw_version = %i\n", rscreen
->info
.ce_fw_version
);
1169 printf("vce_fw_version = %i\n", rscreen
->info
.vce_fw_version
);
1170 printf("vce_harvest_config = %i\n", rscreen
->info
.vce_harvest_config
);
1171 printf("clock_crystal_freq = %i\n", rscreen
->info
.clock_crystal_freq
);
1172 printf("drm = %i.%i.%i\n", rscreen
->info
.drm_major
,
1173 rscreen
->info
.drm_minor
, rscreen
->info
.drm_patchlevel
);
1174 printf("has_userptr = %i\n", rscreen
->info
.has_userptr
);
1176 printf("r600_max_quad_pipes = %i\n", rscreen
->info
.r600_max_quad_pipes
);
1177 printf("max_shader_clock = %i\n", rscreen
->info
.max_shader_clock
);
1178 printf("num_good_compute_units = %i\n", rscreen
->info
.num_good_compute_units
);
1179 printf("max_se = %i\n", rscreen
->info
.max_se
);
1180 printf("max_sh_per_se = %i\n", rscreen
->info
.max_sh_per_se
);
1182 printf("r600_gb_backend_map = %i\n", rscreen
->info
.r600_gb_backend_map
);
1183 printf("r600_gb_backend_map_valid = %i\n", rscreen
->info
.r600_gb_backend_map_valid
);
1184 printf("r600_num_banks = %i\n", rscreen
->info
.r600_num_banks
);
1185 printf("num_render_backends = %i\n", rscreen
->info
.num_render_backends
);
1186 printf("num_tile_pipes = %i\n", rscreen
->info
.num_tile_pipes
);
1187 printf("pipe_interleave_bytes = %i\n", rscreen
->info
.pipe_interleave_bytes
);
1192 void r600_destroy_common_screen(struct r600_common_screen
*rscreen
)
1194 r600_perfcounters_destroy(rscreen
);
1195 r600_gpu_load_kill_thread(rscreen
);
1197 pipe_mutex_destroy(rscreen
->gpu_load_mutex
);
1198 pipe_mutex_destroy(rscreen
->aux_context_lock
);
1199 rscreen
->aux_context
->destroy(rscreen
->aux_context
);
1201 rscreen
->ws
->destroy(rscreen
->ws
);
1205 bool r600_can_dump_shader(struct r600_common_screen
*rscreen
,
1208 switch (processor
) {
1209 case PIPE_SHADER_VERTEX
:
1210 return (rscreen
->debug_flags
& DBG_VS
) != 0;
1211 case PIPE_SHADER_TESS_CTRL
:
1212 return (rscreen
->debug_flags
& DBG_TCS
) != 0;
1213 case PIPE_SHADER_TESS_EVAL
:
1214 return (rscreen
->debug_flags
& DBG_TES
) != 0;
1215 case PIPE_SHADER_GEOMETRY
:
1216 return (rscreen
->debug_flags
& DBG_GS
) != 0;
1217 case PIPE_SHADER_FRAGMENT
:
1218 return (rscreen
->debug_flags
& DBG_PS
) != 0;
1219 case PIPE_SHADER_COMPUTE
:
1220 return (rscreen
->debug_flags
& DBG_CS
) != 0;
1226 void r600_screen_clear_buffer(struct r600_common_screen
*rscreen
, struct pipe_resource
*dst
,
1227 uint64_t offset
, uint64_t size
, unsigned value
,
1228 enum r600_coherency coher
)
1230 struct r600_common_context
*rctx
= (struct r600_common_context
*)rscreen
->aux_context
;
1232 pipe_mutex_lock(rscreen
->aux_context_lock
);
1233 rctx
->clear_buffer(&rctx
->b
, dst
, offset
, size
, value
, coher
);
1234 rscreen
->aux_context
->flush(rscreen
->aux_context
, NULL
, 0);
1235 pipe_mutex_unlock(rscreen
->aux_context_lock
);