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48012723b7e12fc377accc0ea9ccebb47c358bce
[mesa.git] / src / gallium / drivers / radeon / radeon_vce.c
1 /**************************************************************************
2 *
3 * Copyright 2013 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include <stdio.h>
29
30 #include "pipe/p_video_codec.h"
31
32 #include "util/u_video.h"
33 #include "util/u_memory.h"
34
35 #include "vl/vl_video_buffer.h"
36
37 #include "radeonsi/si_pipe.h"
38 #include "radeon_video.h"
39 #include "radeon_vce.h"
40
41 #define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
42 #define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
43 #define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
44 #define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
45 #define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
46 #define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
47 #define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8))
48 #define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
49 #define FW_53 (53 << 24)
50
51 /**
52 * flush commands to the hardware
53 */
54 static void flush(struct rvce_encoder *enc)
55 {
56 enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL);
57 enc->task_info_idx = 0;
58 enc->bs_idx = 0;
59 }
60
61 #if 0
62 static void dump_feedback(struct rvce_encoder *enc, struct rvid_buffer *fb)
63 {
64 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
65 unsigned i = 0;
66 fprintf(stderr, "\n");
67 fprintf(stderr, "encStatus:\t\t\t%08x\n", ptr[i++]);
68 fprintf(stderr, "encHasBitstream:\t\t%08x\n", ptr[i++]);
69 fprintf(stderr, "encHasAudioBitstream:\t\t%08x\n", ptr[i++]);
70 fprintf(stderr, "encBitstreamOffset:\t\t%08x\n", ptr[i++]);
71 fprintf(stderr, "encBitstreamSize:\t\t%08x\n", ptr[i++]);
72 fprintf(stderr, "encAudioBitstreamOffset:\t%08x\n", ptr[i++]);
73 fprintf(stderr, "encAudioBitstreamSize:\t\t%08x\n", ptr[i++]);
74 fprintf(stderr, "encExtrabytes:\t\t\t%08x\n", ptr[i++]);
75 fprintf(stderr, "encAudioExtrabytes:\t\t%08x\n", ptr[i++]);
76 fprintf(stderr, "videoTimeStamp:\t\t\t%08x\n", ptr[i++]);
77 fprintf(stderr, "audioTimeStamp:\t\t\t%08x\n", ptr[i++]);
78 fprintf(stderr, "videoOutputType:\t\t%08x\n", ptr[i++]);
79 fprintf(stderr, "attributeFlags:\t\t\t%08x\n", ptr[i++]);
80 fprintf(stderr, "seiPrivatePackageOffset:\t%08x\n", ptr[i++]);
81 fprintf(stderr, "seiPrivatePackageSize:\t\t%08x\n", ptr[i++]);
82 fprintf(stderr, "\n");
83 enc->ws->buffer_unmap(fb->res->buf);
84 }
85 #endif
86
87 /**
88 * reset the CPB handling
89 */
90 static void reset_cpb(struct rvce_encoder *enc)
91 {
92 unsigned i;
93
94 list_inithead(&enc->cpb_slots);
95 for (i = 0; i < enc->cpb_num; ++i) {
96 struct rvce_cpb_slot *slot = &enc->cpb_array[i];
97 slot->index = i;
98 slot->picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP;
99 slot->frame_num = 0;
100 slot->pic_order_cnt = 0;
101 list_addtail(&slot->list, &enc->cpb_slots);
102 }
103 }
104
105 /**
106 * sort l0 and l1 to the top of the list
107 */
108 static void sort_cpb(struct rvce_encoder *enc)
109 {
110 struct rvce_cpb_slot *i, *l0 = NULL, *l1 = NULL;
111
112 LIST_FOR_EACH_ENTRY(i, &enc->cpb_slots, list) {
113 if (i->frame_num == enc->pic.ref_idx_l0)
114 l0 = i;
115
116 if (i->frame_num == enc->pic.ref_idx_l1)
117 l1 = i;
118
119 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P && l0)
120 break;
121
122 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B &&
123 l0 && l1)
124 break;
125 }
126
127 if (l1) {
128 LIST_DEL(&l1->list);
129 list_add(&l1->list, &enc->cpb_slots);
130 }
131
132 if (l0) {
133 LIST_DEL(&l0->list);
134 list_add(&l0->list, &enc->cpb_slots);
135 }
136 }
137
138 /**
139 * get number of cpbs based on dpb
140 */
141 static unsigned get_cpb_num(struct rvce_encoder *enc)
142 {
143 unsigned w = align(enc->base.width, 16) / 16;
144 unsigned h = align(enc->base.height, 16) / 16;
145 unsigned dpb;
146
147 switch (enc->base.level) {
148 case 10:
149 dpb = 396;
150 break;
151 case 11:
152 dpb = 900;
153 break;
154 case 12:
155 case 13:
156 case 20:
157 dpb = 2376;
158 break;
159 case 21:
160 dpb = 4752;
161 break;
162 case 22:
163 case 30:
164 dpb = 8100;
165 break;
166 case 31:
167 dpb = 18000;
168 break;
169 case 32:
170 dpb = 20480;
171 break;
172 case 40:
173 case 41:
174 dpb = 32768;
175 break;
176 case 42:
177 dpb = 34816;
178 break;
179 case 50:
180 dpb = 110400;
181 break;
182 default:
183 case 51:
184 case 52:
185 dpb = 184320;
186 break;
187 }
188
189 return MIN2(dpb / (w * h), 16);
190 }
191
192 /**
193 * Get the slot for the currently encoded frame
194 */
195 struct rvce_cpb_slot *si_current_slot(struct rvce_encoder *enc)
196 {
197 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list);
198 }
199
200 /**
201 * Get the slot for L0
202 */
203 struct rvce_cpb_slot *si_l0_slot(struct rvce_encoder *enc)
204 {
205 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list);
206 }
207
208 /**
209 * Get the slot for L1
210 */
211 struct rvce_cpb_slot *si_l1_slot(struct rvce_encoder *enc)
212 {
213 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, list);
214 }
215
216 /**
217 * Calculate the offsets into the CPB
218 */
219 void si_vce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
220 signed *luma_offset, signed *chroma_offset)
221 {
222 struct si_screen *sscreen = (struct si_screen *)enc->screen;
223 unsigned pitch, vpitch, fsize;
224
225 if (sscreen->info.chip_class < GFX9) {
226 pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
227 vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16);
228 } else {
229 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256);
230 vpitch = align(enc->luma->u.gfx9.surf_height, 16);
231 }
232 fsize = pitch * (vpitch + vpitch / 2);
233
234 *luma_offset = slot->index * fsize;
235 *chroma_offset = *luma_offset + pitch * vpitch;
236 }
237
238 /**
239 * destroy this video encoder
240 */
241 static void rvce_destroy(struct pipe_video_codec *encoder)
242 {
243 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
244 if (enc->stream_handle) {
245 struct rvid_buffer fb;
246 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
247 enc->fb = &fb;
248 enc->session(enc);
249 enc->destroy(enc);
250 flush(enc);
251 si_vid_destroy_buffer(&fb);
252 }
253 si_vid_destroy_buffer(&enc->cpb);
254 enc->ws->cs_destroy(enc->cs);
255 FREE(enc->cpb_array);
256 FREE(enc);
257 }
258
259 static void rvce_begin_frame(struct pipe_video_codec *encoder,
260 struct pipe_video_buffer *source,
261 struct pipe_picture_desc *picture)
262 {
263 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
264 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
265 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
266
267 bool need_rate_control =
268 enc->pic.rate_ctrl.rate_ctrl_method != pic->rate_ctrl.rate_ctrl_method ||
269 enc->pic.quant_i_frames != pic->quant_i_frames ||
270 enc->pic.quant_p_frames != pic->quant_p_frames ||
271 enc->pic.quant_b_frames != pic->quant_b_frames;
272
273 enc->pic = *pic;
274 si_get_pic_param(enc, pic);
275
276 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
277 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
278
279 if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
280 reset_cpb(enc);
281 else if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
282 pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)
283 sort_cpb(enc);
284
285 if (!enc->stream_handle) {
286 struct rvid_buffer fb;
287 enc->stream_handle = si_vid_alloc_stream_handle();
288 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
289 enc->fb = &fb;
290 enc->session(enc);
291 enc->create(enc);
292 enc->config(enc);
293 enc->feedback(enc);
294 flush(enc);
295 //dump_feedback(enc, &fb);
296 si_vid_destroy_buffer(&fb);
297 need_rate_control = false;
298 }
299
300 if (need_rate_control) {
301 enc->session(enc);
302 enc->config(enc);
303 flush(enc);
304 }
305 }
306
307 static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
308 struct pipe_video_buffer *source,
309 struct pipe_resource *destination,
310 void **fb)
311 {
312 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
313 enc->get_buffer(destination, &enc->bs_handle, NULL);
314 enc->bs_size = destination->width0;
315
316 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
317 if (!si_vid_create_buffer(enc->screen, enc->fb, 512, PIPE_USAGE_STAGING)) {
318 RVID_ERR("Can't create feedback buffer.\n");
319 return;
320 }
321 if (!radeon_emitted(enc->cs, 0))
322 enc->session(enc);
323 enc->encode(enc);
324 enc->feedback(enc);
325 }
326
327 static void rvce_end_frame(struct pipe_video_codec *encoder,
328 struct pipe_video_buffer *source,
329 struct pipe_picture_desc *picture)
330 {
331 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
332 struct rvce_cpb_slot *slot = LIST_ENTRY(
333 struct rvce_cpb_slot, enc->cpb_slots.prev, list);
334
335 if (!enc->dual_inst || enc->bs_idx > 1)
336 flush(enc);
337
338 /* update the CPB backtrack with the just encoded frame */
339 slot->picture_type = enc->pic.picture_type;
340 slot->frame_num = enc->pic.frame_num;
341 slot->pic_order_cnt = enc->pic.pic_order_cnt;
342 if (!enc->pic.not_referenced) {
343 LIST_DEL(&slot->list);
344 list_add(&slot->list, &enc->cpb_slots);
345 }
346 }
347
348 static void rvce_get_feedback(struct pipe_video_codec *encoder,
349 void *feedback, unsigned *size)
350 {
351 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
352 struct rvid_buffer *fb = feedback;
353
354 if (size) {
355 uint32_t *ptr = enc->ws->buffer_map(
356 fb->res->buf, enc->cs,
357 PIPE_TRANSFER_READ_WRITE | RADEON_TRANSFER_TEMPORARY);
358
359 if (ptr[1]) {
360 *size = ptr[4] - ptr[9];
361 } else {
362 *size = 0;
363 }
364
365 enc->ws->buffer_unmap(fb->res->buf);
366 }
367 //dump_feedback(enc, fb);
368 si_vid_destroy_buffer(fb);
369 FREE(fb);
370 }
371
372 /**
373 * flush any outstanding command buffers to the hardware
374 */
375 static void rvce_flush(struct pipe_video_codec *encoder)
376 {
377 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
378
379 flush(enc);
380 }
381
382 static void rvce_cs_flush(void *ctx, unsigned flags,
383 struct pipe_fence_handle **fence)
384 {
385 // just ignored
386 }
387
388 struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
389 const struct pipe_video_codec *templ,
390 struct radeon_winsys* ws,
391 rvce_get_buffer get_buffer)
392 {
393 struct si_screen *sscreen = (struct si_screen *)context->screen;
394 struct si_context *sctx = (struct si_context*)context;
395 struct rvce_encoder *enc;
396 struct pipe_video_buffer *tmp_buf, templat = {};
397 struct radeon_surf *tmp_surf;
398 unsigned cpb_size;
399
400 if (!sscreen->info.vce_fw_version) {
401 RVID_ERR("Kernel doesn't supports VCE!\n");
402 return NULL;
403
404 } else if (!si_vce_is_fw_version_supported(sscreen)) {
405 RVID_ERR("Unsupported VCE fw version loaded!\n");
406 return NULL;
407 }
408
409 enc = CALLOC_STRUCT(rvce_encoder);
410 if (!enc)
411 return NULL;
412
413 if (sscreen->info.is_amdgpu)
414 enc->use_vm = true;
415 if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) ||
416 sscreen->info.is_amdgpu)
417 enc->use_vui = true;
418 if (sscreen->info.family >= CHIP_TONGA &&
419 sscreen->info.family != CHIP_STONEY &&
420 sscreen->info.family != CHIP_POLARIS11 &&
421 sscreen->info.family != CHIP_POLARIS12 &&
422 sscreen->info.family != CHIP_VEGAM)
423 enc->dual_pipe = true;
424 /* TODO enable B frame with dual instance */
425 if ((sscreen->info.family >= CHIP_TONGA) &&
426 (templ->max_references == 1) &&
427 (sscreen->info.vce_harvest_config == 0))
428 enc->dual_inst = true;
429
430 enc->base = *templ;
431 enc->base.context = context;
432
433 enc->base.destroy = rvce_destroy;
434 enc->base.begin_frame = rvce_begin_frame;
435 enc->base.encode_bitstream = rvce_encode_bitstream;
436 enc->base.end_frame = rvce_end_frame;
437 enc->base.flush = rvce_flush;
438 enc->base.get_feedback = rvce_get_feedback;
439 enc->get_buffer = get_buffer;
440
441 enc->screen = context->screen;
442 enc->ws = ws;
443 enc->cs = ws->cs_create(sctx->ctx, RING_VCE, rvce_cs_flush, enc, false);
444 if (!enc->cs) {
445 RVID_ERR("Can't get command submission context.\n");
446 goto error;
447 }
448
449 templat.buffer_format = PIPE_FORMAT_NV12;
450 templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
451 templat.width = enc->base.width;
452 templat.height = enc->base.height;
453 templat.interlaced = false;
454 if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
455 RVID_ERR("Can't create video buffer.\n");
456 goto error;
457 }
458
459 enc->cpb_num = get_cpb_num(enc);
460 if (!enc->cpb_num)
461 goto error;
462
463 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
464
465 cpb_size = (sscreen->info.chip_class < GFX9) ?
466 align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
467 align(tmp_surf->u.legacy.level[0].nblk_y, 32) :
468
469 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
470 align(tmp_surf->u.gfx9.surf_height, 32);
471
472 cpb_size = cpb_size * 3 / 2;
473 cpb_size = cpb_size * enc->cpb_num;
474 if (enc->dual_pipe)
475 cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
476 RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
477 tmp_buf->destroy(tmp_buf);
478 if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
479 RVID_ERR("Can't create CPB buffer.\n");
480 goto error;
481 }
482
483 enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot));
484 if (!enc->cpb_array)
485 goto error;
486
487 reset_cpb(enc);
488
489 switch (sscreen->info.vce_fw_version) {
490 case FW_40_2_2:
491 si_vce_40_2_2_init(enc);
492 si_get_pic_param = si_vce_40_2_2_get_param;
493 break;
494
495 case FW_50_0_1:
496 case FW_50_1_2:
497 case FW_50_10_2:
498 case FW_50_17_3:
499 si_vce_50_init(enc);
500 si_get_pic_param = si_vce_50_get_param;
501 break;
502
503 case FW_52_0_3:
504 case FW_52_4_3:
505 case FW_52_8_3:
506 si_vce_52_init(enc);
507 si_get_pic_param = si_vce_52_get_param;
508 break;
509
510 default:
511 if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53) {
512 si_vce_52_init(enc);
513 si_get_pic_param = si_vce_52_get_param;
514 } else
515 goto error;
516 }
517
518 return &enc->base;
519
520 error:
521 if (enc->cs)
522 enc->ws->cs_destroy(enc->cs);
523
524 si_vid_destroy_buffer(&enc->cpb);
525
526 FREE(enc->cpb_array);
527 FREE(enc);
528 return NULL;
529 }
530
531 /**
532 * check if kernel has the right fw version loaded
533 */
534 bool si_vce_is_fw_version_supported(struct si_screen *sscreen)
535 {
536 switch (sscreen->info.vce_fw_version) {
537 case FW_40_2_2:
538 case FW_50_0_1:
539 case FW_50_1_2:
540 case FW_50_10_2:
541 case FW_50_17_3:
542 case FW_52_0_3:
543 case FW_52_4_3:
544 case FW_52_8_3:
545 return true;
546 default:
547 if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53)
548 return true;
549 else
550 return false;
551 }
552 }
553
554 /**
555 * Add the buffer as relocation to the current command submission
556 */
557 void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
558 enum radeon_bo_usage usage, enum radeon_bo_domain domain,
559 signed offset)
560 {
561 int reloc_idx;
562
563 reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED,
564 domain, 0);
565 if (enc->use_vm) {
566 uint64_t addr;
567 addr = enc->ws->buffer_get_virtual_address(buf);
568 addr = addr + offset;
569 RVCE_CS(addr >> 32);
570 RVCE_CS(addr);
571 } else {
572 offset += enc->ws->buffer_get_reloc_offset(buf);
573 RVCE_CS(reloc_idx * 4);
574 RVCE_CS(offset);
575 }
576 }