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[mesa.git] / src / gallium / drivers / radeon / radeon_vce.c
1 /**************************************************************************
2 *
3 * Copyright 2013 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /*
29 * Authors:
30 * Christian König <christian.koenig@amd.com>
31 *
32 */
33
34 #include <stdio.h>
35
36 #include "pipe/p_video_codec.h"
37
38 #include "util/u_video.h"
39 #include "util/u_memory.h"
40
41 #include "vl/vl_video_buffer.h"
42
43 #include "r600_pipe_common.h"
44 #include "radeon_video.h"
45 #include "radeon_vce.h"
46
47 #define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
48 #define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
49 #define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
50 #define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
51 #define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
52 #define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8))
53 #define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8))
54
55 /**
56 * flush commands to the hardware
57 */
58 static void flush(struct rvce_encoder *enc)
59 {
60 enc->ws->cs_flush(enc->cs, RADEON_FLUSH_ASYNC, NULL);
61 enc->task_info_idx = 0;
62 enc->bs_idx = 0;
63 }
64
65 #if 0
66 static void dump_feedback(struct rvce_encoder *enc, struct rvid_buffer *fb)
67 {
68 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
69 unsigned i = 0;
70 fprintf(stderr, "\n");
71 fprintf(stderr, "encStatus:\t\t\t%08x\n", ptr[i++]);
72 fprintf(stderr, "encHasBitstream:\t\t%08x\n", ptr[i++]);
73 fprintf(stderr, "encHasAudioBitstream:\t\t%08x\n", ptr[i++]);
74 fprintf(stderr, "encBitstreamOffset:\t\t%08x\n", ptr[i++]);
75 fprintf(stderr, "encBitstreamSize:\t\t%08x\n", ptr[i++]);
76 fprintf(stderr, "encAudioBitstreamOffset:\t%08x\n", ptr[i++]);
77 fprintf(stderr, "encAudioBitstreamSize:\t\t%08x\n", ptr[i++]);
78 fprintf(stderr, "encExtrabytes:\t\t\t%08x\n", ptr[i++]);
79 fprintf(stderr, "encAudioExtrabytes:\t\t%08x\n", ptr[i++]);
80 fprintf(stderr, "videoTimeStamp:\t\t\t%08x\n", ptr[i++]);
81 fprintf(stderr, "audioTimeStamp:\t\t\t%08x\n", ptr[i++]);
82 fprintf(stderr, "videoOutputType:\t\t%08x\n", ptr[i++]);
83 fprintf(stderr, "attributeFlags:\t\t\t%08x\n", ptr[i++]);
84 fprintf(stderr, "seiPrivatePackageOffset:\t%08x\n", ptr[i++]);
85 fprintf(stderr, "seiPrivatePackageSize:\t\t%08x\n", ptr[i++]);
86 fprintf(stderr, "\n");
87 enc->ws->buffer_unmap(fb->res->buf);
88 }
89 #endif
90
91 /**
92 * reset the CPB handling
93 */
94 static void reset_cpb(struct rvce_encoder *enc)
95 {
96 unsigned i;
97
98 LIST_INITHEAD(&enc->cpb_slots);
99 for (i = 0; i < enc->cpb_num; ++i) {
100 struct rvce_cpb_slot *slot = &enc->cpb_array[i];
101 slot->index = i;
102 slot->picture_type = PIPE_H264_ENC_PICTURE_TYPE_SKIP;
103 slot->frame_num = 0;
104 slot->pic_order_cnt = 0;
105 LIST_ADDTAIL(&slot->list, &enc->cpb_slots);
106 }
107 }
108
109 /**
110 * sort l0 and l1 to the top of the list
111 */
112 static void sort_cpb(struct rvce_encoder *enc)
113 {
114 struct rvce_cpb_slot *i, *l0 = NULL, *l1 = NULL;
115
116 LIST_FOR_EACH_ENTRY(i, &enc->cpb_slots, list) {
117 if (i->frame_num == enc->pic.ref_idx_l0)
118 l0 = i;
119
120 if (i->frame_num == enc->pic.ref_idx_l1)
121 l1 = i;
122
123 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P && l0)
124 break;
125
126 if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B &&
127 l0 && l1)
128 break;
129 }
130
131 if (l1) {
132 LIST_DEL(&l1->list);
133 LIST_ADD(&l1->list, &enc->cpb_slots);
134 }
135
136 if (l0) {
137 LIST_DEL(&l0->list);
138 LIST_ADD(&l0->list, &enc->cpb_slots);
139 }
140 }
141
142 /**
143 * get number of cpbs based on dpb
144 */
145 static unsigned get_cpb_num(struct rvce_encoder *enc)
146 {
147 unsigned w = align(enc->base.width, 16) / 16;
148 unsigned h = align(enc->base.height, 16) / 16;
149 unsigned dpb;
150
151 switch (enc->base.level) {
152 case 10:
153 dpb = 396;
154 break;
155 case 11:
156 dpb = 900;
157 break;
158 case 12:
159 case 13:
160 case 20:
161 dpb = 2376;
162 break;
163 case 21:
164 dpb = 4752;
165 break;
166 case 22:
167 case 30:
168 dpb = 8100;
169 break;
170 case 31:
171 dpb = 18000;
172 break;
173 case 32:
174 dpb = 20480;
175 break;
176 case 40:
177 case 41:
178 dpb = 32768;
179 break;
180 default:
181 case 42:
182 dpb = 34816;
183 break;
184 case 50:
185 dpb = 110400;
186 break;
187 case 51:
188 dpb = 184320;
189 break;
190 }
191
192 return MIN2(dpb / (w * h), 16);
193 }
194
195 /**
196 * Get the slot for the currently encoded frame
197 */
198 struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc)
199 {
200 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list);
201 }
202
203 /**
204 * Get the slot for L0
205 */
206 struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc)
207 {
208 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list);
209 }
210
211 /**
212 * Get the slot for L1
213 */
214 struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
215 {
216 return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, list);
217 }
218
219 /**
220 * Calculate the offsets into the CPB
221 */
222 void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
223 signed *luma_offset, signed *chroma_offset)
224 {
225 unsigned pitch = align(enc->luma->level[0].pitch_bytes, 128);
226 unsigned vpitch = align(enc->luma->npix_y, 16);
227 unsigned fsize = pitch * (vpitch + vpitch / 2);
228
229 *luma_offset = slot->index * fsize;
230 *chroma_offset = *luma_offset + pitch * vpitch;
231 }
232
233 /**
234 * destroy this video encoder
235 */
236 static void rvce_destroy(struct pipe_video_codec *encoder)
237 {
238 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
239 if (enc->stream_handle) {
240 struct rvid_buffer fb;
241 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
242 enc->fb = &fb;
243 enc->session(enc);
244 enc->feedback(enc);
245 enc->destroy(enc);
246 flush(enc);
247 rvid_destroy_buffer(&fb);
248 }
249 rvid_destroy_buffer(&enc->cpb);
250 enc->ws->cs_destroy(enc->cs);
251 FREE(enc->cpb_array);
252 FREE(enc);
253 }
254
255 static void rvce_begin_frame(struct pipe_video_codec *encoder,
256 struct pipe_video_buffer *source,
257 struct pipe_picture_desc *picture)
258 {
259 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
260 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
261 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
262
263 bool need_rate_control =
264 enc->pic.rate_ctrl.rate_ctrl_method != pic->rate_ctrl.rate_ctrl_method ||
265 enc->pic.quant_i_frames != pic->quant_i_frames ||
266 enc->pic.quant_p_frames != pic->quant_p_frames ||
267 enc->pic.quant_b_frames != pic->quant_b_frames;
268
269 enc->pic = *pic;
270 get_pic_param(enc, pic);
271
272 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
273 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
274
275 if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
276 reset_cpb(enc);
277 else if (pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
278 pic->picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)
279 sort_cpb(enc);
280
281 if (!enc->stream_handle) {
282 struct rvid_buffer fb;
283 enc->stream_handle = rvid_alloc_stream_handle();
284 rvid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
285 enc->fb = &fb;
286 enc->session(enc);
287 enc->create(enc);
288 enc->config(enc);
289 enc->feedback(enc);
290 flush(enc);
291 //dump_feedback(enc, &fb);
292 rvid_destroy_buffer(&fb);
293 need_rate_control = false;
294 }
295
296 if (need_rate_control) {
297 enc->session(enc);
298 enc->config(enc);
299 flush(enc);
300 }
301 }
302
303 static void rvce_encode_bitstream(struct pipe_video_codec *encoder,
304 struct pipe_video_buffer *source,
305 struct pipe_resource *destination,
306 void **fb)
307 {
308 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
309 enc->get_buffer(destination, &enc->bs_handle, NULL);
310 enc->bs_size = destination->width0;
311
312 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
313 if (!rvid_create_buffer(enc->screen, enc->fb, 512, PIPE_USAGE_STAGING)) {
314 RVID_ERR("Can't create feedback buffer.\n");
315 return;
316 }
317 if (!radeon_emitted(enc->cs, 0))
318 enc->session(enc);
319 enc->encode(enc);
320 enc->feedback(enc);
321 }
322
323 static void rvce_end_frame(struct pipe_video_codec *encoder,
324 struct pipe_video_buffer *source,
325 struct pipe_picture_desc *picture)
326 {
327 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
328 struct rvce_cpb_slot *slot = LIST_ENTRY(
329 struct rvce_cpb_slot, enc->cpb_slots.prev, list);
330
331 if (!enc->dual_inst || enc->bs_idx > 1)
332 flush(enc);
333
334 /* update the CPB backtrack with the just encoded frame */
335 slot->picture_type = enc->pic.picture_type;
336 slot->frame_num = enc->pic.frame_num;
337 slot->pic_order_cnt = enc->pic.pic_order_cnt;
338 if (!enc->pic.not_referenced) {
339 LIST_DEL(&slot->list);
340 LIST_ADD(&slot->list, &enc->cpb_slots);
341 }
342 }
343
344 static void rvce_get_feedback(struct pipe_video_codec *encoder,
345 void *feedback, unsigned *size)
346 {
347 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
348 struct rvid_buffer *fb = feedback;
349
350 if (size) {
351 uint32_t *ptr = enc->ws->buffer_map(fb->res->buf, enc->cs, PIPE_TRANSFER_READ_WRITE);
352
353 if (ptr[1]) {
354 *size = ptr[4] - ptr[9];
355 } else {
356 *size = 0;
357 }
358
359 enc->ws->buffer_unmap(fb->res->buf);
360 }
361 //dump_feedback(enc, fb);
362 rvid_destroy_buffer(fb);
363 FREE(fb);
364 }
365
366 /**
367 * flush any outstanding command buffers to the hardware
368 */
369 static void rvce_flush(struct pipe_video_codec *encoder)
370 {
371 struct rvce_encoder *enc = (struct rvce_encoder*)encoder;
372
373 flush(enc);
374 }
375
376 static void rvce_cs_flush(void *ctx, unsigned flags,
377 struct pipe_fence_handle **fence)
378 {
379 // just ignored
380 }
381
382 struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
383 const struct pipe_video_codec *templ,
384 struct radeon_winsys* ws,
385 rvce_get_buffer get_buffer)
386 {
387 struct r600_common_screen *rscreen = (struct r600_common_screen *)context->screen;
388 struct r600_common_context *rctx = (struct r600_common_context*)context;
389 struct rvce_encoder *enc;
390 struct pipe_video_buffer *tmp_buf, templat = {};
391 struct radeon_surf *tmp_surf;
392 unsigned cpb_size;
393
394 if (!rscreen->info.vce_fw_version) {
395 RVID_ERR("Kernel doesn't supports VCE!\n");
396 return NULL;
397
398 } else if (!rvce_is_fw_version_supported(rscreen)) {
399 RVID_ERR("Unsupported VCE fw version loaded!\n");
400 return NULL;
401 }
402
403 enc = CALLOC_STRUCT(rvce_encoder);
404 if (!enc)
405 return NULL;
406
407 if (rscreen->info.drm_major == 3)
408 enc->use_vm = true;
409 if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) ||
410 rscreen->info.drm_major == 3)
411 enc->use_vui = true;
412 if (rscreen->info.family >= CHIP_TONGA &&
413 rscreen->info.family != CHIP_STONEY &&
414 rscreen->info.family != CHIP_POLARIS11)
415 enc->dual_pipe = true;
416 /* TODO enable B frame with dual instance */
417 if ((rscreen->info.family >= CHIP_TONGA) &&
418 (templ->max_references == 1) &&
419 (rscreen->info.vce_harvest_config == 0))
420 enc->dual_inst = true;
421
422 enc->base = *templ;
423 enc->base.context = context;
424
425 enc->base.destroy = rvce_destroy;
426 enc->base.begin_frame = rvce_begin_frame;
427 enc->base.encode_bitstream = rvce_encode_bitstream;
428 enc->base.end_frame = rvce_end_frame;
429 enc->base.flush = rvce_flush;
430 enc->base.get_feedback = rvce_get_feedback;
431 enc->get_buffer = get_buffer;
432
433 enc->screen = context->screen;
434 enc->ws = ws;
435 enc->cs = ws->cs_create(rctx->ctx, RING_VCE, rvce_cs_flush, enc);
436 if (!enc->cs) {
437 RVID_ERR("Can't get command submission context.\n");
438 goto error;
439 }
440
441 templat.buffer_format = PIPE_FORMAT_NV12;
442 templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
443 templat.width = enc->base.width;
444 templat.height = enc->base.height;
445 templat.interlaced = false;
446 if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
447 RVID_ERR("Can't create video buffer.\n");
448 goto error;
449 }
450
451 enc->cpb_num = get_cpb_num(enc);
452 if (!enc->cpb_num)
453 goto error;
454
455 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
456 cpb_size = align(tmp_surf->level[0].pitch_bytes, 128);
457 cpb_size = cpb_size * align(tmp_surf->npix_y, 32);
458 cpb_size = cpb_size * 3 / 2;
459 cpb_size = cpb_size * enc->cpb_num;
460 if (enc->dual_pipe)
461 cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
462 RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
463 tmp_buf->destroy(tmp_buf);
464 if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
465 RVID_ERR("Can't create CPB buffer.\n");
466 goto error;
467 }
468
469 enc->cpb_array = CALLOC(enc->cpb_num, sizeof(struct rvce_cpb_slot));
470 if (!enc->cpb_array)
471 goto error;
472
473 reset_cpb(enc);
474
475 switch (rscreen->info.vce_fw_version) {
476 case FW_40_2_2:
477 radeon_vce_40_2_2_init(enc);
478 get_pic_param = radeon_vce_40_2_2_get_param;
479 break;
480
481 case FW_50_0_1:
482 case FW_50_1_2:
483 case FW_50_10_2:
484 case FW_50_17_3:
485 radeon_vce_50_init(enc);
486 get_pic_param = radeon_vce_50_get_param;
487 break;
488
489 case FW_52_0_3:
490 case FW_52_4_3:
491 radeon_vce_52_init(enc);
492 get_pic_param = radeon_vce_52_get_param;
493 break;
494
495 default:
496 goto error;
497 }
498
499 return &enc->base;
500
501 error:
502 if (enc->cs)
503 enc->ws->cs_destroy(enc->cs);
504
505 rvid_destroy_buffer(&enc->cpb);
506
507 FREE(enc->cpb_array);
508 FREE(enc);
509 return NULL;
510 }
511
512 /**
513 * check if kernel has the right fw version loaded
514 */
515 bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
516 {
517 switch (rscreen->info.vce_fw_version) {
518 case FW_40_2_2:
519 case FW_50_0_1:
520 case FW_50_1_2:
521 case FW_50_10_2:
522 case FW_50_17_3:
523 case FW_52_0_3:
524 case FW_52_4_3:
525 return true;
526 default:
527 return false;
528 }
529 }
530
531 /**
532 * Add the buffer as relocation to the current command submission
533 */
534 void rvce_add_buffer(struct rvce_encoder *enc, struct pb_buffer *buf,
535 enum radeon_bo_usage usage, enum radeon_bo_domain domain,
536 signed offset)
537 {
538 int reloc_idx;
539
540 reloc_idx = enc->ws->cs_add_buffer(enc->cs, buf, usage, domain, RADEON_PRIO_VCE);
541 if (enc->use_vm) {
542 uint64_t addr;
543 addr = enc->ws->buffer_get_virtual_address(buf);
544 addr = addr + offset;
545 RVCE_CS(addr >> 32);
546 RVCE_CS(addr);
547 } else {
548 RVCE_CS(reloc_idx * 4);
549 RVCE_CS(offset);
550 }
551 }