2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014,2015 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
31 static void cik_sdma_copy_buffer(struct si_context
*ctx
,
32 struct pipe_resource
*dst
,
33 struct pipe_resource
*src
,
38 struct radeon_winsys_cs
*cs
= ctx
->b
.dma
.cs
;
39 unsigned i
, ncopy
, csize
;
40 struct r600_resource
*rdst
= r600_resource(dst
);
41 struct r600_resource
*rsrc
= r600_resource(src
);
43 /* Mark the buffer range of destination as valid (initialized),
44 * so that transfer_map knows it should wait for the GPU when mapping
46 util_range_add(&rdst
->valid_buffer_range
, dst_offset
,
49 dst_offset
+= rdst
->gpu_address
;
50 src_offset
+= rsrc
->gpu_address
;
52 ncopy
= DIV_ROUND_UP(size
, CIK_SDMA_COPY_MAX_SIZE
);
53 si_need_dma_space(&ctx
->b
, ncopy
* 7, rdst
, rsrc
);
55 for (i
= 0; i
< ncopy
; i
++) {
56 csize
= MIN2(size
, CIK_SDMA_COPY_MAX_SIZE
);
57 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
58 CIK_SDMA_COPY_SUB_OPCODE_LINEAR
,
60 radeon_emit(cs
, ctx
->b
.chip_class
>= GFX9
? csize
- 1 : csize
);
61 radeon_emit(cs
, 0); /* src/dst endian swap */
62 radeon_emit(cs
, src_offset
);
63 radeon_emit(cs
, src_offset
>> 32);
64 radeon_emit(cs
, dst_offset
);
65 radeon_emit(cs
, dst_offset
>> 32);
72 static void cik_sdma_clear_buffer(struct pipe_context
*ctx
,
73 struct pipe_resource
*dst
,
78 struct si_context
*sctx
= (struct si_context
*)ctx
;
79 struct radeon_winsys_cs
*cs
= sctx
->b
.dma
.cs
;
80 unsigned i
, ncopy
, csize
;
81 struct r600_resource
*rdst
= r600_resource(dst
);
83 if (!cs
|| offset
% 4 != 0 || size
% 4 != 0 ||
84 dst
->flags
& PIPE_RESOURCE_FLAG_SPARSE
) {
85 ctx
->clear_buffer(ctx
, dst
, offset
, size
, &clear_value
, 4);
89 /* Mark the buffer range of destination as valid (initialized),
90 * so that transfer_map knows it should wait for the GPU when mapping
92 util_range_add(&rdst
->valid_buffer_range
, offset
, offset
+ size
);
94 offset
+= rdst
->gpu_address
;
96 /* the same maximum size as for copying */
97 ncopy
= DIV_ROUND_UP(size
, CIK_SDMA_COPY_MAX_SIZE
);
98 si_need_dma_space(&sctx
->b
, ncopy
* 5, rdst
, NULL
);
100 for (i
= 0; i
< ncopy
; i
++) {
101 csize
= MIN2(size
, CIK_SDMA_COPY_MAX_SIZE
);
102 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_PACKET_CONSTANT_FILL
, 0,
103 0x8000 /* dword copy */));
104 radeon_emit(cs
, offset
);
105 radeon_emit(cs
, offset
>> 32);
106 radeon_emit(cs
, clear_value
);
107 radeon_emit(cs
, sctx
->b
.chip_class
>= GFX9
? csize
- 1 : csize
);
113 static unsigned minify_as_blocks(unsigned width
, unsigned level
, unsigned blk_w
)
115 width
= u_minify(width
, level
);
116 return DIV_ROUND_UP(width
, blk_w
);
119 static unsigned encode_tile_info(struct si_context
*sctx
,
120 struct r600_texture
*tex
, unsigned level
,
123 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
124 unsigned tile_index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
125 unsigned macro_tile_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
126 unsigned tile_mode
= info
->si_tile_mode_array
[tile_index
];
127 unsigned macro_tile_mode
= info
->cik_macrotile_mode_array
[macro_tile_index
];
129 return (set_bpp
? util_logbase2(tex
->surface
.bpe
) : 0) |
130 (G_009910_ARRAY_MODE(tile_mode
) << 3) |
131 (G_009910_MICRO_TILE_MODE_NEW(tile_mode
) << 8) |
132 /* Non-depth modes don't have TILE_SPLIT set. */
133 ((util_logbase2(tex
->surface
.u
.legacy
.tile_split
>> 6)) << 11) |
134 (G_009990_BANK_WIDTH(macro_tile_mode
) << 15) |
135 (G_009990_BANK_HEIGHT(macro_tile_mode
) << 18) |
136 (G_009990_NUM_BANKS(macro_tile_mode
) << 21) |
137 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode
) << 24) |
138 (G_009910_PIPE_CONFIG(tile_mode
) << 26);
141 static bool cik_sdma_copy_texture(struct si_context
*sctx
,
142 struct pipe_resource
*dst
,
144 unsigned dstx
, unsigned dsty
, unsigned dstz
,
145 struct pipe_resource
*src
,
147 const struct pipe_box
*src_box
)
149 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
150 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
151 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
152 unsigned bpp
= rdst
->surface
.bpe
;
153 uint64_t dst_address
= rdst
->resource
.gpu_address
+
154 rdst
->surface
.u
.legacy
.level
[dst_level
].offset
;
155 uint64_t src_address
= rsrc
->resource
.gpu_address
+
156 rsrc
->surface
.u
.legacy
.level
[src_level
].offset
;
157 unsigned dst_mode
= rdst
->surface
.u
.legacy
.level
[dst_level
].mode
;
158 unsigned src_mode
= rsrc
->surface
.u
.legacy
.level
[src_level
].mode
;
159 unsigned dst_tile_index
= rdst
->surface
.u
.legacy
.tiling_index
[dst_level
];
160 unsigned src_tile_index
= rsrc
->surface
.u
.legacy
.tiling_index
[src_level
];
161 unsigned dst_tile_mode
= info
->si_tile_mode_array
[dst_tile_index
];
162 unsigned src_tile_mode
= info
->si_tile_mode_array
[src_tile_index
];
163 unsigned dst_micro_mode
= G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode
);
164 unsigned src_micro_mode
= G_009910_MICRO_TILE_MODE_NEW(src_tile_mode
);
165 unsigned dst_tile_swizzle
= dst_mode
== RADEON_SURF_MODE_2D
?
166 rdst
->surface
.tile_swizzle
: 0;
167 unsigned src_tile_swizzle
= src_mode
== RADEON_SURF_MODE_2D
?
168 rsrc
->surface
.tile_swizzle
: 0;
169 unsigned dst_pitch
= rdst
->surface
.u
.legacy
.level
[dst_level
].nblk_x
;
170 unsigned src_pitch
= rsrc
->surface
.u
.legacy
.level
[src_level
].nblk_x
;
171 uint64_t dst_slice_pitch
= rdst
->surface
.u
.legacy
.level
[dst_level
].slice_size
/ bpp
;
172 uint64_t src_slice_pitch
= rsrc
->surface
.u
.legacy
.level
[src_level
].slice_size
/ bpp
;
173 unsigned dst_width
= minify_as_blocks(rdst
->resource
.b
.b
.width0
,
174 dst_level
, rdst
->surface
.blk_w
);
175 unsigned src_width
= minify_as_blocks(rsrc
->resource
.b
.b
.width0
,
176 src_level
, rsrc
->surface
.blk_w
);
177 unsigned dst_height
= minify_as_blocks(rdst
->resource
.b
.b
.height0
,
178 dst_level
, rdst
->surface
.blk_h
);
179 unsigned src_height
= minify_as_blocks(rsrc
->resource
.b
.b
.height0
,
180 src_level
, rsrc
->surface
.blk_h
);
181 unsigned srcx
= src_box
->x
/ rsrc
->surface
.blk_w
;
182 unsigned srcy
= src_box
->y
/ rsrc
->surface
.blk_h
;
183 unsigned srcz
= src_box
->z
;
184 unsigned copy_width
= DIV_ROUND_UP(src_box
->width
, rsrc
->surface
.blk_w
);
185 unsigned copy_height
= DIV_ROUND_UP(src_box
->height
, rsrc
->surface
.blk_h
);
186 unsigned copy_depth
= src_box
->depth
;
188 assert(src_level
<= src
->last_level
);
189 assert(dst_level
<= dst
->last_level
);
190 assert(rdst
->surface
.u
.legacy
.level
[dst_level
].offset
+
191 dst_slice_pitch
* bpp
* (dstz
+ src_box
->depth
) <=
192 rdst
->resource
.buf
->size
);
193 assert(rsrc
->surface
.u
.legacy
.level
[src_level
].offset
+
194 src_slice_pitch
* bpp
* (srcz
+ src_box
->depth
) <=
195 rsrc
->resource
.buf
->size
);
197 if (!si_prepare_for_dma_blit(&sctx
->b
, rdst
, dst_level
, dstx
, dsty
,
198 dstz
, rsrc
, src_level
, src_box
))
201 dstx
/= rdst
->surface
.blk_w
;
202 dsty
/= rdst
->surface
.blk_h
;
204 if (srcx
>= (1 << 14) ||
212 dst_address
|= dst_tile_swizzle
<< 8;
213 src_address
|= src_tile_swizzle
<< 8;
215 /* Linear -> linear sub-window copy. */
216 if (dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
&&
217 src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
&&
218 /* check if everything fits into the bitfields */
219 src_pitch
<= (1 << 14) &&
220 dst_pitch
<= (1 << 14) &&
221 src_slice_pitch
<= (1 << 28) &&
222 dst_slice_pitch
<= (1 << 28) &&
223 copy_width
<= (1 << 14) &&
224 copy_height
<= (1 << 14) &&
225 copy_depth
<= (1 << 11) &&
226 /* HW limitation - CIK: */
227 (sctx
->b
.chip_class
!= CIK
||
228 (copy_width
< (1 << 14) &&
229 copy_height
< (1 << 14) &&
230 copy_depth
< (1 << 11))) &&
231 /* HW limitation - some CIK parts: */
232 ((sctx
->b
.family
!= CHIP_BONAIRE
&&
233 sctx
->b
.family
!= CHIP_KAVERI
) ||
234 (srcx
+ copy_width
!= (1 << 14) &&
235 srcy
+ copy_height
!= (1 << 14)))) {
236 struct radeon_winsys_cs
*cs
= sctx
->b
.dma
.cs
;
238 si_need_dma_space(&sctx
->b
, 13, &rdst
->resource
, &rsrc
->resource
);
240 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
241 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW
, 0) |
242 (util_logbase2(bpp
) << 29));
243 radeon_emit(cs
, src_address
);
244 radeon_emit(cs
, src_address
>> 32);
245 radeon_emit(cs
, srcx
| (srcy
<< 16));
246 radeon_emit(cs
, srcz
| ((src_pitch
- 1) << 16));
247 radeon_emit(cs
, src_slice_pitch
- 1);
248 radeon_emit(cs
, dst_address
);
249 radeon_emit(cs
, dst_address
>> 32);
250 radeon_emit(cs
, dstx
| (dsty
<< 16));
251 radeon_emit(cs
, dstz
| ((dst_pitch
- 1) << 16));
252 radeon_emit(cs
, dst_slice_pitch
- 1);
253 if (sctx
->b
.chip_class
== CIK
) {
254 radeon_emit(cs
, copy_width
| (copy_height
<< 16));
255 radeon_emit(cs
, copy_depth
);
257 radeon_emit(cs
, (copy_width
- 1) | ((copy_height
- 1) << 16));
258 radeon_emit(cs
, (copy_depth
- 1));
263 /* Tiled <-> linear sub-window copy. */
264 if ((src_mode
>= RADEON_SURF_MODE_1D
) != (dst_mode
>= RADEON_SURF_MODE_1D
)) {
265 struct r600_texture
*tiled
= src_mode
>= RADEON_SURF_MODE_1D
? rsrc
: rdst
;
266 struct r600_texture
*linear
= tiled
== rsrc
? rdst
: rsrc
;
267 unsigned tiled_level
= tiled
== rsrc
? src_level
: dst_level
;
268 unsigned linear_level
= linear
== rsrc
? src_level
: dst_level
;
269 unsigned tiled_x
= tiled
== rsrc
? srcx
: dstx
;
270 unsigned linear_x
= linear
== rsrc
? srcx
: dstx
;
271 unsigned tiled_y
= tiled
== rsrc
? srcy
: dsty
;
272 unsigned linear_y
= linear
== rsrc
? srcy
: dsty
;
273 unsigned tiled_z
= tiled
== rsrc
? srcz
: dstz
;
274 unsigned linear_z
= linear
== rsrc
? srcz
: dstz
;
275 unsigned tiled_width
= tiled
== rsrc
? src_width
: dst_width
;
276 unsigned linear_width
= linear
== rsrc
? src_width
: dst_width
;
277 unsigned tiled_pitch
= tiled
== rsrc
? src_pitch
: dst_pitch
;
278 unsigned linear_pitch
= linear
== rsrc
? src_pitch
: dst_pitch
;
279 unsigned tiled_slice_pitch
= tiled
== rsrc
? src_slice_pitch
: dst_slice_pitch
;
280 unsigned linear_slice_pitch
= linear
== rsrc
? src_slice_pitch
: dst_slice_pitch
;
281 uint64_t tiled_address
= tiled
== rsrc
? src_address
: dst_address
;
282 uint64_t linear_address
= linear
== rsrc
? src_address
: dst_address
;
283 unsigned tiled_micro_mode
= tiled
== rsrc
? src_micro_mode
: dst_micro_mode
;
285 assert(tiled_pitch
% 8 == 0);
286 assert(tiled_slice_pitch
% 64 == 0);
287 unsigned pitch_tile_max
= tiled_pitch
/ 8 - 1;
288 unsigned slice_tile_max
= tiled_slice_pitch
/ 64 - 1;
289 unsigned xalign
= MAX2(1, 4 / bpp
);
290 unsigned copy_width_aligned
= copy_width
;
292 /* If the region ends at the last pixel and is unaligned, we
293 * can copy the remainder of the line that is not visible to
296 if (copy_width
% xalign
!= 0 &&
297 linear_x
+ copy_width
== linear_width
&&
298 tiled_x
+ copy_width
== tiled_width
&&
299 linear_x
+ align(copy_width
, xalign
) <= linear_pitch
&&
300 tiled_x
+ align(copy_width
, xalign
) <= tiled_pitch
)
301 copy_width_aligned
= align(copy_width
, xalign
);
303 /* HW limitations. */
304 if ((sctx
->b
.family
== CHIP_BONAIRE
||
305 sctx
->b
.family
== CHIP_KAVERI
) &&
306 linear_pitch
- 1 == 0x3fff &&
310 if (sctx
->b
.chip_class
== CIK
&&
311 (copy_width_aligned
== (1 << 14) ||
312 copy_height
== (1 << 14) ||
313 copy_depth
== (1 << 11)))
316 if ((sctx
->b
.family
== CHIP_BONAIRE
||
317 sctx
->b
.family
== CHIP_KAVERI
||
318 sctx
->b
.family
== CHIP_KABINI
||
319 sctx
->b
.family
== CHIP_MULLINS
) &&
320 (tiled_x
+ copy_width
== (1 << 14) ||
321 tiled_y
+ copy_height
== (1 << 14)))
324 /* The hw can read outside of the given linear buffer bounds,
325 * or access those pages but not touch the memory in case
326 * of writes. (it still causes a VM fault)
328 * Out-of-bounds memory access or page directory access must
331 int64_t start_linear_address
, end_linear_address
;
332 unsigned granularity
;
334 /* Deduce the size of reads from the linear surface. */
335 switch (tiled_micro_mode
) {
336 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING
:
337 granularity
= bpp
== 1 ? 64 / (8*bpp
) :
340 case V_009910_ADDR_SURF_THIN_MICRO_TILING
:
341 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING
:
342 if (0 /* TODO: THICK microtiling */)
343 granularity
= bpp
== 1 ? 32 / (8*bpp
) :
344 bpp
== 2 ? 64 / (8*bpp
) :
345 bpp
<= 8 ? 128 / (8*bpp
) :
348 granularity
= bpp
<= 2 ? 64 / (8*bpp
) :
349 bpp
<= 8 ? 128 / (8*bpp
) :
356 /* The linear reads start at tiled_x & ~(granularity - 1).
357 * If linear_x == 0 && tiled_x % granularity != 0, the hw
358 * starts reading from an address preceding linear_address!!!
360 start_linear_address
=
361 linear
->surface
.u
.legacy
.level
[linear_level
].offset
+
362 bpp
* (linear_z
* linear_slice_pitch
+
363 linear_y
* linear_pitch
+
365 start_linear_address
-= (int)(bpp
* (tiled_x
% granularity
));
368 linear
->surface
.u
.legacy
.level
[linear_level
].offset
+
369 bpp
* ((linear_z
+ copy_depth
- 1) * linear_slice_pitch
+
370 (linear_y
+ copy_height
- 1) * linear_pitch
+
371 (linear_x
+ copy_width
));
373 if ((tiled_x
+ copy_width
) % granularity
)
374 end_linear_address
+= granularity
-
375 (tiled_x
+ copy_width
) % granularity
;
377 if (start_linear_address
< 0 ||
378 end_linear_address
> linear
->surface
.surf_size
)
381 /* Check requirements. */
382 if (tiled_address
% 256 == 0 &&
383 linear_address
% 4 == 0 &&
384 linear_pitch
% xalign
== 0 &&
385 linear_x
% xalign
== 0 &&
386 tiled_x
% xalign
== 0 &&
387 copy_width_aligned
% xalign
== 0 &&
388 tiled_micro_mode
!= V_009910_ADDR_SURF_ROTATED_MICRO_TILING
&&
389 /* check if everything fits into the bitfields */
390 tiled
->surface
.u
.legacy
.tile_split
<= 4096 &&
391 pitch_tile_max
< (1 << 11) &&
392 slice_tile_max
< (1 << 22) &&
393 linear_pitch
<= (1 << 14) &&
394 linear_slice_pitch
<= (1 << 28) &&
395 copy_width_aligned
<= (1 << 14) &&
396 copy_height
<= (1 << 14) &&
397 copy_depth
<= (1 << 11)) {
398 struct radeon_winsys_cs
*cs
= sctx
->b
.dma
.cs
;
399 uint32_t direction
= linear
== rdst
? 1u << 31 : 0;
401 si_need_dma_space(&sctx
->b
, 14, &rdst
->resource
, &rsrc
->resource
);
403 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
404 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW
, 0) |
406 radeon_emit(cs
, tiled_address
);
407 radeon_emit(cs
, tiled_address
>> 32);
408 radeon_emit(cs
, tiled_x
| (tiled_y
<< 16));
409 radeon_emit(cs
, tiled_z
| (pitch_tile_max
<< 16));
410 radeon_emit(cs
, slice_tile_max
);
411 radeon_emit(cs
, encode_tile_info(sctx
, tiled
, tiled_level
, true));
412 radeon_emit(cs
, linear_address
);
413 radeon_emit(cs
, linear_address
>> 32);
414 radeon_emit(cs
, linear_x
| (linear_y
<< 16));
415 radeon_emit(cs
, linear_z
| ((linear_pitch
- 1) << 16));
416 radeon_emit(cs
, linear_slice_pitch
- 1);
417 if (sctx
->b
.chip_class
== CIK
) {
418 radeon_emit(cs
, copy_width_aligned
| (copy_height
<< 16));
419 radeon_emit(cs
, copy_depth
);
421 radeon_emit(cs
, (copy_width_aligned
- 1) | ((copy_height
- 1) << 16));
422 radeon_emit(cs
, (copy_depth
- 1));
428 /* Tiled -> Tiled sub-window copy. */
429 if (dst_mode
>= RADEON_SURF_MODE_1D
&&
430 src_mode
>= RADEON_SURF_MODE_1D
&&
431 /* check if these fit into the bitfields */
432 src_address
% 256 == 0 &&
433 dst_address
% 256 == 0 &&
434 rsrc
->surface
.u
.legacy
.tile_split
<= 4096 &&
435 rdst
->surface
.u
.legacy
.tile_split
<= 4096 &&
440 /* this can either be equal, or display->rotated (VI+ only) */
441 (src_micro_mode
== dst_micro_mode
||
442 (sctx
->b
.chip_class
>= VI
&&
443 src_micro_mode
== V_009910_ADDR_SURF_DISPLAY_MICRO_TILING
&&
444 dst_micro_mode
== V_009910_ADDR_SURF_ROTATED_MICRO_TILING
))) {
445 assert(src_pitch
% 8 == 0);
446 assert(dst_pitch
% 8 == 0);
447 assert(src_slice_pitch
% 64 == 0);
448 assert(dst_slice_pitch
% 64 == 0);
449 unsigned src_pitch_tile_max
= src_pitch
/ 8 - 1;
450 unsigned dst_pitch_tile_max
= dst_pitch
/ 8 - 1;
451 unsigned src_slice_tile_max
= src_slice_pitch
/ 64 - 1;
452 unsigned dst_slice_tile_max
= dst_slice_pitch
/ 64 - 1;
453 unsigned copy_width_aligned
= copy_width
;
454 unsigned copy_height_aligned
= copy_height
;
456 /* If the region ends at the last pixel and is unaligned, we
457 * can copy the remainder of the tile that is not visible to
460 if (copy_width
% 8 != 0 &&
461 srcx
+ copy_width
== src_width
&&
462 dstx
+ copy_width
== dst_width
)
463 copy_width_aligned
= align(copy_width
, 8);
465 if (copy_height
% 8 != 0 &&
466 srcy
+ copy_height
== src_height
&&
467 dsty
+ copy_height
== dst_height
)
468 copy_height_aligned
= align(copy_height
, 8);
470 /* check if these fit into the bitfields */
471 if (src_pitch_tile_max
< (1 << 11) &&
472 dst_pitch_tile_max
< (1 << 11) &&
473 src_slice_tile_max
< (1 << 22) &&
474 dst_slice_tile_max
< (1 << 22) &&
475 copy_width_aligned
<= (1 << 14) &&
476 copy_height_aligned
<= (1 << 14) &&
477 copy_depth
<= (1 << 11) &&
478 copy_width_aligned
% 8 == 0 &&
479 copy_height_aligned
% 8 == 0 &&
480 /* HW limitation - CIK: */
481 (sctx
->b
.chip_class
!= CIK
||
482 (copy_width_aligned
< (1 << 14) &&
483 copy_height_aligned
< (1 << 14) &&
484 copy_depth
< (1 << 11))) &&
485 /* HW limitation - some CIK parts: */
486 ((sctx
->b
.family
!= CHIP_BONAIRE
&&
487 sctx
->b
.family
!= CHIP_KAVERI
&&
488 sctx
->b
.family
!= CHIP_KABINI
&&
489 sctx
->b
.family
!= CHIP_MULLINS
) ||
490 (srcx
+ copy_width_aligned
!= (1 << 14) &&
491 srcy
+ copy_height_aligned
!= (1 << 14) &&
492 dstx
+ copy_width
!= (1 << 14)))) {
493 struct radeon_winsys_cs
*cs
= sctx
->b
.dma
.cs
;
495 si_need_dma_space(&sctx
->b
, 15, &rdst
->resource
, &rsrc
->resource
);
497 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
498 CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW
, 0));
499 radeon_emit(cs
, src_address
);
500 radeon_emit(cs
, src_address
>> 32);
501 radeon_emit(cs
, srcx
| (srcy
<< 16));
502 radeon_emit(cs
, srcz
| (src_pitch_tile_max
<< 16));
503 radeon_emit(cs
, src_slice_tile_max
);
504 radeon_emit(cs
, encode_tile_info(sctx
, rsrc
, src_level
, true));
505 radeon_emit(cs
, dst_address
);
506 radeon_emit(cs
, dst_address
>> 32);
507 radeon_emit(cs
, dstx
| (dsty
<< 16));
508 radeon_emit(cs
, dstz
| (dst_pitch_tile_max
<< 16));
509 radeon_emit(cs
, dst_slice_tile_max
);
510 radeon_emit(cs
, encode_tile_info(sctx
, rdst
, dst_level
, false));
511 if (sctx
->b
.chip_class
== CIK
) {
512 radeon_emit(cs
, copy_width_aligned
|
513 (copy_height_aligned
<< 16));
514 radeon_emit(cs
, copy_depth
);
516 radeon_emit(cs
, (copy_width_aligned
- 8) |
517 ((copy_height_aligned
- 8) << 16));
518 radeon_emit(cs
, (copy_depth
- 1));
527 static void cik_sdma_copy(struct pipe_context
*ctx
,
528 struct pipe_resource
*dst
,
530 unsigned dstx
, unsigned dsty
, unsigned dstz
,
531 struct pipe_resource
*src
,
533 const struct pipe_box
*src_box
)
535 struct si_context
*sctx
= (struct si_context
*)ctx
;
537 if (!sctx
->b
.dma
.cs
||
538 src
->flags
& PIPE_RESOURCE_FLAG_SPARSE
||
539 dst
->flags
& PIPE_RESOURCE_FLAG_SPARSE
)
542 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
543 cik_sdma_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
);
547 if ((sctx
->b
.chip_class
== CIK
|| sctx
->b
.chip_class
== VI
) &&
548 cik_sdma_copy_texture(sctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
549 src
, src_level
, src_box
))
553 si_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
554 src
, src_level
, src_box
);
557 void cik_init_sdma_functions(struct si_context
*sctx
)
559 sctx
->b
.dma_copy
= cik_sdma_copy
;
560 sctx
->b
.dma_clear_buffer
= cik_sdma_clear_buffer
;