src/gallium/drivers/radeonsi/cik_sdma.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2014,2015 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Jerome Glisse
  26  */
  27
  28 #include "sid.h"
  29 #include "si_pipe.h"
  30
  31 static void cik_sdma_do_copy_buffer(struct si_context *ctx,
  32                                     struct pipe_resource *dst,
  33                                     struct pipe_resource *src,
  34                                     uint64_t dst_offset,
  35                                     uint64_t src_offset,
  36                                     uint64_t size)
  37 {
  38         struct radeon_winsys_cs *cs = ctx->b.dma.cs;
  39         unsigned i, ncopy, csize;
  40         struct r600_resource *rdst = (struct r600_resource*)dst;
  41         struct r600_resource *rsrc = (struct r600_resource*)src;
  42
  43         dst_offset += r600_resource(dst)->gpu_address;
  44         src_offset += r600_resource(src)->gpu_address;
  45
  46         ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
  47         r600_need_dma_space(&ctx->b, ncopy * 7, rdst, rsrc);
  48
  49         for (i = 0; i < ncopy; i++) {
  50                 csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);
  51                 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
  52                                                 CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
  53                                                 0));
  54                 radeon_emit(cs, csize);
  55                 radeon_emit(cs, 0); /* src/dst endian swap */
  56                 radeon_emit(cs, src_offset);
  57                 radeon_emit(cs, src_offset >> 32);
  58                 radeon_emit(cs, dst_offset);
  59                 radeon_emit(cs, dst_offset >> 32);
  60                 dst_offset += csize;
  61                 src_offset += csize;
  62                 size -= csize;
  63         }
  64 }
  65
  66 static void cik_sdma_copy_buffer(struct si_context *ctx,
  67                                  struct pipe_resource *dst,
  68                                  struct pipe_resource *src,
  69                                  uint64_t dst_offset,
  70                                  uint64_t src_offset,
  71                                  uint64_t size)
  72 {
  73         struct r600_resource *rdst = (struct r600_resource*)dst;
  74
  75         /* Mark the buffer range of destination as valid (initialized),
  76          * so that transfer_map knows it should wait for the GPU when mapping
  77          * that range. */
  78         util_range_add(&rdst->valid_buffer_range, dst_offset,
  79                        dst_offset + size);
  80
  81         cik_sdma_do_copy_buffer(ctx, dst, src, dst_offset, src_offset, size);
  82         r600_dma_emit_wait_idle(&ctx->b);
  83 }
  84
  85 static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
  86 {
  87         width = u_minify(width, level);
  88         return DIV_ROUND_UP(width, blk_w);
  89 }
  90
  91 static unsigned encode_tile_info(struct si_context *sctx,
  92                                  struct r600_texture *tex, unsigned level,
  93                                  bool set_bpp)
  94 {
  95         struct radeon_info *info = &sctx->screen->b.info;
  96         unsigned tile_index = tex->surface.tiling_index[level];
  97         unsigned macro_tile_index = tex->surface.macro_tile_index;
  98         unsigned tile_mode = info->si_tile_mode_array[tile_index];
  99         unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
 100
 101         return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) |
 102                 (G_009910_ARRAY_MODE(tile_mode) << 3) |
 103                 (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
 104                 /* Non-depth modes don't have TILE_SPLIT set. */
 105                 ((util_logbase2(tex->surface.tile_split >> 6)) << 11) |
 106                 (G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
 107                 (G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
 108                 (G_009990_NUM_BANKS(macro_tile_mode) << 21) |
 109                 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode) << 24) |
 110                 (G_009910_PIPE_CONFIG(tile_mode) << 26);
 111 }
 112
 113 static bool cik_sdma_copy_texture(struct si_context *sctx,
 114                                   struct pipe_resource *dst,
 115                                   unsigned dst_level,
 116                                   unsigned dstx, unsigned dsty, unsigned dstz,
 117                                   struct pipe_resource *src,
 118                                   unsigned src_level,
 119                                   const struct pipe_box *src_box)
 120 {
 121         struct radeon_info *info = &sctx->screen->b.info;
 122         struct r600_texture *rsrc = (struct r600_texture*)src;
 123         struct r600_texture *rdst = (struct r600_texture*)dst;
 124         unsigned bpp = rdst->surface.bpe;
 125         uint64_t dst_address = rdst->resource.gpu_address +
 126                                rdst->surface.level[dst_level].offset;
 127         uint64_t src_address = rsrc->resource.gpu_address +
 128                                rsrc->surface.level[src_level].offset;
 129         unsigned dst_mode = rdst->surface.level[dst_level].mode;
 130         unsigned src_mode = rsrc->surface.level[src_level].mode;
 131         unsigned dst_tile_index = rdst->surface.tiling_index[dst_level];
 132         unsigned src_tile_index = rsrc->surface.tiling_index[src_level];
 133         unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
 134         unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
 135         unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
 136         unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
 137         unsigned dst_pitch = rdst->surface.level[dst_level].pitch_bytes / bpp;
 138         unsigned src_pitch = rsrc->surface.level[src_level].pitch_bytes / bpp;
 139         uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp;
 140         uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp;
 141         unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0,
 142                                               dst_level, rdst->surface.blk_w);
 143         unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0,
 144                                               src_level, rsrc->surface.blk_w);
 145         unsigned dst_height = minify_as_blocks(rdst->resource.b.b.height0,
 146                                                dst_level, rdst->surface.blk_h);
 147         unsigned src_height = minify_as_blocks(rsrc->resource.b.b.height0,
 148                                                src_level, rsrc->surface.blk_h);
 149         unsigned srcx = src_box->x / rsrc->surface.blk_w;
 150         unsigned srcy = src_box->y / rsrc->surface.blk_h;
 151         unsigned srcz = src_box->z;
 152         unsigned copy_width = DIV_ROUND_UP(src_box->width, rsrc->surface.blk_w);
 153         unsigned copy_height = DIV_ROUND_UP(src_box->height, rsrc->surface.blk_h);
 154         unsigned copy_depth = src_box->depth;
 155
 156         assert(src_level <= src->last_level);
 157         assert(dst_level <= dst->last_level);
 158         assert(rdst->surface.level[dst_level].offset +
 159                dst_slice_pitch * bpp * (dstz + src_box->depth) <=
 160                rdst->resource.buf->size);
 161         assert(rsrc->surface.level[src_level].offset +
 162                src_slice_pitch * bpp * (srcz + src_box->depth) <=
 163                rsrc->resource.buf->size);
 164
 165         if (!r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
 166                                         dstz, rsrc, src_level, src_box))
 167                 return false;
 168
 169         dstx /= rdst->surface.blk_w;
 170         dsty /= rdst->surface.blk_h;
 171
 172         if (srcx >= (1 << 14) ||
 173             srcy >= (1 << 14) ||
 174             srcz >= (1 << 11) ||
 175             dstx >= (1 << 14) ||
 176             dsty >= (1 << 14) ||
 177             dstz >= (1 << 11))
 178                 return false;
 179
 180         /* Linear -> linear sub-window copy. */
 181         if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
 182             src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
 183             /* check if everything fits into the bitfields */
 184             src_pitch <= (1 << 14) &&
 185             dst_pitch <= (1 << 14) &&
 186             src_slice_pitch <= (1 << 28) &&
 187             dst_slice_pitch <= (1 << 28) &&
 188             copy_width <= (1 << 14) &&
 189             copy_height <= (1 << 14) &&
 190             copy_depth <= (1 << 11) &&
 191             /* HW limitation - CIK: */
 192             (sctx->b.chip_class != CIK ||
 193              (copy_width < (1 << 14) &&
 194               copy_height < (1 << 14) &&
 195               copy_depth < (1 << 11))) &&
 196             /* HW limitation - some CIK parts: */
 197             ((sctx->b.family != CHIP_BONAIRE &&
 198               sctx->b.family != CHIP_KAVERI) ||
 199              (srcx + copy_width != (1 << 14) &&
 200               srcy + copy_height != (1 << 14)))) {
 201                 struct radeon_winsys_cs *cs = sctx->b.dma.cs;
 202
 203                 r600_need_dma_space(&sctx->b, 13, &rdst->resource, &rsrc->resource);
 204
 205                 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
 206                                                 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
 207                             (util_logbase2(bpp) << 29));
 208                 radeon_emit(cs, src_address);
 209                 radeon_emit(cs, src_address >> 32);
 210                 radeon_emit(cs, srcx | (srcy << 16));
 211                 radeon_emit(cs, srcz | ((src_pitch - 1) << 16));
 212                 radeon_emit(cs, src_slice_pitch - 1);
 213                 radeon_emit(cs, dst_address);
 214                 radeon_emit(cs, dst_address >> 32);
 215                 radeon_emit(cs, dstx | (dsty << 16));
 216                 radeon_emit(cs, dstz | ((dst_pitch - 1) << 16));
 217                 radeon_emit(cs, dst_slice_pitch - 1);
 218                 if (sctx->b.chip_class == CIK) {
 219                         radeon_emit(cs, copy_width | (copy_height << 16));
 220                         radeon_emit(cs, copy_depth);
 221                 } else {
 222                         radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
 223                         radeon_emit(cs, (copy_depth - 1));
 224                 }
 225
 226                 r600_dma_emit_wait_idle(&sctx->b);
 227                 return true;
 228         }
 229
 230         /* Tiled <-> linear sub-window copy. */
 231         if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
 232                 struct r600_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? rsrc : rdst;
 233                 struct r600_texture *linear = tiled == rsrc ? rdst : rsrc;
 234                 unsigned tiled_level =  tiled   == rsrc ? src_level : dst_level;
 235                 unsigned linear_level = linear  == rsrc ? src_level : dst_level;
 236                 unsigned tiled_x =      tiled   == rsrc ? srcx : dstx;
 237                 unsigned linear_x =     linear  == rsrc ? srcx : dstx;
 238                 unsigned tiled_y =      tiled   == rsrc ? srcy : dsty;
 239                 unsigned linear_y =     linear  == rsrc ? srcy : dsty;
 240                 unsigned tiled_z =      tiled   == rsrc ? srcz : dstz;
 241                 unsigned linear_z =     linear  == rsrc ? srcz : dstz;
 242                 unsigned tiled_width =  tiled   == rsrc ? src_width : dst_width;
 243                 unsigned linear_width = linear  == rsrc ? src_width : dst_width;
 244                 unsigned tiled_pitch =  tiled   == rsrc ? src_pitch : dst_pitch;
 245                 unsigned linear_pitch = linear  == rsrc ? src_pitch : dst_pitch;
 246                 unsigned tiled_slice_pitch  = tiled  == rsrc ? src_slice_pitch : dst_slice_pitch;
 247                 unsigned linear_slice_pitch = linear == rsrc ? src_slice_pitch : dst_slice_pitch;
 248                 uint64_t tiled_address =  tiled  == rsrc ? src_address : dst_address;
 249                 uint64_t linear_address = linear == rsrc ? src_address : dst_address;
 250                 unsigned tiled_micro_mode = tiled == rsrc ? src_micro_mode : dst_micro_mode;
 251
 252                 assert(tiled_pitch % 8 == 0);
 253                 assert(tiled_slice_pitch % 64 == 0);
 254                 unsigned pitch_tile_max = tiled_pitch / 8 - 1;
 255                 unsigned slice_tile_max = tiled_slice_pitch / 64 - 1;
 256                 unsigned xalign = MAX2(1, 4 / bpp);
 257                 unsigned copy_width_aligned = copy_width;
 258
 259                 /* If the region ends at the last pixel and is unaligned, we
 260                  * can copy the remainder of the line that is not visible to
 261                  * make it aligned.
 262                  */
 263                 if (copy_width % xalign != 0 &&
 264                     linear_x + copy_width == linear_width &&
 265                     tiled_x  + copy_width == tiled_width &&
 266                     linear_x + align(copy_width, xalign) <= linear_pitch &&
 267                     tiled_x  + align(copy_width, xalign) <= tiled_pitch)
 268                         copy_width_aligned = align(copy_width, xalign);
 269
 270                 /* HW limitations. */
 271                 if ((sctx->b.family == CHIP_BONAIRE ||
 272                      sctx->b.family == CHIP_KAVERI) &&
 273                     linear_pitch - 1 == 0x3fff &&
 274                     bpp == 16)
 275                         return false;
 276
 277                 if (sctx->b.chip_class == CIK &&
 278                     (copy_width_aligned == (1 << 14) ||
 279                      copy_height == (1 << 14) ||
 280                      copy_depth == (1 << 11)))
 281                         return false;
 282
 283                 if ((sctx->b.family == CHIP_BONAIRE ||
 284                      sctx->b.family == CHIP_KAVERI ||
 285                      sctx->b.family == CHIP_KABINI ||
 286                      sctx->b.family == CHIP_MULLINS) &&
 287                     (tiled_x + copy_width == (1 << 14) ||
 288                      tiled_y + copy_height == (1 << 14)))
 289                         return false;
 290
 291                 /* The hw can read outside of the given linear buffer bounds,
 292                  * or access those pages but not touch the memory in case
 293                  * of writes. (it still causes a VM fault)
 294                  *
 295                  * Out-of-bounds memory access or page directory access must
 296                  * be prevented.
 297                  */
 298                 int64_t start_linear_address, end_linear_address;
 299                 unsigned granularity;
 300
 301                 /* Deduce the size of reads from the linear surface. */
 302                 switch (tiled_micro_mode) {
 303                 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING:
 304                         granularity = bpp == 1 ? 64 / (8*bpp) :
 305                                                  128 / (8*bpp);
 306                         break;
 307                 case V_009910_ADDR_SURF_THIN_MICRO_TILING:
 308                 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING:
 309                         if (0 /* TODO: THICK microtiling */)
 310                                 granularity = bpp == 1 ? 32 / (8*bpp) :
 311                                               bpp == 2 ? 64 / (8*bpp) :
 312                                               bpp <= 8 ? 128 / (8*bpp) :
 313                                                          256 / (8*bpp);
 314                         else
 315                                 granularity = bpp <= 2 ? 64 / (8*bpp) :
 316                                               bpp <= 8 ? 128 / (8*bpp) :
 317                                                          256 / (8*bpp);
 318                         break;
 319                 default:
 320                         return false;
 321                 }
 322
 323                 /* The linear reads start at tiled_x & ~(granularity - 1).
 324                  * If linear_x == 0 && tiled_x % granularity != 0, the hw
 325                  * starts reading from an address preceding linear_address!!!
 326                  */
 327                 start_linear_address =
 328                         linear->surface.level[linear_level].offset +
 329                         bpp * (linear_z * linear_slice_pitch +
 330                                linear_y * linear_pitch +
 331                                linear_x);
 332                 start_linear_address -= (int)(bpp * (tiled_x % granularity));
 333
 334                 end_linear_address =
 335                         linear->surface.level[linear_level].offset +
 336                         bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
 337                                (linear_y + copy_height - 1) * linear_pitch +
 338                                (linear_x + copy_width));
 339
 340                 if ((tiled_x + copy_width) % granularity)
 341                         end_linear_address += granularity -
 342                                               (tiled_x + copy_width) % granularity;
 343
 344                 if (start_linear_address < 0 ||
 345                     end_linear_address > linear->surface.surf_size)
 346                         return false;
 347
 348                 /* Check requirements. */
 349                 if (tiled_address % 256 == 0 &&
 350                     linear_address % 4 == 0 &&
 351                     linear_pitch % xalign == 0 &&
 352                     linear_x % xalign == 0 &&
 353                     tiled_x % xalign == 0 &&
 354                     copy_width_aligned % xalign == 0 &&
 355                     tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
 356                     /* check if everything fits into the bitfields */
 357                     tiled->surface.tile_split <= 4096 &&
 358                     pitch_tile_max < (1 << 11) &&
 359                     slice_tile_max < (1 << 22) &&
 360                     linear_pitch <= (1 << 14) &&
 361                     linear_slice_pitch <= (1 << 28) &&
 362                     copy_width_aligned <= (1 << 14) &&
 363                     copy_height <= (1 << 14) &&
 364                     copy_depth <= (1 << 11)) {
 365                         struct radeon_winsys_cs *cs = sctx->b.dma.cs;
 366                         uint32_t direction = linear == rdst ? 1u << 31 : 0;
 367
 368                         r600_need_dma_space(&sctx->b, 14, &rdst->resource, &rsrc->resource);
 369
 370                         radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
 371                                                         CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
 372                                         direction);
 373                         radeon_emit(cs, tiled_address);
 374                         radeon_emit(cs, tiled_address >> 32);
 375                         radeon_emit(cs, tiled_x | (tiled_y << 16));
 376                         radeon_emit(cs, tiled_z | (pitch_tile_max << 16));
 377                         radeon_emit(cs, slice_tile_max);
 378                         radeon_emit(cs, encode_tile_info(sctx, tiled, tiled_level, true));
 379                         radeon_emit(cs, linear_address);
 380                         radeon_emit(cs, linear_address >> 32);
 381                         radeon_emit(cs, linear_x | (linear_y << 16));
 382                         radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
 383                         radeon_emit(cs, linear_slice_pitch - 1);
 384                         if (sctx->b.chip_class == CIK) {
 385                                 radeon_emit(cs, copy_width_aligned | (copy_height << 16));
 386                                 radeon_emit(cs, copy_depth);
 387                         } else {
 388                                 radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16));
 389                                 radeon_emit(cs, (copy_depth - 1));
 390                         }
 391
 392                         r600_dma_emit_wait_idle(&sctx->b);
 393                         return true;
 394                 }
 395         }
 396
 397         /* Tiled -> Tiled sub-window copy. */
 398         if (dst_mode >= RADEON_SURF_MODE_1D &&
 399             src_mode >= RADEON_SURF_MODE_1D &&
 400             /* check if these fit into the bitfields */
 401             src_address % 256 == 0 &&
 402             dst_address % 256 == 0 &&
 403             rsrc->surface.tile_split <= 4096 &&
 404             rdst->surface.tile_split <= 4096 &&
 405             dstx % 8 == 0 &&
 406             dsty % 8 == 0 &&
 407             srcx % 8 == 0 &&
 408             srcy % 8 == 0 &&
 409             /* this can either be equal, or display->rotated (VI only) */
 410             (src_micro_mode == dst_micro_mode ||
 411              (sctx->b.chip_class == VI &&
 412               src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
 413               dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
 414                 assert(src_pitch % 8 == 0);
 415                 assert(dst_pitch % 8 == 0);
 416                 assert(src_slice_pitch % 64 == 0);
 417                 assert(dst_slice_pitch % 64 == 0);
 418                 unsigned src_pitch_tile_max = src_pitch / 8 - 1;
 419                 unsigned dst_pitch_tile_max = dst_pitch / 8 - 1;
 420                 unsigned src_slice_tile_max = src_slice_pitch / 64 - 1;
 421                 unsigned dst_slice_tile_max = dst_slice_pitch / 64 - 1;
 422                 unsigned copy_width_aligned = copy_width;
 423                 unsigned copy_height_aligned = copy_height;
 424
 425                 /* If the region ends at the last pixel and is unaligned, we
 426                  * can copy the remainder of the tile that is not visible to
 427                  * make it aligned.
 428                  */
 429                 if (copy_width % 8 != 0 &&
 430                     srcx + copy_width == src_width &&
 431                     dstx + copy_width == dst_width)
 432                         copy_width_aligned = align(copy_width, 8);
 433
 434                 if (copy_height % 8 != 0 &&
 435                     srcy + copy_height == src_height &&
 436                     dsty + copy_height == dst_height)
 437                         copy_height_aligned = align(copy_height, 8);
 438
 439                 /* check if these fit into the bitfields */
 440                 if (src_pitch_tile_max < (1 << 11) &&
 441                     dst_pitch_tile_max < (1 << 11) &&
 442                     src_slice_tile_max < (1 << 22) &&
 443                     dst_slice_tile_max < (1 << 22) &&
 444                     copy_width_aligned <= (1 << 14) &&
 445                     copy_height_aligned <= (1 << 14) &&
 446                     copy_depth <= (1 << 11) &&
 447                     copy_width_aligned % 8 == 0 &&
 448                     copy_height_aligned % 8 == 0 &&
 449                     /* HW limitation - CIK: */
 450                     (sctx->b.chip_class != CIK ||
 451                      (copy_width_aligned < (1 << 14) &&
 452                       copy_height_aligned < (1 << 14) &&
 453                       copy_depth < (1 << 11))) &&
 454                     /* HW limitation - some CIK parts: */
 455                     ((sctx->b.family != CHIP_BONAIRE &&
 456                       sctx->b.family != CHIP_KAVERI &&
 457                       sctx->b.family != CHIP_KABINI &&
 458                       sctx->b.family != CHIP_MULLINS) ||
 459                      (srcx + copy_width_aligned != (1 << 14) &&
 460                       srcy + copy_height_aligned != (1 << 14) &&
 461                       dstx + copy_width != (1 << 14)))) {
 462                         struct radeon_winsys_cs *cs = sctx->b.dma.cs;
 463
 464                         r600_need_dma_space(&sctx->b, 15, &rdst->resource, &rsrc->resource);
 465
 466                         radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
 467                                                         CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
 468                         radeon_emit(cs, src_address);
 469                         radeon_emit(cs, src_address >> 32);
 470                         radeon_emit(cs, srcx | (srcy << 16));
 471                         radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
 472                         radeon_emit(cs, src_slice_tile_max);
 473                         radeon_emit(cs, encode_tile_info(sctx, rsrc, src_level, true));
 474                         radeon_emit(cs, dst_address);
 475                         radeon_emit(cs, dst_address >> 32);
 476                         radeon_emit(cs, dstx | (dsty << 16));
 477                         radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
 478                         radeon_emit(cs, dst_slice_tile_max);
 479                         radeon_emit(cs, encode_tile_info(sctx, rdst, dst_level, false));
 480                         if (sctx->b.chip_class == CIK) {
 481                                 radeon_emit(cs, copy_width_aligned |
 482                                                 (copy_height_aligned << 16));
 483                                 radeon_emit(cs, copy_depth);
 484                         } else {
 485                                 radeon_emit(cs, (copy_width_aligned - 8) |
 486                                                 ((copy_height_aligned - 8) << 16));
 487                                 radeon_emit(cs, (copy_depth - 1));
 488                         }
 489
 490                         r600_dma_emit_wait_idle(&sctx->b);
 491                         return true;
 492                 }
 493         }
 494
 495         return false;
 496 }
 497
 498 static void cik_sdma_copy(struct pipe_context *ctx,
 499                           struct pipe_resource *dst,
 500                           unsigned dst_level,
 501                           unsigned dstx, unsigned dsty, unsigned dstz,
 502                           struct pipe_resource *src,
 503                           unsigned src_level,
 504                           const struct pipe_box *src_box)
 505 {
 506         struct si_context *sctx = (struct si_context *)ctx;
 507
 508         if (!sctx->b.dma.cs)
 509                 goto fallback;
 510
 511         if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 512                 cik_sdma_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
 513                 return;
 514         }
 515
 516         if (cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
 517                                   src, src_level, src_box))
 518                 return;
 519
 520 fallback:
 521         si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
 522                                 src, src_level, src_box);
 523 }
 524
 525 void cik_init_sdma_functions(struct si_context *sctx)
 526 {
 527         sctx->b.dma_copy = cik_sdma_copy;
 528 }