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radeonsi: update copyrights
[mesa.git] / src / gallium / drivers / radeonsi / cik_sdma.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2015 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "sid.h"
27 #include "si_pipe.h"
28
29 static void cik_sdma_copy_buffer(struct si_context *ctx,
30 struct pipe_resource *dst,
31 struct pipe_resource *src,
32 uint64_t dst_offset,
33 uint64_t src_offset,
34 uint64_t size)
35 {
36 struct radeon_winsys_cs *cs = ctx->b.dma_cs;
37 unsigned i, ncopy, csize;
38 struct r600_resource *rdst = r600_resource(dst);
39 struct r600_resource *rsrc = r600_resource(src);
40
41 /* Mark the buffer range of destination as valid (initialized),
42 * so that transfer_map knows it should wait for the GPU when mapping
43 * that range. */
44 util_range_add(&rdst->valid_buffer_range, dst_offset,
45 dst_offset + size);
46
47 dst_offset += rdst->gpu_address;
48 src_offset += rsrc->gpu_address;
49
50 ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
51 si_need_dma_space(ctx, ncopy * 7, rdst, rsrc);
52
53 for (i = 0; i < ncopy; i++) {
54 csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);
55 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
56 CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
57 0));
58 radeon_emit(cs, ctx->b.chip_class >= GFX9 ? csize - 1 : csize);
59 radeon_emit(cs, 0); /* src/dst endian swap */
60 radeon_emit(cs, src_offset);
61 radeon_emit(cs, src_offset >> 32);
62 radeon_emit(cs, dst_offset);
63 radeon_emit(cs, dst_offset >> 32);
64 dst_offset += csize;
65 src_offset += csize;
66 size -= csize;
67 }
68 }
69
70 static void cik_sdma_clear_buffer(struct pipe_context *ctx,
71 struct pipe_resource *dst,
72 uint64_t offset,
73 uint64_t size,
74 unsigned clear_value)
75 {
76 struct si_context *sctx = (struct si_context *)ctx;
77 struct radeon_winsys_cs *cs = sctx->b.dma_cs;
78 unsigned i, ncopy, csize;
79 struct r600_resource *rdst = r600_resource(dst);
80
81 if (!cs || offset % 4 != 0 || size % 4 != 0 ||
82 dst->flags & PIPE_RESOURCE_FLAG_SPARSE) {
83 ctx->clear_buffer(ctx, dst, offset, size, &clear_value, 4);
84 return;
85 }
86
87 /* Mark the buffer range of destination as valid (initialized),
88 * so that transfer_map knows it should wait for the GPU when mapping
89 * that range. */
90 util_range_add(&rdst->valid_buffer_range, offset, offset + size);
91
92 offset += rdst->gpu_address;
93
94 /* the same maximum size as for copying */
95 ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
96 si_need_dma_space(sctx, ncopy * 5, rdst, NULL);
97
98 for (i = 0; i < ncopy; i++) {
99 csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);
100 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_PACKET_CONSTANT_FILL, 0,
101 0x8000 /* dword copy */));
102 radeon_emit(cs, offset);
103 radeon_emit(cs, offset >> 32);
104 radeon_emit(cs, clear_value);
105 radeon_emit(cs, sctx->b.chip_class >= GFX9 ? csize - 1 : csize);
106 offset += csize;
107 size -= csize;
108 }
109 }
110
111 static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
112 {
113 width = u_minify(width, level);
114 return DIV_ROUND_UP(width, blk_w);
115 }
116
117 static unsigned encode_tile_info(struct si_context *sctx,
118 struct r600_texture *tex, unsigned level,
119 bool set_bpp)
120 {
121 struct radeon_info *info = &sctx->screen->info;
122 unsigned tile_index = tex->surface.u.legacy.tiling_index[level];
123 unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
124 unsigned tile_mode = info->si_tile_mode_array[tile_index];
125 unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
126
127 return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) |
128 (G_009910_ARRAY_MODE(tile_mode) << 3) |
129 (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
130 /* Non-depth modes don't have TILE_SPLIT set. */
131 ((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
132 (G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
133 (G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
134 (G_009990_NUM_BANKS(macro_tile_mode) << 21) |
135 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode) << 24) |
136 (G_009910_PIPE_CONFIG(tile_mode) << 26);
137 }
138
139 static bool cik_sdma_copy_texture(struct si_context *sctx,
140 struct pipe_resource *dst,
141 unsigned dst_level,
142 unsigned dstx, unsigned dsty, unsigned dstz,
143 struct pipe_resource *src,
144 unsigned src_level,
145 const struct pipe_box *src_box)
146 {
147 struct radeon_info *info = &sctx->screen->info;
148 struct r600_texture *rsrc = (struct r600_texture*)src;
149 struct r600_texture *rdst = (struct r600_texture*)dst;
150 unsigned bpp = rdst->surface.bpe;
151 uint64_t dst_address = rdst->resource.gpu_address +
152 rdst->surface.u.legacy.level[dst_level].offset;
153 uint64_t src_address = rsrc->resource.gpu_address +
154 rsrc->surface.u.legacy.level[src_level].offset;
155 unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
156 unsigned src_mode = rsrc->surface.u.legacy.level[src_level].mode;
157 unsigned dst_tile_index = rdst->surface.u.legacy.tiling_index[dst_level];
158 unsigned src_tile_index = rsrc->surface.u.legacy.tiling_index[src_level];
159 unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
160 unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
161 unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
162 unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
163 unsigned dst_tile_swizzle = dst_mode == RADEON_SURF_MODE_2D ?
164 rdst->surface.tile_swizzle : 0;
165 unsigned src_tile_swizzle = src_mode == RADEON_SURF_MODE_2D ?
166 rsrc->surface.tile_swizzle : 0;
167 unsigned dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x;
168 unsigned src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x;
169 uint64_t dst_slice_pitch = ((uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4) / bpp;
170 uint64_t src_slice_pitch = ((uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4) / bpp;
171 unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0,
172 dst_level, rdst->surface.blk_w);
173 unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0,
174 src_level, rsrc->surface.blk_w);
175 unsigned dst_height = minify_as_blocks(rdst->resource.b.b.height0,
176 dst_level, rdst->surface.blk_h);
177 unsigned src_height = minify_as_blocks(rsrc->resource.b.b.height0,
178 src_level, rsrc->surface.blk_h);
179 unsigned srcx = src_box->x / rsrc->surface.blk_w;
180 unsigned srcy = src_box->y / rsrc->surface.blk_h;
181 unsigned srcz = src_box->z;
182 unsigned copy_width = DIV_ROUND_UP(src_box->width, rsrc->surface.blk_w);
183 unsigned copy_height = DIV_ROUND_UP(src_box->height, rsrc->surface.blk_h);
184 unsigned copy_depth = src_box->depth;
185
186 assert(src_level <= src->last_level);
187 assert(dst_level <= dst->last_level);
188 assert(rdst->surface.u.legacy.level[dst_level].offset +
189 dst_slice_pitch * bpp * (dstz + src_box->depth) <=
190 rdst->resource.buf->size);
191 assert(rsrc->surface.u.legacy.level[src_level].offset +
192 src_slice_pitch * bpp * (srcz + src_box->depth) <=
193 rsrc->resource.buf->size);
194
195 if (!si_prepare_for_dma_blit(sctx, rdst, dst_level, dstx, dsty,
196 dstz, rsrc, src_level, src_box))
197 return false;
198
199 dstx /= rdst->surface.blk_w;
200 dsty /= rdst->surface.blk_h;
201
202 if (srcx >= (1 << 14) ||
203 srcy >= (1 << 14) ||
204 srcz >= (1 << 11) ||
205 dstx >= (1 << 14) ||
206 dsty >= (1 << 14) ||
207 dstz >= (1 << 11))
208 return false;
209
210 dst_address |= dst_tile_swizzle << 8;
211 src_address |= src_tile_swizzle << 8;
212
213 /* Linear -> linear sub-window copy. */
214 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
215 src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
216 /* check if everything fits into the bitfields */
217 src_pitch <= (1 << 14) &&
218 dst_pitch <= (1 << 14) &&
219 src_slice_pitch <= (1 << 28) &&
220 dst_slice_pitch <= (1 << 28) &&
221 copy_width <= (1 << 14) &&
222 copy_height <= (1 << 14) &&
223 copy_depth <= (1 << 11) &&
224 /* HW limitation - CIK: */
225 (sctx->b.chip_class != CIK ||
226 (copy_width < (1 << 14) &&
227 copy_height < (1 << 14) &&
228 copy_depth < (1 << 11))) &&
229 /* HW limitation - some CIK parts: */
230 ((sctx->b.family != CHIP_BONAIRE &&
231 sctx->b.family != CHIP_KAVERI) ||
232 (srcx + copy_width != (1 << 14) &&
233 srcy + copy_height != (1 << 14)))) {
234 struct radeon_winsys_cs *cs = sctx->b.dma_cs;
235
236 si_need_dma_space(sctx, 13, &rdst->resource, &rsrc->resource);
237
238 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
239 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
240 (util_logbase2(bpp) << 29));
241 radeon_emit(cs, src_address);
242 radeon_emit(cs, src_address >> 32);
243 radeon_emit(cs, srcx | (srcy << 16));
244 radeon_emit(cs, srcz | ((src_pitch - 1) << 16));
245 radeon_emit(cs, src_slice_pitch - 1);
246 radeon_emit(cs, dst_address);
247 radeon_emit(cs, dst_address >> 32);
248 radeon_emit(cs, dstx | (dsty << 16));
249 radeon_emit(cs, dstz | ((dst_pitch - 1) << 16));
250 radeon_emit(cs, dst_slice_pitch - 1);
251 if (sctx->b.chip_class == CIK) {
252 radeon_emit(cs, copy_width | (copy_height << 16));
253 radeon_emit(cs, copy_depth);
254 } else {
255 radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
256 radeon_emit(cs, (copy_depth - 1));
257 }
258 return true;
259 }
260
261 /* Tiled <-> linear sub-window copy. */
262 if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
263 struct r600_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? rsrc : rdst;
264 struct r600_texture *linear = tiled == rsrc ? rdst : rsrc;
265 unsigned tiled_level = tiled == rsrc ? src_level : dst_level;
266 unsigned linear_level = linear == rsrc ? src_level : dst_level;
267 unsigned tiled_x = tiled == rsrc ? srcx : dstx;
268 unsigned linear_x = linear == rsrc ? srcx : dstx;
269 unsigned tiled_y = tiled == rsrc ? srcy : dsty;
270 unsigned linear_y = linear == rsrc ? srcy : dsty;
271 unsigned tiled_z = tiled == rsrc ? srcz : dstz;
272 unsigned linear_z = linear == rsrc ? srcz : dstz;
273 unsigned tiled_width = tiled == rsrc ? src_width : dst_width;
274 unsigned linear_width = linear == rsrc ? src_width : dst_width;
275 unsigned tiled_pitch = tiled == rsrc ? src_pitch : dst_pitch;
276 unsigned linear_pitch = linear == rsrc ? src_pitch : dst_pitch;
277 unsigned tiled_slice_pitch = tiled == rsrc ? src_slice_pitch : dst_slice_pitch;
278 unsigned linear_slice_pitch = linear == rsrc ? src_slice_pitch : dst_slice_pitch;
279 uint64_t tiled_address = tiled == rsrc ? src_address : dst_address;
280 uint64_t linear_address = linear == rsrc ? src_address : dst_address;
281 unsigned tiled_micro_mode = tiled == rsrc ? src_micro_mode : dst_micro_mode;
282
283 assert(tiled_pitch % 8 == 0);
284 assert(tiled_slice_pitch % 64 == 0);
285 unsigned pitch_tile_max = tiled_pitch / 8 - 1;
286 unsigned slice_tile_max = tiled_slice_pitch / 64 - 1;
287 unsigned xalign = MAX2(1, 4 / bpp);
288 unsigned copy_width_aligned = copy_width;
289
290 /* If the region ends at the last pixel and is unaligned, we
291 * can copy the remainder of the line that is not visible to
292 * make it aligned.
293 */
294 if (copy_width % xalign != 0 &&
295 linear_x + copy_width == linear_width &&
296 tiled_x + copy_width == tiled_width &&
297 linear_x + align(copy_width, xalign) <= linear_pitch &&
298 tiled_x + align(copy_width, xalign) <= tiled_pitch)
299 copy_width_aligned = align(copy_width, xalign);
300
301 /* HW limitations. */
302 if ((sctx->b.family == CHIP_BONAIRE ||
303 sctx->b.family == CHIP_KAVERI) &&
304 linear_pitch - 1 == 0x3fff &&
305 bpp == 16)
306 return false;
307
308 if (sctx->b.chip_class == CIK &&
309 (copy_width_aligned == (1 << 14) ||
310 copy_height == (1 << 14) ||
311 copy_depth == (1 << 11)))
312 return false;
313
314 if ((sctx->b.family == CHIP_BONAIRE ||
315 sctx->b.family == CHIP_KAVERI ||
316 sctx->b.family == CHIP_KABINI ||
317 sctx->b.family == CHIP_MULLINS) &&
318 (tiled_x + copy_width == (1 << 14) ||
319 tiled_y + copy_height == (1 << 14)))
320 return false;
321
322 /* The hw can read outside of the given linear buffer bounds,
323 * or access those pages but not touch the memory in case
324 * of writes. (it still causes a VM fault)
325 *
326 * Out-of-bounds memory access or page directory access must
327 * be prevented.
328 */
329 int64_t start_linear_address, end_linear_address;
330 unsigned granularity;
331
332 /* Deduce the size of reads from the linear surface. */
333 switch (tiled_micro_mode) {
334 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING:
335 granularity = bpp == 1 ? 64 / (8*bpp) :
336 128 / (8*bpp);
337 break;
338 case V_009910_ADDR_SURF_THIN_MICRO_TILING:
339 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING:
340 if (0 /* TODO: THICK microtiling */)
341 granularity = bpp == 1 ? 32 / (8*bpp) :
342 bpp == 2 ? 64 / (8*bpp) :
343 bpp <= 8 ? 128 / (8*bpp) :
344 256 / (8*bpp);
345 else
346 granularity = bpp <= 2 ? 64 / (8*bpp) :
347 bpp <= 8 ? 128 / (8*bpp) :
348 256 / (8*bpp);
349 break;
350 default:
351 return false;
352 }
353
354 /* The linear reads start at tiled_x & ~(granularity - 1).
355 * If linear_x == 0 && tiled_x % granularity != 0, the hw
356 * starts reading from an address preceding linear_address!!!
357 */
358 start_linear_address =
359 linear->surface.u.legacy.level[linear_level].offset +
360 bpp * (linear_z * linear_slice_pitch +
361 linear_y * linear_pitch +
362 linear_x);
363 start_linear_address -= (int)(bpp * (tiled_x % granularity));
364
365 end_linear_address =
366 linear->surface.u.legacy.level[linear_level].offset +
367 bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
368 (linear_y + copy_height - 1) * linear_pitch +
369 (linear_x + copy_width));
370
371 if ((tiled_x + copy_width) % granularity)
372 end_linear_address += granularity -
373 (tiled_x + copy_width) % granularity;
374
375 if (start_linear_address < 0 ||
376 end_linear_address > linear->surface.surf_size)
377 return false;
378
379 /* Check requirements. */
380 if (tiled_address % 256 == 0 &&
381 linear_address % 4 == 0 &&
382 linear_pitch % xalign == 0 &&
383 linear_x % xalign == 0 &&
384 tiled_x % xalign == 0 &&
385 copy_width_aligned % xalign == 0 &&
386 tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
387 /* check if everything fits into the bitfields */
388 tiled->surface.u.legacy.tile_split <= 4096 &&
389 pitch_tile_max < (1 << 11) &&
390 slice_tile_max < (1 << 22) &&
391 linear_pitch <= (1 << 14) &&
392 linear_slice_pitch <= (1 << 28) &&
393 copy_width_aligned <= (1 << 14) &&
394 copy_height <= (1 << 14) &&
395 copy_depth <= (1 << 11)) {
396 struct radeon_winsys_cs *cs = sctx->b.dma_cs;
397 uint32_t direction = linear == rdst ? 1u << 31 : 0;
398
399 si_need_dma_space(sctx, 14, &rdst->resource, &rsrc->resource);
400
401 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
402 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
403 direction);
404 radeon_emit(cs, tiled_address);
405 radeon_emit(cs, tiled_address >> 32);
406 radeon_emit(cs, tiled_x | (tiled_y << 16));
407 radeon_emit(cs, tiled_z | (pitch_tile_max << 16));
408 radeon_emit(cs, slice_tile_max);
409 radeon_emit(cs, encode_tile_info(sctx, tiled, tiled_level, true));
410 radeon_emit(cs, linear_address);
411 radeon_emit(cs, linear_address >> 32);
412 radeon_emit(cs, linear_x | (linear_y << 16));
413 radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
414 radeon_emit(cs, linear_slice_pitch - 1);
415 if (sctx->b.chip_class == CIK) {
416 radeon_emit(cs, copy_width_aligned | (copy_height << 16));
417 radeon_emit(cs, copy_depth);
418 } else {
419 radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16));
420 radeon_emit(cs, (copy_depth - 1));
421 }
422 return true;
423 }
424 }
425
426 /* Tiled -> Tiled sub-window copy. */
427 if (dst_mode >= RADEON_SURF_MODE_1D &&
428 src_mode >= RADEON_SURF_MODE_1D &&
429 /* check if these fit into the bitfields */
430 src_address % 256 == 0 &&
431 dst_address % 256 == 0 &&
432 rsrc->surface.u.legacy.tile_split <= 4096 &&
433 rdst->surface.u.legacy.tile_split <= 4096 &&
434 dstx % 8 == 0 &&
435 dsty % 8 == 0 &&
436 srcx % 8 == 0 &&
437 srcy % 8 == 0 &&
438 /* this can either be equal, or display->rotated (VI+ only) */
439 (src_micro_mode == dst_micro_mode ||
440 (sctx->b.chip_class >= VI &&
441 src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
442 dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
443 assert(src_pitch % 8 == 0);
444 assert(dst_pitch % 8 == 0);
445 assert(src_slice_pitch % 64 == 0);
446 assert(dst_slice_pitch % 64 == 0);
447 unsigned src_pitch_tile_max = src_pitch / 8 - 1;
448 unsigned dst_pitch_tile_max = dst_pitch / 8 - 1;
449 unsigned src_slice_tile_max = src_slice_pitch / 64 - 1;
450 unsigned dst_slice_tile_max = dst_slice_pitch / 64 - 1;
451 unsigned copy_width_aligned = copy_width;
452 unsigned copy_height_aligned = copy_height;
453
454 /* If the region ends at the last pixel and is unaligned, we
455 * can copy the remainder of the tile that is not visible to
456 * make it aligned.
457 */
458 if (copy_width % 8 != 0 &&
459 srcx + copy_width == src_width &&
460 dstx + copy_width == dst_width)
461 copy_width_aligned = align(copy_width, 8);
462
463 if (copy_height % 8 != 0 &&
464 srcy + copy_height == src_height &&
465 dsty + copy_height == dst_height)
466 copy_height_aligned = align(copy_height, 8);
467
468 /* check if these fit into the bitfields */
469 if (src_pitch_tile_max < (1 << 11) &&
470 dst_pitch_tile_max < (1 << 11) &&
471 src_slice_tile_max < (1 << 22) &&
472 dst_slice_tile_max < (1 << 22) &&
473 copy_width_aligned <= (1 << 14) &&
474 copy_height_aligned <= (1 << 14) &&
475 copy_depth <= (1 << 11) &&
476 copy_width_aligned % 8 == 0 &&
477 copy_height_aligned % 8 == 0 &&
478 /* HW limitation - CIK: */
479 (sctx->b.chip_class != CIK ||
480 (copy_width_aligned < (1 << 14) &&
481 copy_height_aligned < (1 << 14) &&
482 copy_depth < (1 << 11))) &&
483 /* HW limitation - some CIK parts: */
484 ((sctx->b.family != CHIP_BONAIRE &&
485 sctx->b.family != CHIP_KAVERI &&
486 sctx->b.family != CHIP_KABINI &&
487 sctx->b.family != CHIP_MULLINS) ||
488 (srcx + copy_width_aligned != (1 << 14) &&
489 srcy + copy_height_aligned != (1 << 14) &&
490 dstx + copy_width != (1 << 14)))) {
491 struct radeon_winsys_cs *cs = sctx->b.dma_cs;
492
493 si_need_dma_space(sctx, 15, &rdst->resource, &rsrc->resource);
494
495 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
496 CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
497 radeon_emit(cs, src_address);
498 radeon_emit(cs, src_address >> 32);
499 radeon_emit(cs, srcx | (srcy << 16));
500 radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
501 radeon_emit(cs, src_slice_tile_max);
502 radeon_emit(cs, encode_tile_info(sctx, rsrc, src_level, true));
503 radeon_emit(cs, dst_address);
504 radeon_emit(cs, dst_address >> 32);
505 radeon_emit(cs, dstx | (dsty << 16));
506 radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
507 radeon_emit(cs, dst_slice_tile_max);
508 radeon_emit(cs, encode_tile_info(sctx, rdst, dst_level, false));
509 if (sctx->b.chip_class == CIK) {
510 radeon_emit(cs, copy_width_aligned |
511 (copy_height_aligned << 16));
512 radeon_emit(cs, copy_depth);
513 } else {
514 radeon_emit(cs, (copy_width_aligned - 8) |
515 ((copy_height_aligned - 8) << 16));
516 radeon_emit(cs, (copy_depth - 1));
517 }
518 return true;
519 }
520 }
521
522 return false;
523 }
524
525 static void cik_sdma_copy(struct pipe_context *ctx,
526 struct pipe_resource *dst,
527 unsigned dst_level,
528 unsigned dstx, unsigned dsty, unsigned dstz,
529 struct pipe_resource *src,
530 unsigned src_level,
531 const struct pipe_box *src_box)
532 {
533 struct si_context *sctx = (struct si_context *)ctx;
534
535 if (!sctx->b.dma_cs ||
536 src->flags & PIPE_RESOURCE_FLAG_SPARSE ||
537 dst->flags & PIPE_RESOURCE_FLAG_SPARSE)
538 goto fallback;
539
540 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
541 cik_sdma_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
542 return;
543 }
544
545 if ((sctx->b.chip_class == CIK || sctx->b.chip_class == VI) &&
546 cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
547 src, src_level, src_box))
548 return;
549
550 fallback:
551 si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
552 src, src_level, src_box);
553 }
554
555 void cik_init_sdma_functions(struct si_context *sctx)
556 {
557 sctx->b.dma_copy = cik_sdma_copy;
558 sctx->b.dma_clear_buffer = cik_sdma_clear_buffer;
559 }