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radeonsi: remove unnecessary #includes
[mesa.git] / src / gallium / drivers / radeonsi / cik_sdma.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014,2015 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse
26 */
27
28 #include "sid.h"
29 #include "si_pipe.h"
30
31 static void cik_sdma_do_copy_buffer(struct si_context *ctx,
32 struct pipe_resource *dst,
33 struct pipe_resource *src,
34 uint64_t dst_offset,
35 uint64_t src_offset,
36 uint64_t size)
37 {
38 struct radeon_winsys_cs *cs = ctx->b.dma.cs;
39 unsigned i, ncopy, csize;
40 struct r600_resource *rdst = (struct r600_resource*)dst;
41 struct r600_resource *rsrc = (struct r600_resource*)src;
42
43 dst_offset += r600_resource(dst)->gpu_address;
44 src_offset += r600_resource(src)->gpu_address;
45
46 ncopy = DIV_ROUND_UP(size, CIK_SDMA_COPY_MAX_SIZE);
47 r600_need_dma_space(&ctx->b, ncopy * 7, rdst, rsrc);
48
49 for (i = 0; i < ncopy; i++) {
50 csize = MIN2(size, CIK_SDMA_COPY_MAX_SIZE);
51 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
52 CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
53 0));
54 radeon_emit(cs, csize);
55 radeon_emit(cs, 0); /* src/dst endian swap */
56 radeon_emit(cs, src_offset);
57 radeon_emit(cs, src_offset >> 32);
58 radeon_emit(cs, dst_offset);
59 radeon_emit(cs, dst_offset >> 32);
60 dst_offset += csize;
61 src_offset += csize;
62 size -= csize;
63 }
64 }
65
66 static void cik_sdma_copy_buffer(struct si_context *ctx,
67 struct pipe_resource *dst,
68 struct pipe_resource *src,
69 uint64_t dst_offset,
70 uint64_t src_offset,
71 uint64_t size)
72 {
73 struct r600_resource *rdst = (struct r600_resource*)dst;
74
75 /* Mark the buffer range of destination as valid (initialized),
76 * so that transfer_map knows it should wait for the GPU when mapping
77 * that range. */
78 util_range_add(&rdst->valid_buffer_range, dst_offset,
79 dst_offset + size);
80
81 cik_sdma_do_copy_buffer(ctx, dst, src, dst_offset, src_offset, size);
82 r600_dma_emit_wait_idle(&ctx->b);
83 }
84
85 static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
86 {
87 width = u_minify(width, level);
88 return DIV_ROUND_UP(width, blk_w);
89 }
90
91 static unsigned encode_tile_info(struct si_context *sctx,
92 struct r600_texture *tex, unsigned level,
93 bool set_bpp)
94 {
95 struct radeon_info *info = &sctx->screen->b.info;
96 unsigned tile_index = tex->surface.tiling_index[level];
97 unsigned macro_tile_index = tex->surface.macro_tile_index;
98 unsigned tile_mode = info->si_tile_mode_array[tile_index];
99 unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
100
101 return (set_bpp ? util_logbase2(tex->surface.bpe) : 0) |
102 (G_009910_ARRAY_MODE(tile_mode) << 3) |
103 (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
104 /* Non-depth modes don't have TILE_SPLIT set. */
105 ((util_logbase2(tex->surface.tile_split >> 6)) << 11) |
106 (G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
107 (G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
108 (G_009990_NUM_BANKS(macro_tile_mode) << 21) |
109 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode) << 24) |
110 (G_009910_PIPE_CONFIG(tile_mode) << 26);
111 }
112
113 static bool cik_sdma_copy_texture(struct si_context *sctx,
114 struct pipe_resource *dst,
115 unsigned dst_level,
116 unsigned dstx, unsigned dsty, unsigned dstz,
117 struct pipe_resource *src,
118 unsigned src_level,
119 const struct pipe_box *src_box)
120 {
121 struct radeon_info *info = &sctx->screen->b.info;
122 struct r600_texture *rsrc = (struct r600_texture*)src;
123 struct r600_texture *rdst = (struct r600_texture*)dst;
124 unsigned bpp = rdst->surface.bpe;
125 uint64_t dst_address = rdst->resource.gpu_address +
126 rdst->surface.level[dst_level].offset;
127 uint64_t src_address = rsrc->resource.gpu_address +
128 rsrc->surface.level[src_level].offset;
129 unsigned dst_mode = rdst->surface.level[dst_level].mode;
130 unsigned src_mode = rsrc->surface.level[src_level].mode;
131 unsigned dst_tile_index = rdst->surface.tiling_index[dst_level];
132 unsigned src_tile_index = rsrc->surface.tiling_index[src_level];
133 unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
134 unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
135 unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
136 unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
137 unsigned dst_pitch = rdst->surface.level[dst_level].pitch_bytes / bpp;
138 unsigned src_pitch = rsrc->surface.level[src_level].pitch_bytes / bpp;
139 uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp;
140 uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp;
141 unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0,
142 dst_level, rdst->surface.blk_w);
143 unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0,
144 src_level, rsrc->surface.blk_w);
145 unsigned dst_height = minify_as_blocks(rdst->resource.b.b.height0,
146 dst_level, rdst->surface.blk_h);
147 unsigned src_height = minify_as_blocks(rsrc->resource.b.b.height0,
148 src_level, rsrc->surface.blk_h);
149 unsigned srcx = src_box->x / rsrc->surface.blk_w;
150 unsigned srcy = src_box->y / rsrc->surface.blk_h;
151 unsigned srcz = src_box->z;
152 unsigned copy_width = DIV_ROUND_UP(src_box->width, rsrc->surface.blk_w);
153 unsigned copy_height = DIV_ROUND_UP(src_box->height, rsrc->surface.blk_h);
154 unsigned copy_depth = src_box->depth;
155
156 assert(src_level <= src->last_level);
157 assert(dst_level <= dst->last_level);
158 assert(rdst->surface.level[dst_level].offset +
159 dst_slice_pitch * bpp * (dstz + src_box->depth) <=
160 rdst->resource.buf->size);
161 assert(rsrc->surface.level[src_level].offset +
162 src_slice_pitch * bpp * (srcz + src_box->depth) <=
163 rsrc->resource.buf->size);
164
165 /* Test CIK with radeon and amdgpu before enabling this. */
166 if (sctx->b.chip_class == CIK)
167 return false;
168
169 if (!r600_prepare_for_dma_blit(&sctx->b, rdst, dst_level, dstx, dsty,
170 dstz, rsrc, src_level, src_box))
171 return false;
172
173 dstx /= rdst->surface.blk_w;
174 dsty /= rdst->surface.blk_h;
175
176 if (srcx >= (1 << 14) ||
177 srcy >= (1 << 14) ||
178 srcz >= (1 << 11) ||
179 dstx >= (1 << 14) ||
180 dsty >= (1 << 14) ||
181 dstz >= (1 << 11))
182 return false;
183
184 /* Linear -> linear sub-window copy. */
185 if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
186 src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
187 /* check if everything fits into the bitfields */
188 src_pitch <= (1 << 14) &&
189 dst_pitch <= (1 << 14) &&
190 src_slice_pitch <= (1 << 28) &&
191 dst_slice_pitch <= (1 << 28) &&
192 copy_width <= (1 << 14) &&
193 copy_height <= (1 << 14) &&
194 copy_depth <= (1 << 11) &&
195 /* HW limitation - CIK: */
196 (sctx->b.chip_class != CIK ||
197 (copy_width < (1 << 14) &&
198 copy_height < (1 << 14) &&
199 copy_depth < (1 << 11))) &&
200 /* HW limitation - some CIK parts: */
201 ((sctx->b.family != CHIP_BONAIRE &&
202 sctx->b.family != CHIP_KAVERI) ||
203 (srcx + copy_width != (1 << 14) &&
204 srcy + copy_height != (1 << 14)))) {
205 struct radeon_winsys_cs *cs = sctx->b.dma.cs;
206
207 r600_need_dma_space(&sctx->b, 13, &rdst->resource, &rsrc->resource);
208
209 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
210 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
211 (util_logbase2(bpp) << 29));
212 radeon_emit(cs, src_address);
213 radeon_emit(cs, src_address >> 32);
214 radeon_emit(cs, srcx | (srcy << 16));
215 radeon_emit(cs, srcz | ((src_pitch - 1) << 16));
216 radeon_emit(cs, src_slice_pitch - 1);
217 radeon_emit(cs, dst_address);
218 radeon_emit(cs, dst_address >> 32);
219 radeon_emit(cs, dstx | (dsty << 16));
220 radeon_emit(cs, dstz | ((dst_pitch - 1) << 16));
221 radeon_emit(cs, dst_slice_pitch - 1);
222 if (sctx->b.chip_class == CIK) {
223 radeon_emit(cs, copy_width | (copy_height << 16));
224 radeon_emit(cs, copy_depth);
225 } else {
226 radeon_emit(cs, (copy_width - 1) | ((copy_height - 1) << 16));
227 radeon_emit(cs, (copy_depth - 1));
228 }
229
230 r600_dma_emit_wait_idle(&sctx->b);
231 return true;
232 }
233
234 /* Tiled <-> linear sub-window copy. */
235 if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
236 struct r600_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? rsrc : rdst;
237 struct r600_texture *linear = tiled == rsrc ? rdst : rsrc;
238 unsigned tiled_level = tiled == rsrc ? src_level : dst_level;
239 unsigned linear_level = linear == rsrc ? src_level : dst_level;
240 unsigned tiled_x = tiled == rsrc ? srcx : dstx;
241 unsigned linear_x = linear == rsrc ? srcx : dstx;
242 unsigned tiled_y = tiled == rsrc ? srcy : dsty;
243 unsigned linear_y = linear == rsrc ? srcy : dsty;
244 unsigned tiled_z = tiled == rsrc ? srcz : dstz;
245 unsigned linear_z = linear == rsrc ? srcz : dstz;
246 unsigned tiled_width = tiled == rsrc ? src_width : dst_width;
247 unsigned linear_width = linear == rsrc ? src_width : dst_width;
248 unsigned tiled_pitch = tiled == rsrc ? src_pitch : dst_pitch;
249 unsigned linear_pitch = linear == rsrc ? src_pitch : dst_pitch;
250 unsigned tiled_slice_pitch = tiled == rsrc ? src_slice_pitch : dst_slice_pitch;
251 unsigned linear_slice_pitch = linear == rsrc ? src_slice_pitch : dst_slice_pitch;
252 uint64_t tiled_address = tiled == rsrc ? src_address : dst_address;
253 uint64_t linear_address = linear == rsrc ? src_address : dst_address;
254 unsigned tiled_micro_mode = tiled == rsrc ? src_micro_mode : dst_micro_mode;
255
256 assert(tiled_pitch % 8 == 0);
257 assert(tiled_slice_pitch % 64 == 0);
258 unsigned pitch_tile_max = tiled_pitch / 8 - 1;
259 unsigned slice_tile_max = tiled_slice_pitch / 64 - 1;
260 unsigned xalign = MAX2(1, 4 / bpp);
261 unsigned copy_width_aligned = copy_width;
262
263 /* If the region ends at the last pixel and is unaligned, we
264 * can copy the remainder of the line that is not visible to
265 * make it aligned.
266 */
267 if (copy_width % xalign != 0 &&
268 linear_x + copy_width == linear_width &&
269 tiled_x + copy_width == tiled_width &&
270 linear_x + align(copy_width, xalign) <= linear_pitch &&
271 tiled_x + align(copy_width, xalign) <= tiled_pitch)
272 copy_width_aligned = align(copy_width, xalign);
273
274 /* HW limitations. */
275 if ((sctx->b.family == CHIP_BONAIRE ||
276 sctx->b.family == CHIP_KAVERI) &&
277 linear_pitch - 1 == 0x3fff &&
278 bpp == 16)
279 return false;
280
281 if (sctx->b.chip_class == CIK &&
282 (copy_width_aligned == (1 << 14) ||
283 copy_height == (1 << 14) ||
284 copy_depth == (1 << 11)))
285 return false;
286
287 if ((sctx->b.family == CHIP_BONAIRE ||
288 sctx->b.family == CHIP_KAVERI ||
289 sctx->b.family == CHIP_KABINI ||
290 sctx->b.family == CHIP_MULLINS) &&
291 (tiled_x + copy_width == (1 << 14) ||
292 tiled_y + copy_height == (1 << 14)))
293 return false;
294
295 /* The hw can read outside of the given linear buffer bounds,
296 * or access those pages but not touch the memory in case
297 * of writes. (it still causes a VM fault)
298 *
299 * Out-of-bounds memory access or page directory access must
300 * be prevented.
301 */
302 int64_t start_linear_address, end_linear_address;
303 unsigned granularity;
304
305 /* Deduce the size of reads from the linear surface. */
306 switch (tiled_micro_mode) {
307 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING:
308 granularity = bpp == 1 ? 64 / (8*bpp) :
309 128 / (8*bpp);
310 break;
311 case V_009910_ADDR_SURF_THIN_MICRO_TILING:
312 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING:
313 if (0 /* TODO: THICK microtiling */)
314 granularity = bpp == 1 ? 32 / (8*bpp) :
315 bpp == 2 ? 64 / (8*bpp) :
316 bpp <= 8 ? 128 / (8*bpp) :
317 256 / (8*bpp);
318 else
319 granularity = bpp <= 2 ? 64 / (8*bpp) :
320 bpp <= 8 ? 128 / (8*bpp) :
321 256 / (8*bpp);
322 break;
323 default:
324 return false;
325 }
326
327 /* The linear reads start at tiled_x & ~(granularity - 1).
328 * If linear_x == 0 && tiled_x % granularity != 0, the hw
329 * starts reading from an address preceding linear_address!!!
330 */
331 start_linear_address =
332 linear->surface.level[linear_level].offset +
333 bpp * (linear_z * linear_slice_pitch +
334 linear_y * linear_pitch +
335 linear_x);
336 start_linear_address -= (int)(bpp * (tiled_x % granularity));
337
338 end_linear_address =
339 linear->surface.level[linear_level].offset +
340 bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
341 (linear_y + copy_height - 1) * linear_pitch +
342 (linear_x + copy_width));
343
344 if ((tiled_x + copy_width) % granularity)
345 end_linear_address += granularity -
346 (tiled_x + copy_width) % granularity;
347
348 if (start_linear_address < 0 ||
349 end_linear_address > linear->surface.bo_size)
350 return false;
351
352 /* Check requirements. */
353 if (tiled_address % 256 == 0 &&
354 linear_address % 4 == 0 &&
355 linear_pitch % xalign == 0 &&
356 linear_x % xalign == 0 &&
357 tiled_x % xalign == 0 &&
358 copy_width_aligned % xalign == 0 &&
359 tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
360 /* check if everything fits into the bitfields */
361 tiled->surface.tile_split <= 4096 &&
362 pitch_tile_max < (1 << 11) &&
363 slice_tile_max < (1 << 22) &&
364 linear_pitch <= (1 << 14) &&
365 linear_slice_pitch <= (1 << 28) &&
366 copy_width_aligned <= (1 << 14) &&
367 copy_height <= (1 << 14) &&
368 copy_depth <= (1 << 11)) {
369 struct radeon_winsys_cs *cs = sctx->b.dma.cs;
370 uint32_t direction = linear == rdst ? 1u << 31 : 0;
371
372 r600_need_dma_space(&sctx->b, 14, &rdst->resource, &rsrc->resource);
373
374 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
375 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
376 direction);
377 radeon_emit(cs, tiled_address);
378 radeon_emit(cs, tiled_address >> 32);
379 radeon_emit(cs, tiled_x | (tiled_y << 16));
380 radeon_emit(cs, tiled_z | (pitch_tile_max << 16));
381 radeon_emit(cs, slice_tile_max);
382 radeon_emit(cs, encode_tile_info(sctx, tiled, tiled_level, true));
383 radeon_emit(cs, linear_address);
384 radeon_emit(cs, linear_address >> 32);
385 radeon_emit(cs, linear_x | (linear_y << 16));
386 radeon_emit(cs, linear_z | ((linear_pitch - 1) << 16));
387 radeon_emit(cs, linear_slice_pitch - 1);
388 if (sctx->b.chip_class == CIK) {
389 radeon_emit(cs, copy_width_aligned | (copy_height << 16));
390 radeon_emit(cs, copy_depth);
391 } else {
392 radeon_emit(cs, (copy_width_aligned - 1) | ((copy_height - 1) << 16));
393 radeon_emit(cs, (copy_depth - 1));
394 }
395
396 r600_dma_emit_wait_idle(&sctx->b);
397 return true;
398 }
399 }
400
401 /* Tiled -> Tiled sub-window copy. */
402 if (dst_mode >= RADEON_SURF_MODE_1D &&
403 src_mode >= RADEON_SURF_MODE_1D &&
404 /* check if these fit into the bitfields */
405 src_address % 256 == 0 &&
406 dst_address % 256 == 0 &&
407 rsrc->surface.tile_split <= 4096 &&
408 rdst->surface.tile_split <= 4096 &&
409 dstx % 8 == 0 &&
410 dsty % 8 == 0 &&
411 srcx % 8 == 0 &&
412 srcy % 8 == 0 &&
413 /* this can either be equal, or display->rotated (VI only) */
414 (src_micro_mode == dst_micro_mode ||
415 (sctx->b.chip_class == VI &&
416 src_micro_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING &&
417 dst_micro_mode == V_009910_ADDR_SURF_ROTATED_MICRO_TILING))) {
418 assert(src_pitch % 8 == 0);
419 assert(dst_pitch % 8 == 0);
420 assert(src_slice_pitch % 64 == 0);
421 assert(dst_slice_pitch % 64 == 0);
422 unsigned src_pitch_tile_max = src_pitch / 8 - 1;
423 unsigned dst_pitch_tile_max = dst_pitch / 8 - 1;
424 unsigned src_slice_tile_max = src_slice_pitch / 64 - 1;
425 unsigned dst_slice_tile_max = dst_slice_pitch / 64 - 1;
426 unsigned copy_width_aligned = copy_width;
427 unsigned copy_height_aligned = copy_height;
428
429 /* If the region ends at the last pixel and is unaligned, we
430 * can copy the remainder of the tile that is not visible to
431 * make it aligned.
432 */
433 if (copy_width % 8 != 0 &&
434 srcx + copy_width == src_width &&
435 dstx + copy_width == dst_width)
436 copy_width_aligned = align(copy_width, 8);
437
438 if (copy_height % 8 != 0 &&
439 srcy + copy_height == src_height &&
440 dsty + copy_height == dst_height)
441 copy_height_aligned = align(copy_height, 8);
442
443 /* check if these fit into the bitfields */
444 if (src_pitch_tile_max < (1 << 11) &&
445 dst_pitch_tile_max < (1 << 11) &&
446 src_slice_tile_max < (1 << 22) &&
447 dst_slice_tile_max < (1 << 22) &&
448 copy_width_aligned <= (1 << 14) &&
449 copy_height_aligned <= (1 << 14) &&
450 copy_depth <= (1 << 11) &&
451 copy_width_aligned % 8 == 0 &&
452 copy_height_aligned % 8 == 0 &&
453 /* HW limitation - CIK: */
454 (sctx->b.chip_class != CIK ||
455 (copy_width_aligned < (1 << 14) &&
456 copy_height_aligned < (1 << 14) &&
457 copy_depth < (1 << 11))) &&
458 /* HW limitation - some CIK parts: */
459 ((sctx->b.family != CHIP_BONAIRE &&
460 sctx->b.family != CHIP_KAVERI &&
461 sctx->b.family != CHIP_KABINI &&
462 sctx->b.family != CHIP_MULLINS) ||
463 (srcx + copy_width_aligned != (1 << 14) &&
464 srcy + copy_height_aligned != (1 << 14) &&
465 dstx + copy_width != (1 << 14)))) {
466 struct radeon_winsys_cs *cs = sctx->b.dma.cs;
467
468 r600_need_dma_space(&sctx->b, 15, &rdst->resource, &rsrc->resource);
469
470 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
471 CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
472 radeon_emit(cs, src_address);
473 radeon_emit(cs, src_address >> 32);
474 radeon_emit(cs, srcx | (srcy << 16));
475 radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
476 radeon_emit(cs, src_slice_tile_max);
477 radeon_emit(cs, encode_tile_info(sctx, rsrc, src_level, true));
478 radeon_emit(cs, dst_address);
479 radeon_emit(cs, dst_address >> 32);
480 radeon_emit(cs, dstx | (dsty << 16));
481 radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
482 radeon_emit(cs, dst_slice_tile_max);
483 radeon_emit(cs, encode_tile_info(sctx, rdst, dst_level, false));
484 if (sctx->b.chip_class == CIK) {
485 radeon_emit(cs, copy_width_aligned |
486 (copy_height_aligned << 16));
487 radeon_emit(cs, copy_depth);
488 } else {
489 radeon_emit(cs, (copy_width_aligned - 8) |
490 ((copy_height_aligned - 8) << 16));
491 radeon_emit(cs, (copy_depth - 1));
492 }
493
494 r600_dma_emit_wait_idle(&sctx->b);
495 return true;
496 }
497 }
498
499 return false;
500 }
501
502 static void cik_sdma_copy(struct pipe_context *ctx,
503 struct pipe_resource *dst,
504 unsigned dst_level,
505 unsigned dstx, unsigned dsty, unsigned dstz,
506 struct pipe_resource *src,
507 unsigned src_level,
508 const struct pipe_box *src_box)
509 {
510 struct si_context *sctx = (struct si_context *)ctx;
511
512 if (!sctx->b.dma.cs)
513 goto fallback;
514
515 if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
516 cik_sdma_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
517 return;
518 }
519
520 /* Carrizo SDMA texture copying is very broken for some users.
521 * https://bugs.freedesktop.org/show_bug.cgi?id=97029
522 */
523 if (sctx->b.family == CHIP_CARRIZO)
524 goto fallback;
525
526 if (cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
527 src, src_level, src_box))
528 return;
529
530 fallback:
531 si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
532 src, src_level, src_box);
533 }
534
535 void cik_init_sdma_functions(struct si_context *sctx)
536 {
537 sctx->b.dma_copy = cik_sdma_copy;
538 }