2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014,2015 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
31 static void cik_sdma_do_copy_buffer(struct si_context
*ctx
,
32 struct pipe_resource
*dst
,
33 struct pipe_resource
*src
,
38 struct radeon_winsys_cs
*cs
= ctx
->b
.dma
.cs
;
39 unsigned i
, ncopy
, csize
;
40 struct r600_resource
*rdst
= (struct r600_resource
*)dst
;
41 struct r600_resource
*rsrc
= (struct r600_resource
*)src
;
43 dst_offset
+= r600_resource(dst
)->gpu_address
;
44 src_offset
+= r600_resource(src
)->gpu_address
;
46 ncopy
= DIV_ROUND_UP(size
, CIK_SDMA_COPY_MAX_SIZE
);
47 r600_need_dma_space(&ctx
->b
, ncopy
* 7, rdst
, rsrc
);
49 for (i
= 0; i
< ncopy
; i
++) {
50 csize
= MIN2(size
, CIK_SDMA_COPY_MAX_SIZE
);
51 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
52 CIK_SDMA_COPY_SUB_OPCODE_LINEAR
,
54 radeon_emit(cs
, csize
);
55 radeon_emit(cs
, 0); /* src/dst endian swap */
56 radeon_emit(cs
, src_offset
);
57 radeon_emit(cs
, src_offset
>> 32);
58 radeon_emit(cs
, dst_offset
);
59 radeon_emit(cs
, dst_offset
>> 32);
66 static void cik_sdma_copy_buffer(struct si_context
*ctx
,
67 struct pipe_resource
*dst
,
68 struct pipe_resource
*src
,
73 struct r600_resource
*rdst
= (struct r600_resource
*)dst
;
75 /* Mark the buffer range of destination as valid (initialized),
76 * so that transfer_map knows it should wait for the GPU when mapping
78 util_range_add(&rdst
->valid_buffer_range
, dst_offset
,
81 cik_sdma_do_copy_buffer(ctx
, dst
, src
, dst_offset
, src_offset
, size
);
82 r600_dma_emit_wait_idle(&ctx
->b
);
85 static void cik_sdma_clear_buffer(struct pipe_context
*ctx
,
86 struct pipe_resource
*dst
,
91 struct si_context
*sctx
= (struct si_context
*)ctx
;
92 struct radeon_winsys_cs
*cs
= sctx
->b
.dma
.cs
;
93 unsigned i
, ncopy
, csize
;
94 struct r600_resource
*rdst
= r600_resource(dst
);
96 if (!cs
|| offset
% 4 != 0 || size
% 4 != 0) {
97 ctx
->clear_buffer(ctx
, dst
, offset
, size
, &clear_value
, 4);
101 /* Mark the buffer range of destination as valid (initialized),
102 * so that transfer_map knows it should wait for the GPU when mapping
104 util_range_add(&rdst
->valid_buffer_range
, offset
, offset
+ size
);
106 offset
+= rdst
->gpu_address
;
108 /* the same maximum size as for copying */
109 ncopy
= DIV_ROUND_UP(size
, CIK_SDMA_COPY_MAX_SIZE
);
110 r600_need_dma_space(&sctx
->b
, ncopy
* 5, rdst
, NULL
);
112 for (i
= 0; i
< ncopy
; i
++) {
113 csize
= MIN2(size
, CIK_SDMA_COPY_MAX_SIZE
);
114 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_PACKET_CONSTANT_FILL
, 0,
115 0x8000 /* dword copy */));
116 radeon_emit(cs
, offset
);
117 radeon_emit(cs
, offset
>> 32);
118 radeon_emit(cs
, clear_value
);
119 radeon_emit(cs
, csize
);
123 r600_dma_emit_wait_idle(&sctx
->b
);
126 static unsigned minify_as_blocks(unsigned width
, unsigned level
, unsigned blk_w
)
128 width
= u_minify(width
, level
);
129 return DIV_ROUND_UP(width
, blk_w
);
132 static unsigned encode_tile_info(struct si_context
*sctx
,
133 struct r600_texture
*tex
, unsigned level
,
136 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
137 unsigned tile_index
= tex
->surface
.tiling_index
[level
];
138 unsigned macro_tile_index
= tex
->surface
.macro_tile_index
;
139 unsigned tile_mode
= info
->si_tile_mode_array
[tile_index
];
140 unsigned macro_tile_mode
= info
->cik_macrotile_mode_array
[macro_tile_index
];
142 return (set_bpp
? util_logbase2(tex
->surface
.bpe
) : 0) |
143 (G_009910_ARRAY_MODE(tile_mode
) << 3) |
144 (G_009910_MICRO_TILE_MODE_NEW(tile_mode
) << 8) |
145 /* Non-depth modes don't have TILE_SPLIT set. */
146 ((util_logbase2(tex
->surface
.tile_split
>> 6)) << 11) |
147 (G_009990_BANK_WIDTH(macro_tile_mode
) << 15) |
148 (G_009990_BANK_HEIGHT(macro_tile_mode
) << 18) |
149 (G_009990_NUM_BANKS(macro_tile_mode
) << 21) |
150 (G_009990_MACRO_TILE_ASPECT(macro_tile_mode
) << 24) |
151 (G_009910_PIPE_CONFIG(tile_mode
) << 26);
154 static bool cik_sdma_copy_texture(struct si_context
*sctx
,
155 struct pipe_resource
*dst
,
157 unsigned dstx
, unsigned dsty
, unsigned dstz
,
158 struct pipe_resource
*src
,
160 const struct pipe_box
*src_box
)
162 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
163 struct r600_texture
*rsrc
= (struct r600_texture
*)src
;
164 struct r600_texture
*rdst
= (struct r600_texture
*)dst
;
165 unsigned bpp
= rdst
->surface
.bpe
;
166 uint64_t dst_address
= rdst
->resource
.gpu_address
+
167 rdst
->surface
.level
[dst_level
].offset
;
168 uint64_t src_address
= rsrc
->resource
.gpu_address
+
169 rsrc
->surface
.level
[src_level
].offset
;
170 unsigned dst_mode
= rdst
->surface
.level
[dst_level
].mode
;
171 unsigned src_mode
= rsrc
->surface
.level
[src_level
].mode
;
172 unsigned dst_tile_index
= rdst
->surface
.tiling_index
[dst_level
];
173 unsigned src_tile_index
= rsrc
->surface
.tiling_index
[src_level
];
174 unsigned dst_tile_mode
= info
->si_tile_mode_array
[dst_tile_index
];
175 unsigned src_tile_mode
= info
->si_tile_mode_array
[src_tile_index
];
176 unsigned dst_micro_mode
= G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode
);
177 unsigned src_micro_mode
= G_009910_MICRO_TILE_MODE_NEW(src_tile_mode
);
178 unsigned dst_pitch
= rdst
->surface
.level
[dst_level
].nblk_x
;
179 unsigned src_pitch
= rsrc
->surface
.level
[src_level
].nblk_x
;
180 uint64_t dst_slice_pitch
= rdst
->surface
.level
[dst_level
].slice_size
/ bpp
;
181 uint64_t src_slice_pitch
= rsrc
->surface
.level
[src_level
].slice_size
/ bpp
;
182 unsigned dst_width
= minify_as_blocks(rdst
->resource
.b
.b
.width0
,
183 dst_level
, rdst
->surface
.blk_w
);
184 unsigned src_width
= minify_as_blocks(rsrc
->resource
.b
.b
.width0
,
185 src_level
, rsrc
->surface
.blk_w
);
186 unsigned dst_height
= minify_as_blocks(rdst
->resource
.b
.b
.height0
,
187 dst_level
, rdst
->surface
.blk_h
);
188 unsigned src_height
= minify_as_blocks(rsrc
->resource
.b
.b
.height0
,
189 src_level
, rsrc
->surface
.blk_h
);
190 unsigned srcx
= src_box
->x
/ rsrc
->surface
.blk_w
;
191 unsigned srcy
= src_box
->y
/ rsrc
->surface
.blk_h
;
192 unsigned srcz
= src_box
->z
;
193 unsigned copy_width
= DIV_ROUND_UP(src_box
->width
, rsrc
->surface
.blk_w
);
194 unsigned copy_height
= DIV_ROUND_UP(src_box
->height
, rsrc
->surface
.blk_h
);
195 unsigned copy_depth
= src_box
->depth
;
197 assert(src_level
<= src
->last_level
);
198 assert(dst_level
<= dst
->last_level
);
199 assert(rdst
->surface
.level
[dst_level
].offset
+
200 dst_slice_pitch
* bpp
* (dstz
+ src_box
->depth
) <=
201 rdst
->resource
.buf
->size
);
202 assert(rsrc
->surface
.level
[src_level
].offset
+
203 src_slice_pitch
* bpp
* (srcz
+ src_box
->depth
) <=
204 rsrc
->resource
.buf
->size
);
206 if (!r600_prepare_for_dma_blit(&sctx
->b
, rdst
, dst_level
, dstx
, dsty
,
207 dstz
, rsrc
, src_level
, src_box
))
210 dstx
/= rdst
->surface
.blk_w
;
211 dsty
/= rdst
->surface
.blk_h
;
213 if (srcx
>= (1 << 14) ||
221 /* Linear -> linear sub-window copy. */
222 if (dst_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
&&
223 src_mode
== RADEON_SURF_MODE_LINEAR_ALIGNED
&&
224 /* check if everything fits into the bitfields */
225 src_pitch
<= (1 << 14) &&
226 dst_pitch
<= (1 << 14) &&
227 src_slice_pitch
<= (1 << 28) &&
228 dst_slice_pitch
<= (1 << 28) &&
229 copy_width
<= (1 << 14) &&
230 copy_height
<= (1 << 14) &&
231 copy_depth
<= (1 << 11) &&
232 /* HW limitation - CIK: */
233 (sctx
->b
.chip_class
!= CIK
||
234 (copy_width
< (1 << 14) &&
235 copy_height
< (1 << 14) &&
236 copy_depth
< (1 << 11))) &&
237 /* HW limitation - some CIK parts: */
238 ((sctx
->b
.family
!= CHIP_BONAIRE
&&
239 sctx
->b
.family
!= CHIP_KAVERI
) ||
240 (srcx
+ copy_width
!= (1 << 14) &&
241 srcy
+ copy_height
!= (1 << 14)))) {
242 struct radeon_winsys_cs
*cs
= sctx
->b
.dma
.cs
;
244 r600_need_dma_space(&sctx
->b
, 13, &rdst
->resource
, &rsrc
->resource
);
246 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
247 CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW
, 0) |
248 (util_logbase2(bpp
) << 29));
249 radeon_emit(cs
, src_address
);
250 radeon_emit(cs
, src_address
>> 32);
251 radeon_emit(cs
, srcx
| (srcy
<< 16));
252 radeon_emit(cs
, srcz
| ((src_pitch
- 1) << 16));
253 radeon_emit(cs
, src_slice_pitch
- 1);
254 radeon_emit(cs
, dst_address
);
255 radeon_emit(cs
, dst_address
>> 32);
256 radeon_emit(cs
, dstx
| (dsty
<< 16));
257 radeon_emit(cs
, dstz
| ((dst_pitch
- 1) << 16));
258 radeon_emit(cs
, dst_slice_pitch
- 1);
259 if (sctx
->b
.chip_class
== CIK
) {
260 radeon_emit(cs
, copy_width
| (copy_height
<< 16));
261 radeon_emit(cs
, copy_depth
);
263 radeon_emit(cs
, (copy_width
- 1) | ((copy_height
- 1) << 16));
264 radeon_emit(cs
, (copy_depth
- 1));
267 r600_dma_emit_wait_idle(&sctx
->b
);
271 /* Tiled <-> linear sub-window copy. */
272 if ((src_mode
>= RADEON_SURF_MODE_1D
) != (dst_mode
>= RADEON_SURF_MODE_1D
)) {
273 struct r600_texture
*tiled
= src_mode
>= RADEON_SURF_MODE_1D
? rsrc
: rdst
;
274 struct r600_texture
*linear
= tiled
== rsrc
? rdst
: rsrc
;
275 unsigned tiled_level
= tiled
== rsrc
? src_level
: dst_level
;
276 unsigned linear_level
= linear
== rsrc
? src_level
: dst_level
;
277 unsigned tiled_x
= tiled
== rsrc
? srcx
: dstx
;
278 unsigned linear_x
= linear
== rsrc
? srcx
: dstx
;
279 unsigned tiled_y
= tiled
== rsrc
? srcy
: dsty
;
280 unsigned linear_y
= linear
== rsrc
? srcy
: dsty
;
281 unsigned tiled_z
= tiled
== rsrc
? srcz
: dstz
;
282 unsigned linear_z
= linear
== rsrc
? srcz
: dstz
;
283 unsigned tiled_width
= tiled
== rsrc
? src_width
: dst_width
;
284 unsigned linear_width
= linear
== rsrc
? src_width
: dst_width
;
285 unsigned tiled_pitch
= tiled
== rsrc
? src_pitch
: dst_pitch
;
286 unsigned linear_pitch
= linear
== rsrc
? src_pitch
: dst_pitch
;
287 unsigned tiled_slice_pitch
= tiled
== rsrc
? src_slice_pitch
: dst_slice_pitch
;
288 unsigned linear_slice_pitch
= linear
== rsrc
? src_slice_pitch
: dst_slice_pitch
;
289 uint64_t tiled_address
= tiled
== rsrc
? src_address
: dst_address
;
290 uint64_t linear_address
= linear
== rsrc
? src_address
: dst_address
;
291 unsigned tiled_micro_mode
= tiled
== rsrc
? src_micro_mode
: dst_micro_mode
;
293 assert(tiled_pitch
% 8 == 0);
294 assert(tiled_slice_pitch
% 64 == 0);
295 unsigned pitch_tile_max
= tiled_pitch
/ 8 - 1;
296 unsigned slice_tile_max
= tiled_slice_pitch
/ 64 - 1;
297 unsigned xalign
= MAX2(1, 4 / bpp
);
298 unsigned copy_width_aligned
= copy_width
;
300 /* If the region ends at the last pixel and is unaligned, we
301 * can copy the remainder of the line that is not visible to
304 if (copy_width
% xalign
!= 0 &&
305 linear_x
+ copy_width
== linear_width
&&
306 tiled_x
+ copy_width
== tiled_width
&&
307 linear_x
+ align(copy_width
, xalign
) <= linear_pitch
&&
308 tiled_x
+ align(copy_width
, xalign
) <= tiled_pitch
)
309 copy_width_aligned
= align(copy_width
, xalign
);
311 /* HW limitations. */
312 if ((sctx
->b
.family
== CHIP_BONAIRE
||
313 sctx
->b
.family
== CHIP_KAVERI
) &&
314 linear_pitch
- 1 == 0x3fff &&
318 if (sctx
->b
.chip_class
== CIK
&&
319 (copy_width_aligned
== (1 << 14) ||
320 copy_height
== (1 << 14) ||
321 copy_depth
== (1 << 11)))
324 if ((sctx
->b
.family
== CHIP_BONAIRE
||
325 sctx
->b
.family
== CHIP_KAVERI
||
326 sctx
->b
.family
== CHIP_KABINI
||
327 sctx
->b
.family
== CHIP_MULLINS
) &&
328 (tiled_x
+ copy_width
== (1 << 14) ||
329 tiled_y
+ copy_height
== (1 << 14)))
332 /* The hw can read outside of the given linear buffer bounds,
333 * or access those pages but not touch the memory in case
334 * of writes. (it still causes a VM fault)
336 * Out-of-bounds memory access or page directory access must
339 int64_t start_linear_address
, end_linear_address
;
340 unsigned granularity
;
342 /* Deduce the size of reads from the linear surface. */
343 switch (tiled_micro_mode
) {
344 case V_009910_ADDR_SURF_DISPLAY_MICRO_TILING
:
345 granularity
= bpp
== 1 ? 64 / (8*bpp
) :
348 case V_009910_ADDR_SURF_THIN_MICRO_TILING
:
349 case V_009910_ADDR_SURF_DEPTH_MICRO_TILING
:
350 if (0 /* TODO: THICK microtiling */)
351 granularity
= bpp
== 1 ? 32 / (8*bpp
) :
352 bpp
== 2 ? 64 / (8*bpp
) :
353 bpp
<= 8 ? 128 / (8*bpp
) :
356 granularity
= bpp
<= 2 ? 64 / (8*bpp
) :
357 bpp
<= 8 ? 128 / (8*bpp
) :
364 /* The linear reads start at tiled_x & ~(granularity - 1).
365 * If linear_x == 0 && tiled_x % granularity != 0, the hw
366 * starts reading from an address preceding linear_address!!!
368 start_linear_address
=
369 linear
->surface
.level
[linear_level
].offset
+
370 bpp
* (linear_z
* linear_slice_pitch
+
371 linear_y
* linear_pitch
+
373 start_linear_address
-= (int)(bpp
* (tiled_x
% granularity
));
376 linear
->surface
.level
[linear_level
].offset
+
377 bpp
* ((linear_z
+ copy_depth
- 1) * linear_slice_pitch
+
378 (linear_y
+ copy_height
- 1) * linear_pitch
+
379 (linear_x
+ copy_width
));
381 if ((tiled_x
+ copy_width
) % granularity
)
382 end_linear_address
+= granularity
-
383 (tiled_x
+ copy_width
) % granularity
;
385 if (start_linear_address
< 0 ||
386 end_linear_address
> linear
->surface
.surf_size
)
389 /* Check requirements. */
390 if (tiled_address
% 256 == 0 &&
391 linear_address
% 4 == 0 &&
392 linear_pitch
% xalign
== 0 &&
393 linear_x
% xalign
== 0 &&
394 tiled_x
% xalign
== 0 &&
395 copy_width_aligned
% xalign
== 0 &&
396 tiled_micro_mode
!= V_009910_ADDR_SURF_ROTATED_MICRO_TILING
&&
397 /* check if everything fits into the bitfields */
398 tiled
->surface
.tile_split
<= 4096 &&
399 pitch_tile_max
< (1 << 11) &&
400 slice_tile_max
< (1 << 22) &&
401 linear_pitch
<= (1 << 14) &&
402 linear_slice_pitch
<= (1 << 28) &&
403 copy_width_aligned
<= (1 << 14) &&
404 copy_height
<= (1 << 14) &&
405 copy_depth
<= (1 << 11)) {
406 struct radeon_winsys_cs
*cs
= sctx
->b
.dma
.cs
;
407 uint32_t direction
= linear
== rdst
? 1u << 31 : 0;
409 r600_need_dma_space(&sctx
->b
, 14, &rdst
->resource
, &rsrc
->resource
);
411 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
412 CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW
, 0) |
414 radeon_emit(cs
, tiled_address
);
415 radeon_emit(cs
, tiled_address
>> 32);
416 radeon_emit(cs
, tiled_x
| (tiled_y
<< 16));
417 radeon_emit(cs
, tiled_z
| (pitch_tile_max
<< 16));
418 radeon_emit(cs
, slice_tile_max
);
419 radeon_emit(cs
, encode_tile_info(sctx
, tiled
, tiled_level
, true));
420 radeon_emit(cs
, linear_address
);
421 radeon_emit(cs
, linear_address
>> 32);
422 radeon_emit(cs
, linear_x
| (linear_y
<< 16));
423 radeon_emit(cs
, linear_z
| ((linear_pitch
- 1) << 16));
424 radeon_emit(cs
, linear_slice_pitch
- 1);
425 if (sctx
->b
.chip_class
== CIK
) {
426 radeon_emit(cs
, copy_width_aligned
| (copy_height
<< 16));
427 radeon_emit(cs
, copy_depth
);
429 radeon_emit(cs
, (copy_width_aligned
- 1) | ((copy_height
- 1) << 16));
430 radeon_emit(cs
, (copy_depth
- 1));
433 r600_dma_emit_wait_idle(&sctx
->b
);
438 /* Tiled -> Tiled sub-window copy. */
439 if (dst_mode
>= RADEON_SURF_MODE_1D
&&
440 src_mode
>= RADEON_SURF_MODE_1D
&&
441 /* check if these fit into the bitfields */
442 src_address
% 256 == 0 &&
443 dst_address
% 256 == 0 &&
444 rsrc
->surface
.tile_split
<= 4096 &&
445 rdst
->surface
.tile_split
<= 4096 &&
450 /* this can either be equal, or display->rotated (VI only) */
451 (src_micro_mode
== dst_micro_mode
||
452 (sctx
->b
.chip_class
== VI
&&
453 src_micro_mode
== V_009910_ADDR_SURF_DISPLAY_MICRO_TILING
&&
454 dst_micro_mode
== V_009910_ADDR_SURF_ROTATED_MICRO_TILING
))) {
455 assert(src_pitch
% 8 == 0);
456 assert(dst_pitch
% 8 == 0);
457 assert(src_slice_pitch
% 64 == 0);
458 assert(dst_slice_pitch
% 64 == 0);
459 unsigned src_pitch_tile_max
= src_pitch
/ 8 - 1;
460 unsigned dst_pitch_tile_max
= dst_pitch
/ 8 - 1;
461 unsigned src_slice_tile_max
= src_slice_pitch
/ 64 - 1;
462 unsigned dst_slice_tile_max
= dst_slice_pitch
/ 64 - 1;
463 unsigned copy_width_aligned
= copy_width
;
464 unsigned copy_height_aligned
= copy_height
;
466 /* If the region ends at the last pixel and is unaligned, we
467 * can copy the remainder of the tile that is not visible to
470 if (copy_width
% 8 != 0 &&
471 srcx
+ copy_width
== src_width
&&
472 dstx
+ copy_width
== dst_width
)
473 copy_width_aligned
= align(copy_width
, 8);
475 if (copy_height
% 8 != 0 &&
476 srcy
+ copy_height
== src_height
&&
477 dsty
+ copy_height
== dst_height
)
478 copy_height_aligned
= align(copy_height
, 8);
480 /* check if these fit into the bitfields */
481 if (src_pitch_tile_max
< (1 << 11) &&
482 dst_pitch_tile_max
< (1 << 11) &&
483 src_slice_tile_max
< (1 << 22) &&
484 dst_slice_tile_max
< (1 << 22) &&
485 copy_width_aligned
<= (1 << 14) &&
486 copy_height_aligned
<= (1 << 14) &&
487 copy_depth
<= (1 << 11) &&
488 copy_width_aligned
% 8 == 0 &&
489 copy_height_aligned
% 8 == 0 &&
490 /* HW limitation - CIK: */
491 (sctx
->b
.chip_class
!= CIK
||
492 (copy_width_aligned
< (1 << 14) &&
493 copy_height_aligned
< (1 << 14) &&
494 copy_depth
< (1 << 11))) &&
495 /* HW limitation - some CIK parts: */
496 ((sctx
->b
.family
!= CHIP_BONAIRE
&&
497 sctx
->b
.family
!= CHIP_KAVERI
&&
498 sctx
->b
.family
!= CHIP_KABINI
&&
499 sctx
->b
.family
!= CHIP_MULLINS
) ||
500 (srcx
+ copy_width_aligned
!= (1 << 14) &&
501 srcy
+ copy_height_aligned
!= (1 << 14) &&
502 dstx
+ copy_width
!= (1 << 14)))) {
503 struct radeon_winsys_cs
*cs
= sctx
->b
.dma
.cs
;
505 r600_need_dma_space(&sctx
->b
, 15, &rdst
->resource
, &rsrc
->resource
);
507 radeon_emit(cs
, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY
,
508 CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW
, 0));
509 radeon_emit(cs
, src_address
);
510 radeon_emit(cs
, src_address
>> 32);
511 radeon_emit(cs
, srcx
| (srcy
<< 16));
512 radeon_emit(cs
, srcz
| (src_pitch_tile_max
<< 16));
513 radeon_emit(cs
, src_slice_tile_max
);
514 radeon_emit(cs
, encode_tile_info(sctx
, rsrc
, src_level
, true));
515 radeon_emit(cs
, dst_address
);
516 radeon_emit(cs
, dst_address
>> 32);
517 radeon_emit(cs
, dstx
| (dsty
<< 16));
518 radeon_emit(cs
, dstz
| (dst_pitch_tile_max
<< 16));
519 radeon_emit(cs
, dst_slice_tile_max
);
520 radeon_emit(cs
, encode_tile_info(sctx
, rdst
, dst_level
, false));
521 if (sctx
->b
.chip_class
== CIK
) {
522 radeon_emit(cs
, copy_width_aligned
|
523 (copy_height_aligned
<< 16));
524 radeon_emit(cs
, copy_depth
);
526 radeon_emit(cs
, (copy_width_aligned
- 8) |
527 ((copy_height_aligned
- 8) << 16));
528 radeon_emit(cs
, (copy_depth
- 1));
531 r600_dma_emit_wait_idle(&sctx
->b
);
539 static void cik_sdma_copy(struct pipe_context
*ctx
,
540 struct pipe_resource
*dst
,
542 unsigned dstx
, unsigned dsty
, unsigned dstz
,
543 struct pipe_resource
*src
,
545 const struct pipe_box
*src_box
)
547 struct si_context
*sctx
= (struct si_context
*)ctx
;
552 if (dst
->target
== PIPE_BUFFER
&& src
->target
== PIPE_BUFFER
) {
553 cik_sdma_copy_buffer(sctx
, dst
, src
, dstx
, src_box
->x
, src_box
->width
);
557 if (cik_sdma_copy_texture(sctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
558 src
, src_level
, src_box
))
562 si_resource_copy_region(ctx
, dst
, dst_level
, dstx
, dsty
, dstz
,
563 src
, src_level
, src_box
);
566 void cik_init_sdma_functions(struct si_context
*sctx
)
568 sctx
->b
.dma_copy
= cik_sdma_copy
;
569 sctx
->b
.dma_clear_buffer
= cik_sdma_clear_buffer
;