src/gallium/drivers/radeonsi/cik_sdma.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  * Copyright 2014,2015 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Jerome Glisse
  26  */
  27
  28 #include "sid.h"
  29 #include "si_pipe.h"
  30 #include "radeon/r600_cs.h"
  31
  32 #include "util/u_format.h"
  33
  34 static uint32_t cik_micro_tile_mode(struct si_screen *sscreen, unsigned tile_mode)
  35 {
  36         if (sscreen->b.info.si_tile_mode_array_valid) {
  37                 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
  38
  39                 return G_009910_MICRO_TILE_MODE_NEW(gb_tile_mode);
  40         }
  41
  42         /* The kernel cannod return the tile mode array. Guess? */
  43         return V_009910_ADDR_SURF_THIN_MICRO_TILING;
  44 }
  45
  46 static void cik_sdma_do_copy_buffer(struct si_context *ctx,
  47                                     struct pipe_resource *dst,
  48                                     struct pipe_resource *src,
  49                                     uint64_t dst_offset,
  50                                     uint64_t src_offset,
  51                                     uint64_t size)
  52 {
  53         struct radeon_winsys_cs *cs = ctx->b.dma.cs;
  54         unsigned i, ncopy, csize;
  55         struct r600_resource *rdst = (struct r600_resource*)dst;
  56         struct r600_resource *rsrc = (struct r600_resource*)src;
  57
  58         dst_offset += r600_resource(dst)->gpu_address;
  59         src_offset += r600_resource(src)->gpu_address;
  60
  61         ncopy = (size + CIK_SDMA_COPY_MAX_SIZE - 1) / CIK_SDMA_COPY_MAX_SIZE;
  62         r600_need_dma_space(&ctx->b, ncopy * 7);
  63
  64         radeon_add_to_buffer_list(&ctx->b, &ctx->b.dma, rsrc, RADEON_USAGE_READ,
  65                               RADEON_PRIO_SDMA_BUFFER);
  66         radeon_add_to_buffer_list(&ctx->b, &ctx->b.dma, rdst, RADEON_USAGE_WRITE,
  67                               RADEON_PRIO_SDMA_BUFFER);
  68
  69         for (i = 0; i < ncopy; i++) {
  70                 csize = size < CIK_SDMA_COPY_MAX_SIZE ? size : CIK_SDMA_COPY_MAX_SIZE;
  71                 cs->buf[cs->cdw++] = CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
  72                                                      CIK_SDMA_COPY_SUB_OPCODE_LINEAR,
  73                                                      0);
  74                 cs->buf[cs->cdw++] = csize;
  75                 cs->buf[cs->cdw++] = 0; /* src/dst endian swap */
  76                 cs->buf[cs->cdw++] = src_offset;
  77                 cs->buf[cs->cdw++] = src_offset >> 32;
  78                 cs->buf[cs->cdw++] = dst_offset;
  79                 cs->buf[cs->cdw++] = dst_offset >> 32;
  80                 dst_offset += csize;
  81                 src_offset += csize;
  82                 size -= csize;
  83         }
  84 }
  85
  86 static void cik_sdma_copy_buffer(struct si_context *ctx,
  87                                  struct pipe_resource *dst,
  88                                  struct pipe_resource *src,
  89                                  uint64_t dst_offset,
  90                                  uint64_t src_offset,
  91                                  uint64_t size)
  92 {
  93         struct r600_resource *rdst = (struct r600_resource*)dst;
  94
  95         /* Mark the buffer range of destination as valid (initialized),
  96          * so that transfer_map knows it should wait for the GPU when mapping
  97          * that range. */
  98         util_range_add(&rdst->valid_buffer_range, dst_offset,
  99                        dst_offset + size);
 100
 101         cik_sdma_do_copy_buffer(ctx, dst, src, dst_offset, src_offset, size);
 102 }
 103
 104 static void cik_sdma_copy_tile(struct si_context *ctx,
 105                                struct pipe_resource *dst,
 106                                unsigned dst_level,
 107                                struct pipe_resource *src,
 108                                unsigned src_level,
 109                                unsigned y,
 110                                unsigned copy_height,
 111                                unsigned y_align,
 112                                unsigned pitch,
 113                                unsigned bpe)
 114 {
 115         struct radeon_winsys_cs *cs = ctx->b.dma.cs;
 116         struct si_screen *sscreen = ctx->screen;
 117         struct r600_texture *rsrc = (struct r600_texture*)src;
 118         struct r600_texture *rdst = (struct r600_texture*)dst;
 119         struct r600_texture *rlinear, *rtiled;
 120         unsigned linear_lvl, tiled_lvl;
 121         unsigned array_mode, lbpe, pitch_tile_max, slice_tile_max, size;
 122         unsigned ncopy, height, cheight, detile, i, src_mode, dst_mode;
 123         unsigned sub_op, bank_h, bank_w, mt_aspect, nbanks, tile_split, mt;
 124         uint64_t base, addr;
 125         unsigned pipe_config, tile_mode_index;
 126
 127         dst_mode = rdst->surface.level[dst_level].mode;
 128         src_mode = rsrc->surface.level[src_level].mode;
 129         /* downcast linear aligned to linear to simplify test */
 130         src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
 131         dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
 132         assert(dst_mode != src_mode);
 133         assert(src_mode == RADEON_SURF_MODE_LINEAR || dst_mode == RADEON_SURF_MODE_LINEAR);
 134
 135         sub_op = CIK_SDMA_COPY_SUB_OPCODE_TILED;
 136         lbpe = util_logbase2(bpe);
 137         pitch_tile_max = ((pitch / bpe) / 8) - 1;
 138
 139         detile = dst_mode == RADEON_SURF_MODE_LINEAR;
 140         rlinear = detile ? rdst : rsrc;
 141         rtiled = detile ? rsrc : rdst;
 142         linear_lvl = detile ? dst_level : src_level;
 143         tiled_lvl = detile ? src_level : dst_level;
 144
 145         assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format));
 146
 147         array_mode = si_array_mode(rtiled->surface.level[tiled_lvl].mode);
 148         slice_tile_max = (rtiled->surface.level[tiled_lvl].nblk_x *
 149                           rtiled->surface.level[tiled_lvl].nblk_y) / (8*8) - 1;
 150         height = rlinear->surface.level[linear_lvl].nblk_y;
 151         base = rtiled->surface.level[tiled_lvl].offset;
 152         addr = rlinear->surface.level[linear_lvl].offset;
 153         bank_h = cik_bank_wh(rtiled->surface.bankh);
 154         bank_w = cik_bank_wh(rtiled->surface.bankw);
 155         mt_aspect = cik_macro_tile_aspect(rtiled->surface.mtilea);
 156         tile_split = cik_tile_split(rtiled->surface.tile_split);
 157         tile_mode_index = si_tile_mode_index(rtiled, tiled_lvl, false);
 158         nbanks = si_num_banks(sscreen, rtiled);
 159         base += rtiled->resource.gpu_address;
 160         addr += rlinear->resource.gpu_address;
 161
 162         pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
 163         mt = cik_micro_tile_mode(sscreen, tile_mode_index);
 164
 165         size = (copy_height * pitch) / 4;
 166         cheight = copy_height;
 167         if (((cheight * pitch) / 4) > CIK_SDMA_COPY_MAX_SIZE) {
 168                 cheight = (CIK_SDMA_COPY_MAX_SIZE * 4) / pitch;
 169                 cheight &= ~(y_align - 1);
 170         }
 171         ncopy = (copy_height + cheight - 1) / cheight;
 172         r600_need_dma_space(&ctx->b, ncopy * 12);
 173
 174         radeon_add_to_buffer_list(&ctx->b, &ctx->b.dma, &rsrc->resource,
 175                               RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE);
 176         radeon_add_to_buffer_list(&ctx->b, &ctx->b.dma, &rdst->resource,
 177                               RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE);
 178
 179         copy_height = size * 4 / pitch;
 180         for (i = 0; i < ncopy; i++) {
 181                 cheight = copy_height;
 182                 if (((cheight * pitch) / 4) > CIK_SDMA_COPY_MAX_SIZE) {
 183                         cheight = (CIK_SDMA_COPY_MAX_SIZE * 4) / pitch;
 184                         cheight &= ~(y_align - 1);
 185                 }
 186                 size = (cheight * pitch) / 4;
 187
 188                 cs->buf[cs->cdw++] = CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
 189                                                      sub_op, detile << 15);
 190                 cs->buf[cs->cdw++] = base;
 191                 cs->buf[cs->cdw++] = base >> 32;
 192                 cs->buf[cs->cdw++] = ((height - 1) << 16) | pitch_tile_max;
 193                 cs->buf[cs->cdw++] = slice_tile_max;
 194                 cs->buf[cs->cdw++] = (pipe_config << 26) | (mt_aspect << 24) |
 195                         (nbanks << 21) | (bank_h << 18) | (bank_w << 15) |
 196                         (tile_split << 11) | (mt << 8) | (array_mode << 3) |
 197                         lbpe;
 198                 cs->buf[cs->cdw++] = y << 16; /* | x */
 199                 cs->buf[cs->cdw++] = 0; /* z */
 200                 cs->buf[cs->cdw++] = addr & 0xfffffffc;
 201                 cs->buf[cs->cdw++] = addr >> 32;
 202                 cs->buf[cs->cdw++] = (pitch / bpe) - 1;
 203                 cs->buf[cs->cdw++] = size;
 204
 205                 copy_height -= cheight;
 206                 y += cheight;
 207         }
 208 }
 209
 210 void cik_sdma_copy(struct pipe_context *ctx,
 211                    struct pipe_resource *dst,
 212                    unsigned dst_level,
 213                    unsigned dstx, unsigned dsty, unsigned dstz,
 214                    struct pipe_resource *src,
 215                    unsigned src_level,
 216                    const struct pipe_box *src_box)
 217 {
 218         struct si_context *sctx = (struct si_context *)ctx;
 219         struct r600_texture *rsrc = (struct r600_texture*)src;
 220         struct r600_texture *rdst = (struct r600_texture*)dst;
 221         unsigned dst_pitch, src_pitch, bpe, dst_mode, src_mode;
 222         unsigned src_w, dst_w;
 223         unsigned src_x, src_y;
 224         unsigned copy_height, y_align;
 225         unsigned dst_x = dstx, dst_y = dsty, dst_z = dstz;
 226
 227         if (sctx->b.dma.cs == NULL) {
 228                 goto fallback;
 229         }
 230
 231         if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
 232                 cik_sdma_copy_buffer(sctx, dst, src, dst_x, src_box->x, src_box->width);
 233                 return;
 234         }
 235
 236         /* Before re-enabling this, please make sure you can hit all newly
 237          * enabled paths in your testing, preferably with both piglit (in
 238          * particular the streaming-texture-leak test) and real world apps
 239          * (e.g. the UE4 Elemental demo).
 240          */
 241         goto fallback;
 242
 243         if (src->format != dst->format ||
 244             rdst->surface.nsamples > 1 || rsrc->surface.nsamples > 1 ||
 245             (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level) ||
 246             rdst->dcc_buffer || rsrc->dcc_buffer) {
 247                 goto fallback;
 248         }
 249
 250         if (rsrc->dirty_level_mask & (1 << src_level)) {
 251                 if (rsrc->htile_buffer)
 252                         goto fallback;
 253
 254                 ctx->flush_resource(ctx, src);
 255         }
 256
 257         src_x = util_format_get_nblocksx(src->format, src_box->x);
 258         dst_x = util_format_get_nblocksx(src->format, dst_x);
 259         src_y = util_format_get_nblocksy(src->format, src_box->y);
 260         dst_y = util_format_get_nblocksy(src->format, dst_y);
 261
 262         dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
 263         src_pitch = rsrc->surface.level[src_level].pitch_bytes;
 264         src_w = rsrc->surface.level[src_level].npix_x;
 265         dst_w = rdst->surface.level[dst_level].npix_x;
 266
 267         if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w ||
 268             src_box->width != src_w ||
 269             rsrc->surface.level[src_level].nblk_y !=
 270             rdst->surface.level[dst_level].nblk_y) {
 271                 /* FIXME CIK can do partial blit */
 272                 goto fallback;
 273         }
 274
 275         bpe = rdst->surface.bpe;
 276         copy_height = src_box->height / rsrc->surface.blk_h;
 277         dst_mode = rdst->surface.level[dst_level].mode;
 278         src_mode = rsrc->surface.level[src_level].mode;
 279         /* downcast linear aligned to linear to simplify test */
 280         src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode;
 281         dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode;
 282
 283         /* Dimensions must be aligned to (macro)tiles */
 284         switch (src_mode == RADEON_SURF_MODE_LINEAR ? dst_mode : src_mode) {
 285         case RADEON_SURF_MODE_1D:
 286                 if ((src_x % 8) || (src_y % 8) || (dst_x % 8) || (dst_y % 8) ||
 287                     (copy_height % 8))
 288                         goto fallback;
 289                 y_align = 8;
 290                 break;
 291         case RADEON_SURF_MODE_2D: {
 292                 unsigned mtilew, mtileh, num_banks;
 293
 294                         switch (si_num_banks(sctx->screen, rsrc)) {
 295                         case V_02803C_ADDR_SURF_2_BANK:
 296                         default:
 297                                 num_banks = 2;
 298                                 break;
 299                         case V_02803C_ADDR_SURF_4_BANK:
 300                                 num_banks = 4;
 301                                 break;
 302                         case V_02803C_ADDR_SURF_8_BANK:
 303                                 num_banks = 8;
 304                                 break;
 305                         case V_02803C_ADDR_SURF_16_BANK:
 306                                 num_banks = 16;
 307                                 break;
 308                         }
 309
 310                         mtilew = (8 * rsrc->surface.bankw *
 311                                   sctx->screen->b.tiling_info.num_channels) *
 312                                 rsrc->surface.mtilea;
 313                         assert(!(mtilew & (mtilew - 1)));
 314                         mtileh = (8 * rsrc->surface.bankh * num_banks) /
 315                                 rsrc->surface.mtilea;
 316                         assert(!(mtileh & (mtileh - 1)));
 317
 318                         if ((src_x & (mtilew - 1)) || (src_y & (mtileh - 1)) ||
 319                             (dst_x & (mtilew - 1)) || (dst_y & (mtileh - 1)) ||
 320                             (copy_height & (mtileh - 1)))
 321                                 goto fallback;
 322
 323                         y_align = mtileh;
 324                         break;
 325         }
 326         default:
 327                 y_align = 1;
 328         }
 329
 330         if (src_mode == dst_mode) {
 331                 uint64_t dst_offset, src_offset;
 332                 unsigned src_h, dst_h;
 333
 334                 src_h = rsrc->surface.level[src_level].npix_y;
 335                 dst_h = rdst->surface.level[dst_level].npix_y;
 336
 337                 if (src_box->depth > 1 &&
 338                     (src_y || dst_y || src_h != dst_h || src_box->height != src_h))
 339                         goto fallback;
 340
 341                 /* simple dma blit would do NOTE code here assume :
 342                  *   dst_pitch == src_pitch
 343                  */
 344                 src_offset= rsrc->surface.level[src_level].offset;
 345                 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
 346                 src_offset += src_y * src_pitch + src_x * bpe;
 347                 dst_offset = rdst->surface.level[dst_level].offset;
 348                 dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
 349                 dst_offset += dst_y * dst_pitch + dst_x * bpe;
 350                 cik_sdma_do_copy_buffer(sctx, dst, src, dst_offset, src_offset,
 351                                         src_box->depth *
 352                                         rsrc->surface.level[src_level].slice_size);
 353         } else {
 354                 if (dst_y != src_y || src_box->depth > 1 || src_box->z || dst_z)
 355                         goto fallback;
 356
 357                 cik_sdma_copy_tile(sctx, dst, dst_level, src, src_level,
 358                                    src_y, copy_height, y_align, dst_pitch, bpe);
 359         }
 360         return;
 361
 362 fallback:
 363         si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
 364                                 src, src_level, src_box);
 365 }